Power transistor and electronic device

Abstract

The utility model relates to a power transistor and electronic equipment. The power transistor comprises a substrate; the epitaxial layer is arranged on the substrate; the insulating medium layer is arranged above the epitaxial layer; the metal electrode layer is arranged above the insulating dielectric layer; the plurality of first body regions and the plurality of second body regions are arranged in the epitaxial layer, and the upper surfaces of the plurality of second body regions are flush with the upper surface of the epitaxial layer; the plurality of third body regions are arranged above the plurality of first body regions, and the upper surfaces of the plurality of third body regions are flush with the upper surface of the epitaxial layer; and the plurality of trench gates are arranged between the third body region and the second body region, and the trench gates extend downwards from the upper surface of the epitaxial layer.

Description

Technical Field

[0001] The utility model belongs to the field of semiconductor power devices, and particularly relates to a power transistor with higher reliability. Background Art

[0002] In order to improve the withstand voltage of traditional power devices, it is necessary to continuously reduce the doping concentration of the drift region and increase the thickness of the drift region, which makes the on-resistance of the device increase sharply, thereby increasing the power consumption of the system. Super junction power devices use an alternating arrangement of N-type and P-type regions in the drift region of the device to achieve a charge balance structure, which greatly improves the relationship between the on-resistance and breakdown voltage of the device and is gaining more and more attention.

[0003] At the same time, when the super junction power device is turned off, as the drain voltage increases, the N-type and P-type regions of the device will be quickly exhausted in a very short time, and the capacitance at both ends of the gate and drain and the capacitance at both ends of the drain and source will also drop rapidly, causing a drastic change in dv / dt on the drain end of the device, that is, the voltage on the drain end rises rapidly in a short time. Because of these characteristics, compared with traditional planar power devices, the advantage of super junction power devices in switching applications is that the operating frequency can be higher, but the disadvantage is that a large amount of voltage and current noise will be generated. Utility Model Content

[0004] In response to the above-mentioned problems regarding super junction power devices, an embodiment of the utility model provides a power transistor, characterized in that it includes: a substrate; an epitaxial layer, arranged on the substrate; an insulating dielectric layer, arranged above the epitaxial layer; a metal electrode layer, arranged above the insulating dielectric layer; a plurality of first body regions and a plurality of second body regions, arranged in the epitaxial layer, wherein the upper surfaces of the plurality of second body regions are flush with the upper surface of the epitaxial layer; a plurality of third body regions, arranged above the plurality of first body regions, wherein the upper surfaces of the plurality of third body regions are flush with the upper surface of the epitaxial layer; a plurality of trench gates, arranged between the third body regions and the second body regions, wherein the trench gates extend downward from the upper surface of the epitaxial layer; wherein one side of the trench gates is in direct interface contact with one side of the third body region; a plurality of heavily doped regions, arranged in the plurality of third body regions; one side of the heavily doped regions is in direct interface contact with the trench gates, and the other side of the heavily doped regions is in direct contact with a conductive via, and the conductive vias penetrate the insulating dielectric layer and extend into the third body regions. The two sides of the second body region are respectively separated from the trench gate by the epitaxial layer, and the upper surface of the second body region is in interface contact with the lower surface of the insulating dielectric layer.

[0005] It is characterized in that the multiple first body regions are in a non-floating state, and the multiple second body regions are in a floating state.

[0006] The invention is characterized in that the plurality of first body regions and the plurality of second body regions are arranged alternately.

[0007] It is characterized in that the injection window of the first body region and the injection window of the second body region are the same.

[0008] It is characterized in that the injection window of the first body region and the injection window of the second body region are different.

[0009] It is characterized in that the substrate, the epitaxial layer and the heavily doped region all have a first conductivity type.

[0010] The invention is characterized in that the doping concentration of the heavily doped region is greater than the doping concentration of the substrate and the epitaxial layer.

[0011] It is characterized in that the first body region, the second body region and the third body region all have a second conductivity type.

[0012] It is characterized in that the doping concentration of the third body region is greater than the doping concentrations of the first body region and the second body region.

[0013] Yet another embodiment of the present invention includes an electronic device, characterized in that it includes an integrated circuit at least partially formed by the power transistor as described above.

[0014] This summary is provided to introduce some concepts in a simplified form, which will be further described in the following detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The technical solution of the present application is described in detail below with reference to the accompanying drawings, wherein:

[0016] Figure 1 A schematic top view of a power transistor according to an embodiment of the utility model is shown;

[0017] Figure 2 A schematic diagram of the device structure of a part of a cell region of a power transistor according to an embodiment of the utility model is shown;

[0018] Figure 3 A schematic diagram showing the device structure of a partial cell region of a power transistor according to another embodiment of the utility model is shown;

[0019] Figure 4 A schematic diagram of the device structure of a partial cell region of a power transistor according to another embodiment of the utility model is shown.

[0020] In the drawings, the same descriptions in the various drawings indicate the same elements or parts. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0022] The accompanying drawings show various structural schematic diagrams according to embodiments of the utility model. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0023] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "under" the other layer / element when the orientation is reversed.

[0024] The present invention may be embodied in various forms, some examples of which will be described below.

[0025] According to an embodiment of the utility model, a power transistor (for example, a power transistor with a super junction structure) can be formed on a semiconductor substrate, and the semiconductor substrate can be divided into a cell region, a transition region and a terminal structure region in a lateral direction (a direction parallel to the surface of the substrate). The cell region is located in the central region of the semiconductor substrate, and a MOS structure is formed in the cell region. The terminal structure region is located in the peripheral region of the semiconductor substrate and surrounds the cell region. The transition region is formed between the cell region and the terminal structure region. Figure 1 As shown, the dotted box marks the range of the cell area, the cell area is located in the center of the device, and the surface is covered with a metal electrode 10' and a polysilicon gate 8'. A transition area and a terminal structure area are formed on the periphery of the cell area. A plurality of polysilicon strips 8a arranged at intervals are formed in the terminal structure area, and the polysilicon strips 8a are formed in a ring shape, surrounding the cell area.

[0026] Specifically, Figure 2 FIG. 1 shows a schematic diagram of a device structure of a partial cell region of a power transistor according to an embodiment of the present utility model. Figure 2As shown, the power transistor according to the embodiment of the utility model comprises: a back electrode layer 1; a substrate 2, the substrate 2 is of a first conductivity type; an epitaxial layer 3 of the first conductivity type located above the substrate, the first conductivity type is, for example, N-type. A plurality of first body regions 4a and a plurality of second body regions 4b are formed in the epitaxial layer 3, and are arranged alternately with the epitaxial layer 3. The plurality of first body regions 4a and the plurality of second body regions 4b are of the second conductivity type, and the second conductivity type is, for example, P-type. The doping concentration of the first body region 4a and the second body region 4b are the same, and the injection window of the first body region 4a and the second body region 4b are the same, that is, the width of the first body region 4a and the second body region 4b are the same. An insulating dielectric layer 10 is formed above the epitaxial layer 3, and a metal electrode layer 12 is formed above the insulating dielectric layer 10; a plurality of corresponding third body regions 5 are formed above the plurality of first body regions 4a, and the conductivity type of the third body region 5 is the same as the conductivity type of the first body region 4a, and both are of the second conductivity type, and the second conductivity type is, for example, P-type. Moreover, the doping concentration of the third body region 5 is slightly higher than the doping concentration of the first body region 4a and the second body region 4b. The upper surface of the second body region 4b and the upper surface of the third body region 5 are flush with the upper surface of the epitaxial layer. A plurality of trench gates are arranged in the epitaxial layer 3, and the trench gates include a gate oxide layer 7 and a polysilicon gate 8, and the trench gates extend downward from the upper surface of the epitaxial layer and are arranged between the third body region 5 and the second body region 4b. The trench gates are separated from the second body region 4b by the epitaxial layer 3.

[0027] like Figure 2 As shown, one side of the trench gate is in direct interface contact with one side of the third body region 5, that is, one side of the gate oxide layer 7 of the trench gate is in direct interface contact with one side of the third body region 5; a corresponding heavily doped region 9 is formed in each third body region 5, one side of the heavily doped region 9 is in direct interface contact with the gate oxide layer 7 of the trench gate, and the other side of the heavily doped region 9 is in direct contact with a conductive via, which penetrates the insulating dielectric layer and extends into the third body region. The heavily doped region 9 has a first conductivity type, and the first conductivity type is, for example, N-type. The heavily doped region 9 is heavily doped, and the doping concentration is much higher than the doping concentration of the epitaxial layer 3 and the third body region 5. As a result, the heavily doped region 9 forms an electrical contact with the conductive via, forming a conductive path. The conductive via 9 penetrates the insulating dielectric layer 10 and is in electrical contact with the metal electrode layer 12.

[0028] Easy to understand, though Figure 2 Only two first body regions 4a and one second body region 4b therebetween are shown, but those skilled in the art should be able to understand that Figure 2It is only a schematic diagram of the structure of a part of the cell area. In the entire cell area, multiple first body regions 4a and multiple second body regions 4b are alternately arranged. Correspondingly, multiple third body regions 5 are respectively located above the corresponding multiple first body regions 4a, multiple trench gates are located between the corresponding multiple first body regions 4a and multiple second body regions 4b, multiple heavily doped regions 9 are located in the corresponding third body regions 5, and multiple conductive vias extend upward from the multiple corresponding third body regions, penetrate the insulating dielectric layer, and reach the metal electrode layer. And according to Figure 2 It can be seen from the two first body regions 4 a shown on the left and right and the third body region 5 located thereon that a trench gate and a corresponding heavily doped region 9 and a conductive through hole 11 are provided on each of the two sides of each third body region 5 .

[0029] According to an embodiment of the utility model, a corresponding third body region 5, a heavily doped region 9, and a conductive via 11 are formed above the first body region 4a in the cell region, thereby electrically connecting to the top metal electrode layer 12. When the power transistor is applied, that is, when the power transistor is powered on, a potential is applied to the first body region 4a, and thus it is not in a potential floating state. In contrast, when the power transistor is applied, that is, when the power transistor is powered on, the second body region 4b in the cell region is in a potential floating state because the electrical connection with the conductive via and the metal electrode layer is removed above, thereby increasing the capacitance between the gate and drain of the device and reducing the noise and EMI problems generated by the device during switching operation.

[0030] Figure 3 FIG. 1 is a schematic diagram showing a device structure of a partial cell region of a power transistor according to another embodiment of the present utility model. A person skilled in the art should be able to understand that Figure 3 Another embodiment shown is Figure 2 The embodiments shown are identical except that Figure 3 In another embodiment shown, the injection window of the second body region 4b is different from the injection window of the first body region 4a. That is, the width of the second body region 4b can be changed. By adjusting the width of the second body region 4b, the parasitic gate-drain capacitance can be effectively adjusted.

[0031] It should be understood that although Figure 3 It is shown that the injection width of the second body region 4b is smaller than the injection width of the first body region 4a, but the technical solution of the present application can also achieve that the injection width of the second body region 4b is larger than the injection width of the first body region 4a.

[0032] It should also be understood that when the power transistor is applied, that is, when the power transistor is powered on, Figure 3 The second body region 4b in the cell region shown is also in a potential floating state, and Figure 3 The first body region 4a in the cell region shown is also not in a potential floating state.

[0033] Figure 4 FIG. 1 is a schematic diagram showing a device structure of a partial cell region of a power transistor according to another embodiment of the present utility model. A person skilled in the art should be able to understand that Figure 4 Another embodiment shown is Figure 2 The embodiments shown are identical except that Figure 3 In another embodiment shown, the implantation depth of the second body region 4b is different from the implantation depth of the first body region 4a. That is, the depth of the second body region 4b can be changed. By adjusting the depth of the second body region 4b, the parasitic gate-drain capacitance can be effectively adjusted.

[0034] It should be understood that although Figure 4 It is shown that the injection depth of the second body region 4b is smaller than the injection depth of the first body region 4a, but the technical solution of the present application can also achieve that the injection depth of the second body region 4b is greater than the injection depth of the first body region 4a.

[0035] It should also be understood that when the power transistor is applied, that is, when the power transistor is powered on, Figure 4 The second body region 4b in the cell region shown is also in a potential floating state, and Figure 4 The first body region 4a in the cell region shown is also not in a potential floating state.

[0036] It can be seen that the power transistor of the utility model is a super junction transistor structure realized by a deep trench filling process, characterized in that the connection between the through hole and the metal is removed from part of the second body region 4b of the cell region, so that the second body region 4b is in a floating state, the capacitance between the gate and the drain of the device is increased, and the noise and EMI problems generated by the device during switching are reduced. The second body region 4b involved in the utility model can have multiple implementation schemes in specific implementation, and the parasitic gate-drain capacitance can be effectively adjusted by adjusting the width and depth of the second body region 4b. The method for preparing the structure of the utility model does not require additional production costs and is easy to implement.

[0037] The power transistor with a super junction structure according to the embodiment of the utility model can be applied to various electronic devices. For example, by integrating a plurality of such power transistors and other devices (for example, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and an electronic device can be constructed thereby. Therefore, the utility model also provides an electronic device including the above-mentioned power transistor. The electronic device may also include a display screen that cooperates with the integrated circuit and components such as a wireless transceiver that cooperates with the integrated circuit. Such electronic devices include smart phones, computers, tablet computers (PCs), artificial intelligence, wearable devices, mobile power supplies, etc.

[0038] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0039] The embodiments of the present invention are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A power transistor, characterized in that: include substrate; an epitaxial layer, disposed on the substrate; An insulating dielectric layer, disposed above the epitaxial layer; A metal electrode layer, disposed above the insulating dielectric layer; a plurality of first body regions and a plurality of second body regions, disposed in the epitaxial layer, wherein upper surfaces of the plurality of second body regions are flush with an upper surface of the epitaxial layer; a plurality of third body regions, disposed above the plurality of first body regions, wherein upper surfaces of the plurality of third body regions are flush with an upper surface of the epitaxial layer; a plurality of trench gates disposed between the third body region and the second body region, wherein the trench gates extend downward from the upper surface of the epitaxial layer; wherein one side of the trench gate is in direct interface contact with one side of the third body region; A plurality of heavily doped regions are disposed in the plurality of third body regions; one side of the heavily doped region is in direct interface contact with the trench gate, and the other side of the heavily doped region is in direct contact with a conductive through hole, and the conductive through hole penetrates the insulating dielectric layer and extends into the third body region, The two sides of the second body region are respectively separated from the trench gate by the epitaxial layer, and the upper surface of the second body region is in interface contact with the lower surface of the insulating dielectric layer.

2. The power transistor according to claim 1, characterized in that The plurality of first body regions are in a non-floating state, and the plurality of second body regions are in a floating state.

3. The power transistor according to claim 1, characterized in that The plurality of first body regions and the plurality of second body regions are arranged alternately.

4. The power transistor according to claim 1, characterized in that An injection window of the first body region and an injection window of the second body region are the same.

5. The power transistor according to claim 1, characterized in that An implant window of the first body region and an implant window of the second body region are different.

6. The power transistor according to claim 1, characterized in that The substrate, the epitaxial layer and the heavily doped region all have a first conductivity type.

7. The power transistor according to claim 6, characterized in that The doping concentration of the heavily doped region is greater than the doping concentration of the substrate and the epitaxial layer.

8. The power transistor according to claim 1, wherein: The first body region, the second body region, and the third body region all have a second conductivity type.

9. The power transistor according to claim 8, characterized in that The doping concentration of the third body region is greater than the doping concentration of the first body region and the second body region.

10. An electronic device comprising an integrated circuit formed at least in part from a power transistor as claimed in any one of claims 1 to 9.

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