Noise suppression circuit of audio DAC and electronic device

Abstract

The embodiment of the utility model discloses a noise suppression circuit of an audio DAC (Digital-to-Analog Converter) applied to a chip, the chip and electronic equipment, and relates to the field of circuits. A negative feedback channel with a prime number is arranged in each error feedback modulator, the occurrence period of idle sound generated by a direct current signal can be greatly increased when the DAC works, the idle sound output by the audio DAC is effectively restrained, in addition, for chip implementation, the increased area can be almost ignored, and the hardware structure is simple in structure and easy to implement. Therefore, the hardware cost is not too high.

Description

Technical Field

[0001] The utility model relates to the field of circuits, in particular to a noise suppression circuit for an audio DAC and electronic equipment. Background Art

[0002] A DAC (Digital to Analog Converter) is provided in the audio processing circuit. After the DAC converts the audio digital signal into an analog signal, it drives the generating unit to make a sound. The current DAC generally adopts a sigma-delta structure. When the DAC receives a continuous DC signal, it will generate an idle sound, which interferes with the normal use of the user. Utility Model Content

[0003] The embodiments of the present application provide a noise suppression circuit and electronic device for an audio DAC, which can effectively suppress the idle tone generated by a digital-to-analog converter. The technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a noise suppression circuit for an audio DAC, comprising:

[0005] l-1 delayers, l-1 adders and l error feedback modulators, each error feedback modulator has the same hardware structure;

[0006] The input end of the error feedback modulator (C1) is used to input an audio digital signal, the error output end of the first error feedback modulator (C1) is connected to the input end of the second error feedback modulator (C2), the error output end of the second error feedback modulator (C2) is connected to the input end of the third error feedback modulator (C3), ..., the l-1st error feedback modulator (C l-1 ) and the input end of the l-2 error feedback modulator (C l-2 ) is connected to the error output terminal of the l-1 error feedback modulator (C l-1 ) and the error output terminal of the first error feedback modulator (C l ) is connected to the input terminal;

[0007] The output end of the first adder (B1) is used to output the digital signal after the idle tone suppression processing, the first input end of the first adder (B1) is connected to the result output end of the first error feedback modulator (C1), the first input end of the second adder (B2) is connected to the result output end of the second error feedback modulator (C2), ..., the l-1 adder (B l-1 ) and the first input terminal of the l-1 error feedback modulator (C l-1 )’s result output terminal is connected;

[0008] The second input end of the first adder (B1) is connected to the output end of the second adder (B2) and the input end of the first delay device (A1), respectively; the second input end of the second adder (B2) is connected to the output end of the third adder (B3) and the input end of the second delay device (A2), respectively, ..., the l-1 adder (B l-1 ) are connected to the first error feedback modulator (C l ) and the result output of the l-1 delay (A l-1 ) is connected to the input terminal;

[0009] The third input terminal of the first adder B1 is connected to the output terminal of the first delay device (A1), the third input terminal of the second adder (B2) is connected to the output terminal of the second delay device (A2), ..., the third input terminal of the l-1 adder (B l-1 ) and the third input terminal of the l-1th delay device (A l-1 ) is connected to the output terminal;

[0010] The first error feedback modulator (C1) comprises: a prime number generating unit, a first delay register, a second delay register, a first adder, a second adder and a quantizer;

[0011] The first input end of the first adder is the input end of the error feedback modulator 1, the first input end of the first adder is connected to the output end of the first delay register, the third input end of the first adder is connected to the output end of the second delay register, and the output end of the first adder is respectively connected to the input end of the quantizer and the first input end of the second adder;

[0012] The output end of the prime number generating unit is connected to the first input end of the first delay register, the second input end of the first delay register is connected to the output end of the quantizer, the output end of the quantizer is connected to the second input end of the second adder, and the output end of the second adder is respectively connected to the input end of the second delay register and the input end of the second error feedback modulator (C2);

[0013] The output terminal of the quantizer is connected to the first input terminal of the second adder.

[0014] In a second aspect, the present application provides an electronic device, comprising the above-mentioned noise suppression circuit of the audio DAC.

[0015] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0016] By setting a negative feedback channel with a prime number in each error feedback modulator, the relationship between the length of the idle tone generated and the order of the EFM used is: the length of the idle tone = (2n0 -a) l , n0 is the bit width of the adder, l is the order of the cascaded EF, so the occurrence period of the idle tone generated by the DC signal can be greatly increased when the DAC is working, and the idle tone output by the audio DAC can be effectively suppressed. In addition, the increased area of ​​the above hardware structure for chip implementation is almost negligible, so the hardware cost will not be too high. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a structural diagram of a noise suppression circuit of an audio DAC provided in an embodiment of the present application;

[0019] Figure 2 yes Figure 1 Schematic diagram of the structure of the error feedback modulator. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0021] See also Figure 1 and Figure 2 , the utility model provides a structural schematic diagram of a noise suppression circuit of an audio DAC according to an embodiment.

[0022] exist Figure 1 In the embodiment, the noise suppression circuit includes: l-1 delayers, l-1 adders and l error feedback modulators, and each error feedback modulator has the same hardware structure. The l-1 delayers are respectively the first delayer A1, the second delayer A2, ..., the l-1th delayer A l-1 , the l-1 adders are the first adder B1, the second adder B2, ..., the l-1 adder B l-1 , l error feedback modulators (Error Feedback Modulation, EFM) are respectively the first error feedback modulator C1, the second error feedback modulator C2, ..., the lth error feedback modulator Cl The adder is used to perform addition operations, and the delayer is used to delay the input digital, for example: outputting the digital signal stored in the n-1th clock cycle in the nth clock cycle. The error feedback modulator is mainly used to reduce the word length of the digital control signal to the DAC and to perform spectrum shaping on the resulting quantization noise.

[0023] The input end of the first error feedback modulator C1 is used to input the audio digital signal, the error output end of the first error feedback modulator C1 is connected to the input end of the second error feedback modulator C2, the error output end of the second error feedback modulator C2 is connected to the input end of the third error feedback modulator C3, ..., the l-1st error feedback modulator C l-1 The input terminal is connected to the l-2 error feedback modulator C l-2 The error output terminal of the l-1 error feedback modulator C l-1 The error output terminal is connected to the first error feedback modulator C l The input terminal is connected.

[0024] The output end of the first adder B1 is used to output the digital signal after the idle tone suppression processing, the first input end of the first adder B1 is connected to the result output end of the first error feedback modulator C1, the first input end of the second adder B2 is connected to the result output end of the second error feedback modulator C2, ..., the l-1 adder B l-1 The first input terminal is connected to the l-1th error feedback modulator C l-1 The result output terminal is connected to .

[0025] The second input end of the first adder B1 is connected to the output end of the second adder B2 and the input end of the first delay device A1 respectively, the second input end of the second adder B2 is connected to the output end of the third adder B3 and the input end of the second delay device A2 respectively, ..., the l-1 adder B l-1 The second input terminal is respectively connected to the first error feedback modulator B l The result output and the l-1th delay A l-1 The input terminal is connected to

[0026] The third input terminal of the first adder B1 is connected to the output terminal of the first delay device A1, the third input terminal of the second adder B2 is connected to the output terminal of the second delay device A2, ..., the third input terminal of the l-1 adder B l-1 The third input terminal of the first delay A l-1 Each adder performs addition operation on the digital signal inputted from the first input terminal and the digital signal inputted from the second input terminal after taking the negative value of the digital signal inputted from the third input terminal.

[0027] Since the hardware results of each error feedback modulator are the same, see Figure 2 As shown, the first error feedback modulator C1 includes: a prime number generation unit, a first delay register 11, a second delay register 12, a first adder 13, an adder 14, and a quantizer; the quantizer is used to approximate the continuous value (or a large number of possible discrete values) of the signal to a finite number (or fewer) of discrete values. The prime number generation unit is used to output a prime number a, which is multiplied by the output signal of the first delay register 11 and then output to the first adder. The prime number a is the difference between the maximum prime number that does not exceed the current quantization bit number and the maximum prime number that is less than the current prime number quantization bit number. For example: if the quantization bit number is 13, then 2^13-a is the maximum prime number less than 2^13, and this maximum prime number is 8191, so a is 1 at this time.

[0028] The first input end of the first adder 13 is the input end of the first error feedback modulator C1, the first input end of the first adder 13 is connected to the output end of the first delay register 11, the third input end of the first adder 13 is connected to the output end of the second delay register 12, and the output end of the first adder 13 is connected to the input end of the quantizer and the first input end of the adder 14 respectively;

[0029] The output end of the prime number generating unit is connected to the first input end of the first delay register 11, the second input end of the first delay register 11 is connected to the output end of the quantizer, the output end of the quantizer is connected to the second input end of the adder 14, and the output end of the adder 14 is respectively connected to the input end of the second delay register 12 and the input end of the error feedback modulator 2; the adder 14 takes a negative value of the signal output by the quantizer and performs an addition operation with the signal output by the first adder 13. The output end of the quantizer is connected to the first input end of the adder 14.

[0030] Among them, the present application eliminates idle tones by modifying the sigma-delta structure in the DAC structure of the sigma-delta modulator, and uses the mash sigma-delta structure to achieve the same noise shaping result as CIFF / CIFB, that is, the same performance. The performance here mainly values ​​the effective number of quantization bits. At the same time, a mash prime number feedback path is added to the mash structure. Using this structure can effectively eliminate idle tones.

[0031] In the embodiments of the present application, by setting a negative feedback channel with a prime number in each error feedback modulator, the occurrence period of the idle tone generated by the DC signal can be greatly increased when the DAC is working, and the idle tone output by the audio DAC can be effectively suppressed. In addition, the increased area of ​​the above-mentioned hardware structure for chip implementation is almost negligible, so the hardware cost will not be too high.

[0032] The electronic device provided with the above-mentioned noise suppression circuit provided in the embodiment of the present application includes but is not limited to communication equipment, terminal equipment, computer equipment, etc. In addition to the above-mentioned audio DAC noise suppression circuit, the electronic device may also include: a housing for accommodating various components, a display screen and an input device (for example: a keyboard, a mouse or a touch screen), etc.

[0033] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A noise suppression circuit for an audio DAC, characterized in that: include: l-1 delayers, l-1 adders and l error feedback modulators, each error feedback modulator has the same hardware structure; The input end of the error feedback modulator (C1) is used to input an audio digital signal, the error output end of the first error feedback modulator (C1) is connected to the input end of the second error feedback modulator (C2), the error output end of the second error feedback modulator (C2) is connected to the input end of the third error feedback modulator (C3), ..., the l-1st error feedback modulator (C l-1 ) and the input end of the l-2 error feedback modulator (C l-2 ) is connected to the error output terminal of the l-1 error feedback modulator (C l-1 ) and the error output terminal of the first error feedback modulator (C l ) is connected to the input terminal; The output end of the first adder (B1) is used to output the digital signal after the idle tone suppression processing, the first input end of the first adder (B1) is connected to the result output end of the first error feedback modulator (C1), the first input end of the second adder (B2) is connected to the result output end of the second error feedback modulator (C2), ..., the l-1 adder (B l-1 ) and the first input terminal of the l-1 error feedback modulator (C l-1 )’s result output terminal is connected; The second input end of the first adder (B1) is respectively connected to the output end of the second adder (B2) and the input end of the first delay device (A1), the second input end of the second adder (B2) is respectively connected to the output end of the third adder (B3) and the input end of the second delay device (A2), ..., the l-1 adder (B l-1 ) are connected to the first error feedback modulator (C l ) and the result output of the l-1 delay (A l-1 ) is connected to the input terminal; The third input terminal of the first adder (B1) is connected to the output terminal of the first delay device (A1), the third input terminal of the second adder (B2) is connected to the output terminal of the second delay device (A2), ..., the third input terminal of the l-1 adder (B l-1 ) and the third input terminal of the l-1th delay device (A l-1 ) is connected to the output terminal; The first error feedback modulator (C1) comprises: a prime number generating unit, a first delay register, a second delay register, a first adder, a second adder and a quantizer; The first input end of the first adder is the input end of the error feedback modulator (1), the first input end of the first adder is connected to the output end of the first delay register, the third input end of the first adder is connected to the output end of the second delay register, and the output end of the first adder is respectively connected to the input end of the quantizer and the first input end of the second adder; The output end of the prime number generating unit is connected to the first input end of the first delay register, the second input end of the first delay register is connected to the output end of the quantizer, the output end of the quantizer is connected to the second input end of the second adder, and the output end of the second adder is respectively connected to the input end of the second delay register and the input end of the second error feedback modulator (C2); The output terminal of the quantizer is connected to the first input terminal of the second adder.

2. An electronic device, characterized in that: A noise suppression circuit comprising the audio DAC as claimed in claim 1.

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