Memory data delay protection circuit

Abstract

The utility model discloses a memory data delay protection circuit in the field of data protection. The memory data delay protection circuit comprises a memory U1, a VCC end of the memory U1 is connected with a comparison circuit, a CE end of the memory U1 is connected with a reverse latch circuit, the comparison circuit is connected with the reverse latch circuit, and the reverse latch circuit is connected with an integral delay circuit. If power is recovered, the comparison circuit outputs a high level, and the integral delay circuit firstly outputs a low level, so that the reverse latch circuit outputs the high level, the memory U1 is continuously prevented from performing read-write operation, the power supply voltage is stabilized after a period of time is delayed, and the integral delay circuit outputs the high level; the reverse latch circuit outputs a low level to the CE end of the memory U1, and the memory U1 normally performs read-write operation; and the read-write operation of the memory is stopped before the power failure starts and the power supply voltage is stabilized again, so that the SRAM port is in a high-resistance state, and the purpose of data protection is achieved.

Description

Technical Field

[0001] The utility model relates to a memory data delay protection circuit in the technical field of data protection. Background Art

[0002] The big data center provides powerful data support capabilities for the grassroots units of the public security system, which improves work efficiency. In the control system of the big data center, due to the very limited chip memory capacity, the data storage and program storage are often expanded. Whether it is volatile memory or non-volatile memory, the data of the computer application system needs to be protected when the power is off, and the correct operation of the system needs to be ensured after the power is restored. However, in the prior art, when the power is restored, due to the sudden change of the power supply at the moment of step change, the WeChat computer may put the SRAM in a read-write state at this time, and read some random data on the data bus into the SRAM, affecting the accuracy of the data. Utility Model Content

[0003] The utility model aims to provide a memory data delay protection circuit, which prevents the memory from reading and writing operations before power failure and re-powering until the power supply voltage stabilizes, making the SRAM port in a high impedance state to achieve the purpose of data protection.

[0004] To achieve the above-mentioned purpose, the utility model provides a memory data delay protection circuit, including a memory U1, wherein the VCC terminal of the memory U1 is connected to a comparison circuit, the CE terminal of the memory U1 is connected to a reverse latch circuit, the comparison circuit is connected to the reverse latch circuit, and the reverse latch circuit is connected to an integral delay circuit.

[0005] Compared with the prior art, the utility model has the beneficial effect that when the memory is normally powered on, the comparison circuit outputs a high level, the integration delay circuit outputs a high level, and finally outputs a low level to the CE end of the memory U1 through the reverse latch circuit, and the memory U1 performs read and write operations normally; after the memory is powered off, the comparison circuit outputs a low level, no matter whether the integration delay circuit outputs a high level or a low level, the reverse latch circuit outputs a high level, and the CE end of the memory U1 is loaded with a high level, thereby preventing the memory U1 from performing read and write operations; if the power is restored, the comparison circuit outputs a high level, and the integration delay circuit outputs a low level first, so that the reverse latch circuit outputs a high level, and thus the memory U1 continues to be prevented from performing read and write operations. After a delay period, the power supply voltage is stable, then the integration delay circuit outputs a high level, and the reverse latch circuit outputs a low level to the CE end of the memory U1, and the memory U1 performs read and write operations normally; the memory is prevented from performing read and write operations at the beginning of power failure and before the power supply voltage is stabilized after power is re-applied, so that the SRAM port is in a high impedance state, thereby achieving the purpose of data protection.

[0006] As a further improvement of the utility model, the comparison circuit includes a comparator A1, wherein the 2nd pin of the comparator A1 is respectively connected to the positive electrode of the diode D2 and the positive electrode of the backup power supply, the negative electrode of the diode D2 is respectively connected to the negative electrode of the diode D1 and the CE end of the memory U1, the positive electrode of the diode D1 is respectively connected to one end of the resistor R1 and the positive electrode of the 5V power supply, the other end of the resistor R1 is connected to the 3rd pin of the comparator A1, the 3rd pin of the comparator A1 is respectively connected to the negative electrode of the voltage-stabilizing diode D3 and the 3rd pin of the comparator A2, and the positive electrode of the voltage-stabilizing diode D3 is respectively connected to the positive electrode of the voltage-stabilizing diode D3. Grounded, pin 1 of comparator A1 is connected to the cathode of light emitting diode D4, the anode of light emitting diode D4 is connected to the anode of 5V power supply via resistor R2, pin 2 of comparator A2 is connected to one end of resistor R4 and one end of resistor R3 respectively, the other end of resistor R4 is grounded, the other end of resistor R3 is connected to one end of resistor R6 and connected to the anode of 5V power supply, one end of resistor R3 is connected to the other end of resistor R6 via resistor R5, the other end of resistor R6 is connected to pin 1 of comparator A2, and pin 1 of comparator A2 is connected to the reverse latch circuit.

[0007] In this way, when the 5V power supply is normally supplied, the voltage regulator diode D3 provides a reference voltage, and the voltage at the non-inverting input terminal of the comparator A2 is higher than that at the reverse input terminal, so that its output terminal outputs a high level; when the 5V power supply is cut off, the voltage at the non-inverting input terminal of the comparator A2 is lower than that at the reverse input terminal, so that its output terminal outputs a low level; and when the diode D4 lights up, it indicates that the backup power supply voltage is too low and needs to be replaced.

[0008] As a further improvement of the utility model, the integral delay circuit includes an inverter B1, pin 1 of the inverter B1 is connected to the positive electrode of the diode D5, the negative electrode of the diode D5 is respectively connected to the positive electrode of the capacitor C1 and the pin 1 of the inverter B3, the negative electrode of the capacitor C1 is grounded, the diode D5 is connected in parallel with the resistor R7, and the pin 2 of the inverter B3 is connected to the reverse latch circuit.

[0009] In this way, when the 5V power supply is restored after being cut off, inverter B1 outputs a low level, thereby discharging the capacitor. During the discharging process, inverter B3 outputs a low level until the capacitor is discharged, and then inverter B3 outputs a high level, thereby realizing a delayed operation.

[0010] As a further improvement of the utility model, the reverse latch circuit includes an AND gate B2, pin 2 of the AND gate B2 is connected to pin 1 of the comparator A2, pin 3 of the AND gate B2 is connected to pin 2 of the inverter B3, pin 1 of the AND gate B2 is connected to pin 1 of the inverter B4, and pin 2 of the inverter B4 is connected to the CE terminal of the memory U1.

[0011] In this way, when the 5V power supply is normally supplied, when the input end of B2 is at a high level, it outputs a high level, and outputs a low level through the inverter B4, which is loaded to the CE end of the memory U1, so that the memory U1 can read and write data normally; and when the 5V power supply is restored after being cut off, A2 outputs a high level, and the capacitor C1 discharges, so that B3 outputs a low level, so that the input end of B2 is loaded with a low level and a high level, and it outputs a low level, so that B4 outputs a high level, so that the CE end of the memory U1 is loaded with a high level, and the data of the memory U1 is maintained and cannot be read or written. It is not possible to read and write normally until the capacitor circuit is discharged, ensuring that the memory will not read some random data on the data bus into the SRAM before the power supply is restored to a stable state. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is the circuit diagram of the utility model. DETAILED DESCRIPTION

[0013] The utility model is further described below in conjunction with the accompanying drawings:

[0014] like Figure 1 A memory data delay protection circuit shown includes a memory U1, wherein the VCC terminal of the memory U1 is connected to a comparison circuit, the CE terminal of the memory U1 is connected to a reverse latch circuit, the comparison circuit is connected to the reverse latch circuit, and the reverse latch circuit is connected to an integral delay circuit.

[0015] The comparison circuit includes a comparator A1, wherein the 2nd pin of the comparator A1 is respectively connected to the positive electrode of the diode D2 and the positive electrode of the backup power supply, the negative electrode of the diode D2 is respectively connected to the negative electrode of the diode D1 and the CE terminal of the memory U1, the positive electrode of the diode D1 is respectively connected to one end of the resistor R1 and the positive electrode of the 5V power supply, the other end of the resistor R1 is connected to the 3rd pin of the comparator A1, the 3rd pin of the comparator A1 is respectively connected to the negative electrode of the voltage-stabilizing diode D3 and the 3rd pin of the comparator A2, the positive electrode of the voltage-stabilizing diode D3 is grounded, and the comparator A Pin 1 of comparator A1 is connected to the cathode of light emitting diode D4, the anode of light emitting diode D4 is connected to the anode of 5V power supply via resistor R2, pin 2 of comparator A2 is connected to one end of resistor R4 and one end of resistor R3 respectively, the other end of resistor R4 is grounded, the other end of resistor R3 is connected to one end of resistor R6 and connected to the anode of 5V power supply, one end of resistor R3 is connected to the other end of resistor R6 via resistor R5, the other end of resistor R6 is connected to pin 1 of comparator A2, and pin 1 of comparator A2 is connected to the reverse latch circuit.

[0016] The integration delay circuit includes an inverter B1, wherein pin 1 of the inverter B1 is connected to the positive electrode of the diode D5, the negative electrode of the diode D5 is respectively connected to the positive electrode of the capacitor C1 and pin 1 of the inverter B3, the negative electrode of the capacitor C1 is grounded, the diode D5 is connected in parallel with the resistor R7, and pin 2 of the inverter B3 is connected to the reverse latch circuit.

[0017] The reverse latch circuit includes an AND gate B2, wherein pin 2 of the AND gate B2 is connected to pin 1 of the comparator A2, pin 3 of the AND gate B2 is connected to pin 2 of the inverter B3, pin 1 of the AND gate B2 is connected to pin 1 of the inverter B4, and pin 2 of the inverter B4 is connected to the CE terminal of the memory U1.

[0018] In the utility model, the memory U1 is SRAM, the voltage regulator diode D3 provides a reference voltage, and the backup power supply supplies power to the memory U1 when the 5V power supply is cut off to ensure that data will not be lost. Resistors R1, R2, comparator A1 and light-emitting diode D4 constitute a monitoring circuit for the backup power supply. Once the backup power supply voltage is insufficient, the light-emitting diode D4 will light up to remind you to replace the battery.

[0019] When the 5V power supply is normally supplied, the voltage at the non-inverting input of comparator A2 is greater than the voltage at the inverting input, so comparator A2 outputs a high level to the input of AND gate B2, while the input of inverter B1 is high and its output is low, so inverter B3 outputs a high level. In this way, both inputs of AND gate B2 are high, and it outputs a high level to inverter B4, so inverter B4 outputs a low level which is loaded on the CE end of memory U1, so that memory U1 can read and write data normally.

[0020] When the 5V power supply is cut off, the backup power supply supplies power to the memory U1, and the voltage at the non-inverting input of the comparator A2 is less than the voltage at the inverting input. Therefore, the output of the comparator A2 is low level to the input of the AND gate B2. At this time, the input of the inverter B1 is low level, and its output is high level. Since the capacitor C1 needs to be charged, the inverter B3 outputs a high level first and then a low level. However, since the output of the comparator A2 is low level, the output of the AND gate B2 is always low level, so the inverter B4 outputs a high level to the CE end of the memory U1, so that the memory U1 is in a data retention state and cannot read or write data.

[0021] When the 5V power supply is cut off and then restored, the voltage at the non-inverting input of comparator A2 is greater than the voltage at the inverting input, so comparator A2 outputs a high level to the input of AND gate B2, while the input of inverter B1 is high and its output is low, so capacitor C1 will discharge, so that the input of inverter B3 is still high, so during the discharge process, inverter B3 outputs a low level, so AND gate B2 outputs a low level, so inverter B4 outputs a high level to the CE end of memory U1, so that memory U1 is in a data retention state and cannot read or write data. At the moment when the power supply suddenly changes, the computer will not read some random data on the data bus into memory U1, ensuring the accuracy of its data; when the capacitor is discharged, inverter B3 outputs a high level, so that the input of AND gate B2 is all high, and its output is high, so that inverter B4 outputs a low level loaded on the CE end of memory U1, so that memory U1 can read and write data normally.

[0022] The utility model prevents the memory from performing read and write operations at the beginning of power failure and before power is re-applied until the power supply voltage becomes stable, so that the SRAM port is in a high impedance state, thereby achieving the purpose of data protection.

[0023] The present utility model is not limited to the above-mentioned embodiments. On the basis of the technical solution disclosed herein, technicians in this field can make some substitutions and deformations to some technical features therein according to the disclosed technical content without creative labor, and these substitutions and deformations are all within the protection scope of the present utility model.

Claims

1. A memory data delay protection circuit, comprising a memory U1, characterized in that: The VCC terminal of the memory U1 is connected to the comparison circuit, the CE terminal of the memory U1 is connected to the reverse latch circuit, the comparison circuit is connected to the reverse latch circuit, and the reverse latch circuit is connected to the integration delay circuit.

2. The memory data delay protection circuit according to claim 1, characterized in that: The comparison circuit includes a comparator A1, wherein the 2nd pin of the comparator A1 is respectively connected to the positive electrode of the diode D2 and the positive electrode of the backup power supply, the negative electrode of the diode D2 is respectively connected to the negative electrode of the diode D1 and the CE terminal of the memory U1, the positive electrode of the diode D1 is respectively connected to one end of the resistor R1 and the positive electrode of the 5V power supply, the other end of the resistor R1 is connected to the 3rd pin of the comparator A1, the 3rd pin of the comparator A1 is respectively connected to the negative electrode of the voltage-stabilizing diode D3 and the 3rd pin of the comparator A2, the positive electrode of the voltage-stabilizing diode D3 is grounded, and the comparator A Pin 1 of comparator A1 is connected to the cathode of light emitting diode D4, the anode of light emitting diode D4 is connected to the anode of 5V power supply via resistor R2, pin 2 of comparator A2 is connected to one end of resistor R4 and one end of resistor R3 respectively, the other end of resistor R4 is grounded, the other end of resistor R3 is connected to one end of resistor R6 and connected to the anode of 5V power supply, one end of resistor R3 is connected to the other end of resistor R6 via resistor R5, the other end of resistor R6 is connected to pin 1 of comparator A2, and pin 1 of comparator A2 is connected to the reverse latch circuit.

3. The memory data delay protection circuit according to claim 2, characterized in that: The integration delay circuit includes an inverter B1, wherein pin 1 of the inverter B1 is connected to the positive electrode of the diode D5, the negative electrode of the diode D5 is respectively connected to the positive electrode of the capacitor C1 and pin 1 of the inverter B3, the negative electrode of the capacitor C1 is grounded, the diode D5 is connected in parallel with the resistor R7, and pin 2 of the inverter B3 is connected to the reverse latch circuit.

4. The memory data delay protection circuit according to claim 3, characterized in that: The reverse latch circuit includes an AND gate B2, wherein pin 2 of the AND gate B2 is connected to pin 1 of the comparator A2, pin 3 of the AND gate B2 is connected to pin 2 of the inverter B3, pin 1 of the AND gate B2 is connected to pin 1 of the inverter B4, and pin 2 of the inverter B4 is connected to the CE terminal of the memory U1.

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