DDR particle cross stacking layout structure
Through the DDR particle cross-stack layout structure, the problem of laying out more DDR memory particles in a compact PCB space is solved, achieving higher space utilization and simpler signal interconnection.
Patent Information
- Application Number
- CN202421406692.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-19
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2034-06-19
AI Technical Summary
Arrange more DDR memory particles in compact printed circuit board (PCB) space to improve space utilization, especially when the number of devices increases in system design.
Using a DDR particle cross-stack layout structure, by soldering the first DDR memory chip and the second DDR memory chip to one side and the other side of the PCB board respectively, and then flip up and down, cross-coupling and welding, the distribution of the pin area is optimized to reduce the address interconnection length.
The address interconnect length of DDR particles is effectively reduced, the space utilization of printed boards is improved, so that more devices can be arranged in a compact space, and the fan-out and signal interconnection of devices are simplified.
Smart Images
Figure CN222786239U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, and in particular to a DDR particle cross-stacked layout structure. Background Art
[0002] DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is a synchronous dynamic random access memory with a double data transfer rate. Its characteristic is that it can transmit data twice in each system clock cycle, that is, once on the rising edge and once on the falling edge of the clock, thereby achieving a higher data transmission speed than traditional SDRAM.
[0003] With the development of technology, the packaging technology and manufacturing process of DDR memory are also constantly improving. For example, DDR uses TSSOP packaging technology, while DDR2 and DDR3 use FBGA packaging technology, which makes the memory particles perform better in terms of anti-interference and heat dissipation. In DDR4, 3DS (3-Dimensional Stack) three-dimensional stacking technology is used to further increase the capacity of a single chip. In terms of manufacturing process, DDR memory particles widely use 0.13 micron manufacturing process, DDR2 uses 0.09 micron, DDR3 uses 65 nanometers, and DDR4 uses a process below 20 nanometers to manufacture, showing the performance improvement and cost reduction brought about by technological progress.
[0004] However, with the rapid development of technology and market demand, the memory required by the system has increased, and the number of DDRs that can be mounted by more powerful CPUs and FPGAs has increased. In system design, there are many functions and more devices are required, resulting in tight space in PCB (printed circuit board) design. Therefore, we hope to place more devices in a limited space and realize more functions. Utility Model Content
[0005] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a DDR particle cross-stacked layout structure to improve the space utilization of PCB layout.
[0006] The purpose of this utility model is achieved through the following technical solutions:
[0007] A DDR particle cross-stacked layout structure comprises a PCB board, a first DDR memory chip and a second DDR memory chip; the first DDR memory chip is welded on one side of the PCB board, and the second DDR memory chip is welded on the other side of the PCB board after the first DDR memory chip is turned upside down.
[0008] Furthermore, the bottom surface of the DDR memory chip is provided with a first pin area and a second pin area, and there is a spacing area between the first pin area and the second pin area; the first pin area and the second pin area of the cross-mounted first DDR memory chip and the second DDR memory chip are cross-distributed, that is, the first pin area of the second DDR memory chip overlaps with the spacing area of the first DDR memory chip, and the first pin area of the first DDR memory chip overlaps with the spacing area of the second DDR memory chip.
[0009] Furthermore, the left half area of the first pin area and the second pin area of the DDR memory chip is the address bit pin area, and the right half area is the data bit pin area. The address bit pin areas of the cross-mounted first DDR memory chip and the second DDR memory chip are located on the same side of the PCB board, and the data bit pin area is located on the other side of the PCB board.
[0010] Furthermore, the PCB board is provided with a plurality of via arrays and a plurality of pads, the pads and the vias are connected one-to-one through microstrip lines, the distance between the plurality of vias is 0.8 mm, and the pin particles of the DDR memory chip are connected to the pads to realize welding with the PCB board.
[0011] Furthermore, the distance between the most adjacent vias connecting the first DDR memory chip and the second DDR memory chip is set to 0.8 mm.
[0012] The beneficial effects of the utility model are:
[0013] The utility model provides a DDR particle cross-stacked layout structure, which can effectively reduce the length of the address interconnection of the DDR particles; effectively increase the space utilization rate of the printed circuit board, ensure that more devices can be arranged in a compact space, and facilitate the fan-out and signal interconnection of the devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 A schematic diagram of a layout scheme in which four DDR chips are stacked in pairs in a cross-stacked manner according to an embodiment;
[0015] Figure 2 A schematic diagram of two DDR particles cross-stacked according to an embodiment. DETAILED DESCRIPTION
[0016] The following will be combined with the embodiments to clearly and completely describe the technical solution of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0017] See also Figure 1-Figure 2 , the utility model provides a technical solution:
[0018] like Figure 1 As shown, this embodiment provides a DDR particle cross-stacked layout structure, including a PCB board, a first DDR memory chip and a second DDR memory chip; the first DDR memory chip is soldered on one side of the PCB board, and the second DDR memory chip is the first DDR memory chip turned upside down and cross-stitched and soldered on the other side of the PCB board. This embodiment adopts a cross-stacked method of different surfaces, stacking two DDR memory chips on different surfaces together to achieve the effect of reducing space occupation.
[0019] Specifically, the bottom surface of the DDR memory chip is provided with a first pin area and a second pin area, and there is a spacing area between the first pin area and the second pin area; the first pin area and the second pin area of the cross-mounted first DDR memory chip and the second DDR memory chip are cross-distributed, that is, the first pin area of the second DDR memory chip overlaps with the spacing area of the first DDR memory chip, and the first pin area of the first DDR memory chip overlaps with the spacing area of the second DDR memory chip.
[0020] like Figure 1 The schematic diagram shows a layout structure in which a first DDR memory chip and a second DDR memory chip are cross-mounted on a PCB board, wherein a first pin area A and a second pin area B of the first DDR memory chip are spaced apart from a first pin area C and a second pin area D of the second DDR memory chip, and their projection areas on the PCB board do not overlap with each other.
[0021] The left half of the first pin area and the second pin area of the DDR memory chip is the address pin area, and the right half is the data pin area. The address pin areas of the first DDR memory chip and the second DDR memory chip that are cross-attached are located on the same side of the PCB board, and the data pin areas are located on the other side of the PCB board. For a DDR memory chip, usually its address pins and data pins are located on both sides of the DDR pins. It can be understood that the address pin areas of the two DDR memory chips that are flipped upside down and attached are located on the same side of the PCB board, and the corresponding data pin areas are located on the other side of the PCB board. This layout method can shorten the address line interconnection length of multiple DDR memory chips.
[0022] In this embodiment, the PCB board is provided with a plurality of via arrays and a plurality of pads, the pads and the vias are connected one-to-one through microstrip lines, the distance between the plurality of vias is 0.8 mm, and the pin particles of the DDR memory chip are connected to the pads to realize welding with the PCB board.
[0023] like Figure 2 The distance between the most adjacent vias connecting the first DDR memory chip and the second DDR memory chip is set to 0.8 mm. Since the spacing between vias on the PCB board is a fixed distance, in order to ensure a more compact layout, the vias connected to the DDR particle pins on different surfaces should be adjacent but not overlapped.
[0024] In this embodiment, only the layout of two DDR chips is illustrated as an example. The layout of more DDR chips is similar, and two by two are stacked and placed crosswise to save a lot of layout space.
[0025] The embodiment of the utility model provides a DDR particle cross-stacked layout structure, which can effectively reduce the length of the address interconnection of the DDR particles; effectively increase the space utilization rate of the printed circuit board, ensure that more devices can be arranged in a compact space, and facilitate the fan-out and signal interconnection of the devices.
[0026] The above is only a preferred embodiment of the utility model. It should be understood that the utility model is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the utility model, and should be within the scope of protection of the claims attached to the utility model.
Claims
1. A DDR particle cross-stacked layout structure, characterized in that: It includes a PCB board, a first DDR memory chip and a second DDR memory chip; the first DDR memory chip is welded on one side of the PCB board, and the second DDR memory chip is welded on the other side of the PCB board after the first DDR memory chip is turned upside down.
2. The DDR chip cross-stacked layout structure according to claim 1, characterized in that: The bottom surface of the DDR memory chip is provided with a first pin area and a second pin area, and there is a spacing area between the first pin area and the second pin area; the first pin area and the second pin area of the cross-mounted first DDR memory chip and the second DDR memory chip are cross-distributed, that is, the first pin area of the second DDR memory chip overlaps with the spacing area of the first DDR memory chip, and the first pin area of the first DDR memory chip overlaps with the spacing area of the second DDR memory chip.
3. The DDR chip cross-stacked layout structure according to claim 2, characterized in that: The left half of the first pin area and the second pin area of the DDR memory chip are address pin areas, and the right half are data pin areas. The address pin areas of the cross-mounted first DDR memory chip and the second DDR memory chip are located on the same side of the PCB board, and the data pin areas are located on the other side of the PCB board.
4. The DDR chip cross-stacked layout structure according to claim 1, characterized in that: The PCB board is provided with a plurality of via arrays and a plurality of pads, the pads and the vias are connected one-to-one through microstrip lines, the distance between the plurality of vias is 0.8 mm, and the pin particles of the DDR memory chip are connected to the pads to realize welding with the PCB board.
5. The DDR chip cross stacking layout structure according to claim 4, characterized in that: The distance between the most adjacent vias connecting the first DDR memory chip and the second DDR memory chip is set to 0.8 mm.