Inverter circuit and semiconductor circuit

Abstract

An inverter circuit includes: an electrically insulating structure having a planar geometry including a first surface and a second surface, the first surface and the second surface being parallel to each other and each oriented in a respective plane perpendicular to a thickness direction; the p-type semiconductor layer is formed on the first surface; the n-type semiconductor layer is formed on the second surface; a gate dielectric layer formed in contact with the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed in contact with the gate dielectric layer; a first source electrode and a first drain electrode formed so as to be in contact with the p-type semiconductor layer; and a second source electrode and a second drain electrode formed so as to be in contact with the n-type semiconductor layer. The inverter circuit is connectable to a voltage source, a ground voltage terminal, an input signal terminal, and an output signal terminal to operate as an inverter.

Description

Technical Field

[0001] The embodiments of the utility model relate to an inverter circuit and a semiconductor circuit. Background Art

[0002] The semiconductor industry has grown due to continued improvements in the integration density of various electronic components, such as transistors, diodes, resistors, inductors, capacitors, etc. In large part, these improvements in integration density have come from repeated reductions in minimum feature size, which has enabled more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become increasingly smaller, and there is a continuing need to develop new materials, processes, and designs for semiconductor devices and interconnects to enable further advancements.

[0003] Transistors made from oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because they can be processed at low temperatures and thus may not damage previously fabricated devices. For example, fabrication conditions and techniques may not damage previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. Circuits based on oxide semiconductor-based transistor devices may further include other components that may be fabricated in BEOL processes, such as capacitors, inductors, resistors, and integrated passive devices. Utility Model Content

[0004] Some embodiments of the present utility model provide an inverter circuit, characterized in that it includes: an electrically insulating structure having a flat plate geometry including a first surface and a second surface, the first surface and the second surface are parallel to each other and are respectively oriented in corresponding planes perpendicular to the thickness direction; a p-type semiconductor layer formed on the first surface; an n-type semiconductor layer formed on the second surface; a gate dielectric layer formed to contact the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed to contact the gate dielectric layer; a first source electrode and a first drain electrode formed to contact the p-type semiconductor layer; and a second source electrode and a second drain electrode formed to contact the n-type semiconductor layer, wherein the first source electrode is electrically connected to a voltage source, and the second source electrode is electrically connected to a ground voltage terminal, wherein the gate electrode is electrically connected to an input signal terminal, and wherein the first drain electrode and the second drain electrode are electrically connected to an output signal terminal.

[0005] In addition, other embodiments of the present invention provide a semiconductor circuit, characterized in that it includes: a first layer of p-type metal oxide semiconductor, which is formed in the interlayer dielectric layer along a first vertical plane relative to a horizontal interface of the interlayer dielectric layer; a second layer of n-type metal oxide semiconductor, which is formed in the interlayer dielectric layer along a second vertical plane relative to the horizontal interface of the interlayer dielectric layer, so that the first layer and the second layer are parallel to each other and separated from each other by a part of the interlayer dielectric layer; a gate electrode, which has a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; a gate dielectric layer, which separates the first vertical portion of the gate electrode from the first layer, and separates the second vertical portion of the gate electrode from the second layer; a first source electrode and a first drain electrode, which are formed to contact the p-type metal oxide semiconductor; and a second source electrode and a second drain electrode, which are formed to contact the n-type metal oxide semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of a first exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower level dielectric material layer, and an isolation dielectric layer according to various embodiments.

[0008] Figure 2A is a three-dimensional perspective view of a semiconductor circuit that can be formed in a BEOL process according to various embodiments.

[0009] Figure 2B According to various embodiments Figure 2A Another three-dimensional perspective view of the semiconductor circuit shown.

[0010] Figure 2C According to various embodiments Figure 2A and Figure 2B Schematic equivalent circuit of the semiconductor circuit shown.

[0011] Figure 2D According to various embodiments Figure 2A Another three-dimensional perspective view of a semiconductor circuit is shown, and various sizes of components of the semiconductor circuit are shown.

[0012] Figure 3Ais a vertical cross-sectional view of an intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0013] Figure 3B According to various embodiments Figure 3A A top view of the intermediate structure shown.

[0014] Figure 4A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0015] Figure 4B According to various embodiments Figure 4A A top view of the intermediate structure shown.

[0016] Figure 5A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0017] Figure 5B According to various embodiments Figure 5A A top view of the intermediate structure shown.

[0018] Fig. 6A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0019] Figure 6B According to various embodiments Fig. 6A A top view of the intermediate structure shown.

[0020] Fig. 7A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0021] Figure 7B According to various embodiments Fig. 7A A top view of the intermediate structure shown.

[0022] Fig. 8A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0023] Figure 8B According to various embodiments Fig. 8A A top view of the intermediate structure shown.

[0024] Fig.9A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0025] Fig. 9B According to various embodiments Fig.9A A top view of the intermediate structure shown.

[0026] Fig. 10A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0027] Fig. 10B According to various embodiments Fig. 10A A top view of the intermediate structure shown.

[0028] Fig.11A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0029] Fig. 11B According to various embodiments Fig.11A A top view of the intermediate structure shown.

[0030] Fig. 12A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0031] Fig. 12B According to various embodiments Fig. 12A A top view of the intermediate structure shown.

[0032] Fig.13A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0033] Fig. 13B According to various embodiments Fig.13A A top view of the intermediate structure shown.

[0034] Fig.14A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0035] Fig. 14B According to various embodiments Fig.14A A top view of the intermediate structure shown.

[0036] Fig. 14C According to various embodiments Fig.14A and Fig. 14B Another vertical cross-sectional view of the intermediate structure shown.

[0037] Fig.15A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0038] Fig. 15B According to various embodiments Fig.15A A top view of the intermediate structure shown.

[0039] Fig. 15C According to various embodiments Fig.15A and Fig. 15BAnother vertical cross-sectional view of the intermediate structure shown.

[0040] Fig.16A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0041] Fig. 16B According to various embodiments Fig.16A A top view of the intermediate structure shown.

[0042] Fig. 16C According to various embodiments Fig.16A and Fig. 16B Another vertical cross-sectional view of the intermediate structure shown.

[0043] Fig.17A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0044] Fig. 17B According to various embodiments Fig.17A A top view of the intermediate structure shown.

[0045] Fig. 17C According to various embodiments Fig.17A and Fig. 17B Another vertical cross-sectional view of the intermediate structure shown.

[0046] Fig.18A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0047] Fig.18B According to various embodiments Fig.18A A top view of the intermediate structure shown.

[0048] Fig.18C According to various embodiments Fig.18A and Fig.18B Another vertical cross-sectional view of the intermediate structure shown.

[0049] Fig.19A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0050] Fig.19B According to various embodiments Fig.19A A top view of the intermediate structure shown.

[0051] Fig.19C According to various embodiments Fig.19A and Fig.19B Another vertical cross-sectional view of the intermediate structure shown.

[0052] Fig. 20Ais a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0053] Fig. 20B According to various embodiments Fig. 20A A top view of the intermediate structure shown.

[0054] Fig. 20C According to various embodiments Fig. 20A and Fig. 20B Another vertical cross-sectional view of the intermediate structure shown.

[0055] Fig.21A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0056] Fig.21B According to various embodiments Fig.21A A top view of the intermediate structure shown.

[0057] Fig. 21C According to various embodiments Fig.21A and Fig.21B Another vertical cross-sectional view of the intermediate structure shown.

[0058] Fig.22A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0059] Fig. 22B According to various embodiments Fig.22A A top view of the intermediate structure shown.

[0060] Fig. 22C According to various embodiments Fig.22A and Fig. 22B Another vertical cross-sectional view of the intermediate structure shown.

[0061] Fig.23A is a vertical cross-sectional view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0062] Fig. 23B According to various embodiments Fig.23A A top view of the intermediate structure shown.

[0063] Fig.23C According to various embodiments Fig.23A and Fig. 23B Another vertical cross-sectional view of the intermediate structure shown.

[0064] Fig.24A According to various embodiments, by referring to FIG. 3A to FIG. 23C A vertical cross-sectional view of a semiconductor circuit formed by the illustrated process.

[0065] Fig. 24B According to various embodiments Fig.24A A top view of the semiconductor circuit shown.

[0066] Fig.24C According to various embodiments Fig.24A and Fig. 24B Still another vertical cross-sectional view of the semiconductor circuit shown.

[0067] Fig.24D According to various embodiments FIG. 24A to FIG. 24C A three-dimensional perspective view of the semiconductor circuit shown.

[0068] Fig.25 is a flowchart illustrating the operations of a method of forming a semiconductor circuit according to various embodiments. DETAILED DESCRIPTION

[0069] The following disclosure provides many different embodiments or examples to implement different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0070] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to have the same material composition and have a thickness within the same thickness range.

[0071] Various embodiments of the present disclosure provide semiconductor circuits and methods that may have advantages in terms of manufacturing flexibility, size reduction, and short channel effect reduction. In this regard, an embodiment semiconductor circuit (e.g., complementary metal-oxide-semiconductor (CMOS) inverter) is provided that can be formed in a BEOL process and can be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed semiconductor circuits may include materials that can be processed at low temperatures, thereby not damaging previously fabricated devices (e.g., FEOL devices and MEOL devices). In addition, various embodiment semiconductor circuits may include p-channel metal oxide semiconductor field effect transistors (pFETs) having vertical channel layers and n-channel metal oxide semiconductor field effect transistors (nFETs) also having vertical channel layers. Each of the vertical p-channel and the vertical n-channel may be formed on opposite sides of a vertically oriented electrically insulating structure such that the vertical p-channel and the vertical n-channel are closely spaced relative to each other. Use of such a vertical channel may provide semiconductor circuits having reduced dimensions relative to alternative structures that do not include a vertical channel, and may allow for longer channel lengths without increasing device size, which may mitigate short channel effects.

[0072] An embodiment inverter circuit includes an electrically insulating structure having a slab geometry including a first surface and a second surface parallel to each other. The first surface and the second surface may each be oriented in a respective plane perpendicular to a thickness direction. The embodiment inverter circuit may include: a p-type semiconductor layer formed on the first surface; an n-type semiconductor layer formed on the second surface; a gate dielectric layer formed to contact the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed to contact the gate dielectric layer; a first source electrode and a first drain electrode formed to contact the p-type semiconductor layer; and a second source electrode and a second drain electrode formed to contact the n-type semiconductor layer. The inverter circuit may be connected to a voltage supply, a ground voltage terminal, an input signal terminal, and an output signal terminal to operate as an inverter.

[0073] In another embodiment, a semiconductor circuit may include: a first layer formed of a p-type metal oxide semiconductor, formed in the interlayer dielectric layer along a first vertical plane relative to a horizontal interface of the interlayer dielectric layer; a second layer formed of an n-type metal oxide semiconductor, formed in the interlayer dielectric layer along a second vertical plane relative to the horizontal interface of the interlayer dielectric layer, such that the first layer and the second layer are parallel to each other and separated from each other by a portion of the interlayer dielectric layer. The semiconductor circuit may further include: a gate electrode having a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; a gate dielectric layer separating the first vertical portion of the gate electrode from the first layer and also separating the second vertical portion of the gate electrode from the second layer; a first source electrode and a first drain electrode formed to contact the p-type metal oxide semiconductor; and a second source electrode and a second drain electrode formed to contact the n-type metal oxide semiconductor.

[0074] An embodiment method of forming a semiconductor circuit may include: forming an electrically insulating structure, the electrically insulating structure having a planar geometry including a first surface and a second surface, the first surface and the second surface being parallel to each other and each oriented in a corresponding plane perpendicular to a thickness direction; forming a p-type semiconductor layer on the first surface; forming an n-type semiconductor layer on the second surface; forming a gate dielectric layer in contact with the p-type semiconductor layer and the n-type semiconductor layer; forming a gate electrode in contact with the gate dielectric layer; forming a first source electrode and a first drain electrode in contact with the p-type semiconductor layer; and forming a second source electrode and a second drain electrode in contact with the n-type semiconductor layer.

[0075] Figure 1 A semiconductor structure 100 according to various embodiments is shown. The semiconductor structure 100 includes a substrate 102, which may be a semiconductor substrate (e.g., a commercially available silicon substrate). The substrate 102 may include a semiconductor material layer 104 at least at an upper portion thereof. The semiconductor material layer 104 may be a surface portion of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 104 includes a single crystalline semiconductor material (e.g., single crystalline silicon). In one embodiment, the substrate 102 may include a single crystalline silicon substrate including a single crystalline silicon material.

[0076] A shallow trench isolation structure 106 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 104. A suitable doped semiconductor well such as a p-type well and an n-type well may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 106. Field effect transistors 108 may be formed over the top surface of the semiconductor material layer 104. For example, each of the field effect transistors 108 may include a source electrode 110, a drain electrode 112, a semiconductor channel 114 including a surface portion of the substrate 102 extending between the source electrode 110 and the drain electrode 112, and a gate structure 116. The semiconductor channel 114 may include a single crystalline semiconductor material.

[0077] Each gate structure 116 may include a gate dielectric layer 118, a gate electrode 120, a gate cap dielectric 122, and a dielectric gate spacer 124. A source-side metal semiconductor alloy region 126 may be formed on each source electrode 110, and a drain-side metal semiconductor alloy region 128 may be formed on each drain electrode 112. Devices formed on the top surface of the semiconductor material layer 104 may include complementary metal oxide semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuits 134.

[0078] Figure 1 The semiconductor structure 100 may include a memory array region 130 in which an array of memory cells may be subsequently formed. The first exemplary structure may further include a peripheral region 132 in which metal wiring for the array of memory devices is provided. Generally speaking, the field effect transistors 108 in the CMOS circuit 134 may be electrically connected to electrodes of corresponding memory cells via a collection of corresponding metal interconnect structures.

[0079] The devices in the peripheral region 132 (e.g., field effect transistors 108) may provide functions for operating an array of memory cells to be subsequently formed. Specifically, the devices in the peripheral region may be configured to control programming operations, erasing operations, and sensing (reading) operations of the array of memory cells. For example, the devices in the peripheral region 132 may include sensing circuitry and / or programming circuitry.

[0080] One or more of the field effect transistors 108 in the CMOS circuit 134 may include a semiconductor channel 114 that includes a portion of a semiconductor material layer 104 in the substrate 102. In an embodiment in which the semiconductor material layer 104 includes a single crystalline semiconductor material (e.g., single crystalline silicon), the semiconductor channel 114 of each of the field effect transistors 108 in the CMOS circuit 134 may include a single crystalline semiconductor channel (e.g., a single crystalline silicon channel). In one embodiment, a plurality of field effect transistors 108 in the CMOS circuit 134 may include a corresponding node that is subsequently electrically connected to a node of a corresponding memory cell to be subsequently formed. For example, a plurality of field effect transistors 108 in the CMOS circuit 134 may include a corresponding source electrode 110 or a corresponding drain electrode 112 that is subsequently electrically connected to a node of a corresponding memory cell to be subsequently formed.

[0081] In one embodiment, the CMOS circuit 134 may include a programming control circuit configured to control the gate voltage of the set of field effect transistors 108 (the gate voltage may be used to program the corresponding memory cell (e.g., ferroelectric memory cell)) and control the gate voltage of a transistor (e.g., a thin film transistor) to be formed subsequently. In this embodiment, the programming control circuit may be configured to provide a first programming pulse, the first programming pulse programs the corresponding ferroelectric dielectric material layer in the selected ferroelectric memory cell into a first polarization state, in which the electrical polarization in the ferroelectric dielectric material layer is directed toward the first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse, the second programming pulse programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state, in which the electrical polarization in the ferroelectric dielectric material layer is directed toward the second electrode of the selected ferroelectric memory cell.

[0082] In one embodiment, the substrate 102 may include a single crystal silicon substrate, and the field effect transistor 108 may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. As used herein, a "semiconducting" device refers to a device with a conductivity of 1.0×10 -6 Siemens / cm (S / cm) to 1.0×10 5 Siemens / cm range. As used herein, "semiconductor material" refers to a semiconductor material having an electrical conductivity in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm range and can produce conductivity in the range of 1.0 Siemens / cm to 1.0×10 5Doped materials in the Siemens / cm range.

[0083] According to an embodiment, the field effect transistor 108 may then be electrically connected to a drain electrode and a gate electrode of an access transistor including a semiconductive metal oxide plate to be formed above the field effect transistor 108. In one embodiment, a subset of the field effect transistors 108 may then be electrically connected to at least one of the drain electrode and the gate electrode. For example, the field effect transistor 108 may include a first word line driver configured to apply a first gate voltage to a first word line through a first subset of a lower level metal interconnect structure to be formed later, and a second word line driver configured to apply a second gate voltage to a second word line through a second subset of a lower level metal interconnect structure to be formed later. In addition, the field effect transistor 108 may include a bit line driver and a sense amplifier, the bit line driver being configured to apply a bit line bias voltage to a bit line to be formed later, and the sense amplifier being configured to detect a current flowing through the bit line during a read operation.

[0084] Various metal interconnect structures formed within the dielectric material layer may subsequently be formed over the substrate 102 and the semiconductor devices thereon, such as the field effect transistor 108. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 136 (sometimes referred to as a contact level dielectric material layer), which may be a layer surrounding contact structures connected to the source and drain, a first inline level dielectric material layer 138, and a second inline level dielectric material layer 140. The metal interconnect structures may include a device contact via structure 142 formed in the first dielectric material layer 136 and contacting respective components of the CMOS circuit 134, a first metal line structure 144 formed in the first inline level dielectric material layer 138, a first metal via structure 146 formed in a lower portion of the second inline level dielectric material layer 140, and a second metal line structure 148 formed in an upper portion of the second inline level dielectric material layer 140.

[0085] Each of the dielectric material layers (136, 138, 140) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (142, 144, 146, 148) may include at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof.

[0086] Other suitable metal liners and metal fill materials may also be used within the scope of the present disclosure. In one embodiment, the first metal via structure 146 and the second metal line structure 148 may be formed as an integrated line and via structure by a dual damascene process. The dielectric material layers (136, 138, 140) are referred to herein as lower level dielectric material layers. The metal interconnect structures (142, 144, 146, 148) formed in the lower level dielectric material layers are referred to herein as lower level metal interconnect structures.

[0087] Although the present disclosure is described using embodiments in which an array of memory cells may be formed above the second line and via level dielectric material layer 140, embodiments in which an array of memory cells may be formed at a different metal interconnect level are expressly contemplated herein.

[0088] An array of thin film transistors and an array of ferroelectric memory cells (or other types of memory cells) may then be deposited on the dielectric material layer (136, 138, 140) in which the metal interlink structures (142, 144, 146, 148) are formed. The collection of all dielectric material layers formed before forming the array of thin film transistors or the array of ferroelectric memory cells is collectively referred to as lower-level dielectric material layers (136, 138, 140). The collection of all metal interlink structures formed within the lower-level dielectric material layers (136, 138, 140) is referred to herein as first metal interlink structures (142, 144, 146, 148). In general, the first metal interlink structures (142, 144, 146, 148) formed within at least one lower-level dielectric material layer (136, 138, 140) may be formed on the semiconductor material layer 104 located in the substrate 102.

[0089] According to an embodiment, a thin film transistor may then be formed in the metal interconnect level, the thin film transistor being overlying the metal interconnect level including the lower level dielectric material layer (136, 138, 140) and the first metal interconnect structure (142, 144, 146, 148). In one embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower level dielectric material layer (136, 138, 140). The planar dielectric material layer is referred to herein as an insulating matrix layer 150. The insulating matrix layer 150 may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 may range from 20 nanometers (i.e., 200 angstroms) to 300 nanometers (i.e., 3000 angstroms), although lesser and greater thicknesses may also be used.

[0090] Generally, an inline-level dielectric layer (e.g., lower-level dielectric material layer (136, 138, 140)) containing a metal inline structure (e.g., first metal inline structure (142, 144, 146, 148)) may be formed over the semiconductor device. An insulating matrix layer 150 may be formed over the inline-level dielectric layer. Other passive devices may be formed in the BEOL process. For example, various capacitors, inductors, resistors, and integrated passive devices may be used with other BEOL devices.

[0091] Figure 2A is a three-dimensional perspective view of a semiconductor circuit 200 that can be formed in a BEOL process according to various embodiments, and Figure 2B yes Figure 2A Another three-dimensional perspective view of the semiconductor circuit 200 is shown. Figure 2C According to various embodiments Figure 2A and Figure 2B Schematic equivalent circuit 200c of semiconductor circuit 200 is shown. Figure 2A and Figure 2B As shown, the semiconductor circuit 200 may include an electrically insulating structure 202 having a planar geometry including a first surface 204a and a second surface 204b, wherein the first surface 204a and the second surface 204b are parallel to each other and are each oriented perpendicular to a thickness direction (e.g., the thickness direction is along Figure 2A and Figure 2BThe semiconductor circuit 200 may further include: a p-type semiconductor layer 206a formed on the first surface 204a; an n-type semiconductor layer 206b formed on the second surface 204b; a gate dielectric layer 118 formed to contact the p-type semiconductor layer 206a and the n-type semiconductor layer 206b; and a gate electrode 116 formed to contact the gate dielectric layer 118.

[0092] The semiconductor circuit 200 may further include a first source electrode 110a and a first drain electrode 112a (see, for example, Figure 2B ), formed to contact the p-type semiconductor layer 206a; and a second source electrode 110b and a second drain electrode 112b, formed to contact the n-type semiconductor layer 206b. Figure 2B As shown, the first source electrode 110a can be electrically connected to a voltage source 208 (e.g., can be maintained at a source voltage VDD), and the second source electrode 110b can be connected to a ground voltage terminal 210 (e.g., can be maintained at a ground (GND) voltage). The gate electrode 116 can be connected to an input signal terminal 212, and the first drain electrode 112a and the second drain electrode 112b can be electrically connected to an output signal terminal 214. In this way, the semiconductor circuit 200 can be configured as an inverter circuit, such as Figure 2C shown.

[0093] Figure 2C According to various embodiments Figure 2A and Figure 2B Schematic equivalent circuit 200c of semiconductor circuit 200 is shown. In this aspect, p-type semiconductor layer 206a can be configured as a vertical channel layer of a p-channel metal oxide semiconductor field effect transistor (MOSFET) (i.e., pFET 216), and n-type semiconductor layer 206b can be configured as a vertical channel layer of an n-channel MOSFET transistor (i.e., nFET 218). Therefore, pFET 216 includes p-type semiconductor layer 206a, a first source electrode 110a, a first drain electrode 112a, a gate dielectric layer 118, and a gate electrode 116. Similarly, nFET 218 includes n-type semiconductor layer 206b, a second source electrode 110b, a second drain electrode 112b, and a gate electrode 116.

[0094] The low voltage placed on the input signal terminal 212 turns on the pFET 216 and turns off the nFET 218. Since the source of the pFET 216 (ie, the first source electrode 110a) is connected to the voltage source 208 having a high voltage, the output voltage V out(i.e., the voltage at the first drain electrode 112a) will have a high voltage. Similarly, the high voltage placed on the input signal terminal 212 turns on the nFET 218 and turns off the pFET 216. Since the source of the nFET 218 (i.e., the second source electrode 110b) is connected to the ground voltage terminal, the output voltage V out (ie, the voltage at the second drain electrode 112 b ) will have a low voltage. In this way, a high output signal is converted into a low output signal, and a low input signal is converted into a high input signal. In this way, the semiconductor circuit 200 is configured as an inverter circuit.

[0095] Figure 2A and Figure 2B The semiconductor circuit 200 shown may be formed on an interlayer dielectric layer having a horizontal interface. For example, the semiconductor circuit 200 may be formed on an insulating matrix layer 150 (see, for example, Figure 1 ) or formed on one or more additional interconnect layers on the insulating matrix layer 150. Figure 2A and Figure 2B As shown, the electrically insulating structure 202 may have a vertical orientation such that each of the first surface 204a and the second surface 204b is perpendicular to a horizontal interface of the interlayer dielectric layer (see, for example, Figure 1 , wherein the insulating matrix layer 150 has a horizontal surface).

[0096] An interlayer dielectric layer (see, for example, Figure 1 The lower level dielectric material layer (136, 138, 140) in the embodiment may include one or more electrical interconnect structures (see, for example, Figure 1 The first metal interconnect structure (142, 144, 146, 148) in the embodiment of the present invention is electrically connected to the first metal interconnect structure (142, 144, 146, 148), wherein the one or more electrical interconnect structures can be electrically connected to the first metal interconnect structure (142, 144, 146, 148) in the embodiment of the present invention. Figure 2A and Figure 2B The semiconductor circuit 200 is shown. In this aspect, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to the one or more electrical interconnect structures (142, 144, 146, 148) formed in the one or more dielectric material layers (136, 138, 140) below the semiconductor circuit 200. In other embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to one or more electrical interconnect structures that will be subsequently formed above the semiconductor circuit 200.

[0097] In one or more embodiments, one or both of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may include a metal oxide semiconductor. For example, the p-type semiconductor layer 206a may include one or more of NiO, SnO, and Cu2O, and the n-type semiconductor layer 206b may include amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x In some embodiments, the n-type semiconductor layer 206b may have a x Ga y Zn z MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. In other embodiments, the n-type semiconductor layer 206b may include an alloy of oxygen, a group III element and a group V element. In other embodiments, one or more of the n-type semiconductor layer and the p-type semiconductor layer may be formed of a metal oxide semiconductor having a multilayer structure.

[0098] In some embodiments, as described above, the electrically insulating structure 202 may include AlO x 、SiO2、SiN x Or one or more of other interlayer dielectric materials. The gate dielectric layer 118 may be a high-k dielectric material and may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, hafnium dioxide-alumina, etc. As described in more detail below, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b may include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al, etc. Other suitable conductor materials may be within the scope of the present disclosure.

[0099] Figure 2D According to various embodiments, Figure 2A Another three-dimensional perspective view of various sizes of components of the semiconductor circuit 200 is shown. As described above, the p-type semiconductor layer 206a can be configured as a p-channel layer of a pFET 216 device, and the n-type semiconductor layer 206b can be configured as an nFET 218 device (see, for example, Figure 2C ) of the n-channel layer. Thus, when the corresponding device (216, 218) is enabled, the current can be as follows Figure 2DIn this regard, when the pFET 216 is enabled (e.g., by applying a low or zero bias to the gate electrode 116), positive charge carriers (i.e., "holes") may flow from the first source electrode 110a to the first drain electrode 112a (e.g., see Figure 2B ), thereby generating a first current 220a. Similarly, when the nFET 218 is enabled (e.g., by applying a high bias to the gate electrode 116), negative charge carriers (i.e., electrons) may flow from the second drain electrode 112b to the second source electrode 110b, but since the current carried by the negative charges is opposite to their movement, the movement of charges in the nFET 218 generates a second current 220b in the same direction as the first current 220a flowing in the pFET 216.

[0100] Each of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may have a corresponding channel length 222 and a corresponding channel width 224. In various embodiments, the channel length 222 may have a value greater than 15 nanometers. An increased value of the channel length 222 may mitigate the short channel effect. However, increasing the channel length 222 may reduce the drive current and make the size of the semiconductor circuit 200 larger. Therefore, the channel length 222 may be optimized to determine a sufficiently large value to avoid the short channel effect while also keeping the size of the semiconductor circuit 200 as small as possible. According to various embodiments, the channel width 224 may have a value greater than 5 nanometers and less than 500 nanometers.

[0101] The first source electrode 110a and the first drain electrode 112a (see, for example, Figure 2B), each of the second source electrode 110b and the second drain electrode 112b may have a source / drain width approximately equal to the channel width 224. Each of the source / drain electrodes (110a, 110b, 112a, 112b) may also have a source / drain length 226 and a source / drain thickness 228, each of which may have a value greater than 5 nanometers. The electrically insulating structure 202 may have a thickness 230 greater than 5 nanometers and less than 500 nanometers. The gate electrode 116 may have a gate length 232 and a gate width 234 that may be comparable to the channel length 222 and the channel width 224, respectively. In this regard, the gate length 232 may be greater than 10 nanometers, and the gate width 234 may be greater than 5 nanometers and less than 500 nanometers. The top portion of the gate electrode 116 may have a gate thickness 236 that may have a value greater than 10 nanometers and less than 150 nanometers. The gate dielectric layer 118 may have a gate dielectric thickness 238 greater than 2 nanometers and less than 20 nanometers. The p-type semiconductor layer 206a may have a p-type thickness 240a, and the n-type semiconductor layer 206b may have an n-type thickness 240b, each of which may be greater than 2 nanometers and less than 50 nanometers.

[0102] Figure 3A is a vertical cross-sectional view of an intermediate structure 300 that may be used to form the semiconductor circuit 200 according to various embodiments, and Figure 3B yes Figure 3A A top view of the intermediate structure 300 is shown. Definition Figure 3A The vertical plane of view in is given by Figure 3B The cross section A-A' is represented by Figure 3A As shown, the intermediate structure 300 may include a substrate 302 , an interlayer dielectric layer 202L, an etch stop layer 306L, and a photoresist 308L.

[0103] The substrate 302 may be formed in a BEOL process and thus may be a dielectric layer (eg Figure 1The substrate 302 may be an interlayer dielectric layer or insulating matrix layer 150. For example, the substrate 302 may include undoped silicate glass, doped silicate glass (e.g., deposited by decomposing tetraethylorthosilicate (TEOS)), organosilicate glass, silicon oxynitride, or silicon carbide nitride. Other suitable dielectric materials are also within the scope of the present disclosure. The dielectric material of the substrate 302 may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin coating). The thickness of the substrate 302 may each be in the range of approximately 15 nanometers to approximately 60 nanometers (e.g., approximately 20 nanometers to approximately 40 nanometers), but lesser and greater thicknesses may also be used.

[0104] The interlayer dielectric layer 202L may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina, or various other insulating structures (e.g., a multi-layer stack structure including alternating insulating layers). The interlayer dielectric layer 202L may be deposited by a conformal deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc.) or by a self-planarization deposition process (e.g., spin coating). In this example, the interlayer dielectric layer 202L may be formed as a flat blanket (i.e., unpatterned) layer having a flat top surface and a flat bottom surface. Excess portions of the interlayer dielectric layer 202L may be removed from above the top surface of the intermediate structure 300 by a planarization process, such as by chemical mechanical planarization (CMP). The thickness of the interlayer dielectric layer 202L may be in a range of approximately 5 nanometers to approximately 50 nanometers, such as approximately 20 nanometers to approximately 40 nanometers, although other embodiments may include lesser and greater thicknesses.

[0105] The etch stop layer 306L may include an etch stop material such as silicon nitride, silicon carbide, silicon nitride carbide, or a dielectric metal oxide such as aluminum oxide, titanium oxide, tantalum oxide, etc. The etch stop layer 306L may be deposited by a conformal deposition process or a non-conformal deposition process. In one embodiment, the etch stop layer 306L may be deposited by CVD, ALD, or PVD. The thickness of the etch stop layer 306L may range from approximately 2 nanometers to approximately 20 nanometers (e.g., approximately 3 nanometers to approximately 12 nanometers), although lesser and greater thicknesses may also be used.

[0106] Figure 4A is a vertical cross-sectional view of yet another intermediate structure 400 that may be used to form the semiconductor circuit 200 according to various embodiments, and Figure 4B yes Figure 4A A top view of the intermediate structure 400 is shown. Definition Figure 4A The vertical plane of view in is given by Figure 4B The cross section AA' is represented. Figure 3A and Figure 3B The photoresist 308L may be formed as a uniform layer on the etch stop layer 306L, and then the photoresist 308L may be patterned using photolithography techniques to form a Figure 4A and Figure 4B The patterned photoresist 308 is shown. According to some embodiments, the patterned photoresist 308 may be formed into a periodic array of rectangular shapes on the etch stop layer 306L. For example, Figure 4A and Figure 4B The view of may correspond to a repeating unit of the array of periodic rectangular shapes. Each portion of the patterned photoresist 308 may have a first horizontal direction (ie, Figure 4B The width of the x-direction in the second horizontal direction (i.e. Figure 4B The patterned photoresist 308 may then be used as a mask to pattern the etch stop layer 306L and the interlayer dielectric layer 202L, as described below with reference to Figure 5A and Figure 5B A more detailed description is shown below.

[0107] Figure 5A is a vertical cross-sectional view of yet another intermediate structure 500 that may be used to form the semiconductor circuit 200 according to various embodiments, and Figure 5B yes Figure 5A A top view of the intermediate structure 500 is shown. Definition Figure 5A The vertical plane of view in is given by Figure 5B The cross section AA' is represented. Figure 5A and Figure 5B The intermediate structure 500 can be self-assembled in the following manner: Figure 4A and Figure 4B The intermediate structure 400 is formed by performing an anisotropic etching process to remove portions of the interlayer dielectric layer 202L and the etch stop layer 306L that are not masked by the patterned photoresist 308. The patterned photoresist 308 can then be removed by ashing or by dissolving with a solvent. FIG. 2A to FIG. 2D The illustrated electrically insulating structure 202 may include the remaining portion of the interlayer dielectric layer 202L after the anisotropic etching process. As shown, each electrically insulating structure 202 formed in this manner may have a plate geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b being parallel to each other and each oriented perpendicular to the thickness direction (e.g., Figure 5A The intermediate structure 500 also includes a remaining portion of the etch stop layer 306L formed on the top portion of the electrically insulating structure 202.

[0108] Fig. 6A is a vertical cross-sectional view of yet another intermediate structure 600 that may be used to form the semiconductor circuit 200 according to various embodiments, and Figure 6B yes Fig. 6A A top view of the intermediate structure 600 is shown. Definition Fig. 6A The vertical plane of view in is given by Figure 6B The intermediate structure 600 can be formed by Figure 5A and Figure 5B The intermediate structure 500 is formed by depositing a first oxide semiconductor layer 206La on the intermediate structure 500. The first oxide semiconductor layer 206La may be a p-type semiconducting material, including but not limited to NiO, SnO, and Cu2O, which may be formed by any suitable method (e.g., ALD, CVD, PECVD, PVD, etc.). The thickness of the first oxide semiconductor layer 206La may be in a range of approximately 2 nanometers to approximately 50 nanometers (e.g., approximately 5 nanometers to approximately 15 nanometers), but other embodiments may include smaller and larger thicknesses. After depositing the first oxide semiconductor layer 206La, the intermediate structure 600 may be selectively annealed. The selective annealing process may be performed using a rapid thermal annealing or a furnace annealing process at a temperature in a range of 200 degrees Celsius to 400 degrees Celsius. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0109] Fig. 7A is a vertical cross-sectional view of yet another intermediate structure 700 that may be used to form the semiconductor circuit 200 according to various embodiments, and Figure 7B yes Fig. 7AA top view of the intermediate structure 700 is shown. Definition Fig. 7A The vertical plane of view in is given by Figure 7B The intermediate structure 700 can be self-assembled by the following method: Fig. 6A and Figure 6B The intermediate structure 600 is formed by depositing an additional interlayer dielectric layer 202L over the intermediate structure 600, followed by forming an additional patterned photoresist 308. In this regard, the additional interlayer dielectric layer 202L may be deposited by a conformal deposition process (e.g., CVD, ALD, PVD, PECVD, etc.) or by a self-planarization deposition process (e.g., spin coating). Excess portions of the interlayer dielectric layer 202L may be removed from above the top surface of the first oxide semiconductor layer 206La by a planarization process (e.g., by CMP).

[0110] A photoresist layer (not shown) may then be formed over the top surface of the interlayer dielectric layer 202L and the top surface of the first oxide semiconductor layer 206La. The photoresist layer may then be patterned using a photolithography technique to produce a patterned photoresist 308, which may then be used as a mask to further etch the intermediate structure 700. Fig. 7A As shown, the patterned photoresist 308 can be configured to mask the top portion 702 and the side portion 704 of the first oxide semiconductor layer 206La, while leaving the remaining portions of the first oxide semiconductor layer 206La and the interlayer dielectric layer 202L unmasked. The unmasked portions can then be removed in a subsequent anisotropic etching process, as described below with reference to Fig. 8A and Figure 8B A more detailed description is shown below.

[0111] Fig. 8A is a vertical cross-sectional view of yet another intermediate structure 800 that may be used to form the semiconductor circuit 200 according to various embodiments, Figure 8B yes Fig. 8A A top view of the intermediate structure 800 is shown. Definitions Fig. 8A The vertical plane of view in is given by Figure 8B 7 . As shown, the intermediate structure 800 can be formed from the intermediate structure 700 shown in FIG. 7 by performing an anisotropic etching process to remove the unshielded portions of the first oxide semiconductor layer 206La and the interlayer dielectric layer 202L. The patterned photoresist 308 can then be removed by ashing or by dissolving with a solvent. The resulting intermediate structure 800 includes the electrically insulating structure 202, the patterned etch stop layer 306, and the remaining top portion 702 and side portion 704 of the first oxide semiconductor layer 206La.

[0112] Fig.9Ais a vertical cross-sectional view of yet another intermediate structure 900 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 9B yes Fig.9A A top view of the intermediate structure 900 is shown. Definitions Fig.9A The vertical plane of view in is given by Fig. 9B The cross section AA' is represented. Fig.9A and Fig. 9B The intermediate structure 900 may be formed by further depositing an additional interlayer dielectric layer 202L over the intermediate structure 800 and forming a patterned photoresist 308 over the resulting structure.

[0113] In this regard, the additional interlayer dielectric layer 202L may be deposited by a conformal deposition process (e.g., CVD, ALD, PVD, PECVD, etc.) or by a self-planarization deposition process (e.g., spin coating). Excess portions of the interlayer dielectric layer 202L may be removed from above the top surface of the first oxide semiconductor layer 206La by a planarization process (e.g., by CMP). The planarization process may also remove a top portion 702 of the first oxide semiconductor layer 206La (e.g., see Fig. 8A ). Then, the remaining piece of the side portion 704 forms the p-type semiconductor layer 206a of the semiconductor circuit 200 to be formed later. Then, a uniform photoresist layer (not shown) can be deposited on the planarized surface of the interlayer dielectric layer 202L and the patterned etch stop layer 306. Then, the uniform photoresist layer can be patterned using photolithography technology to form a patterned photoresist 308. Fig. 9B As shown, the patterned photoresist 308 may include exposed areas 902 that may be etched in subsequent processing operations, as shown in FIG. Fig. 10A and Fig. 10B A more detailed description is shown below.

[0114] Fig. 10A is a vertical cross-sectional view of yet another intermediate structure 1000 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 10B yes Fig. 10A A top view of the intermediate structure 1000 is shown. Definition Fig. 10A The vertical plane of view in is given by Fig. 10B The intermediate structure 1000 can be formed from the intermediate structure 900 by performing an anisotropic etching process to remove the portion of the interlayer dielectric layer 202L that is not masked by the patterned photoresist 308. In this way, the anisotropic etching process can produce trenches 1002. The presence of trenches 1002 can allow the n-type semiconductor layer 206b to be subsequently formed on the second surface 204b of the electrically insulating structure 202, as described below with reference to FIG. 11A to FIG. 13BAfter the anisotropic etching process is performed, the patterned photoresist 308 may be removed by ashing or by dissolving with a solvent.

[0115] Fig.11A is a vertical cross-sectional view of yet another intermediate structure 1100 that may be used to form the semiconductor circuit 200 according to various embodiments, Fig. 11B yes Fig.11A A top view of the intermediate structure 1100 is shown. Definition Fig.11A The vertical plane of view in is given by Fig. 11B The intermediate structure 1100 can be formed by Fig. 10A and Fig. 10B The second oxide semiconductor layer 206Lb is formed by depositing a second oxide semiconductor layer 206Lb on the intermediate structure 1000. The second oxide semiconductor layer 206Lb can be an n-type semiconductive material, including but not limited to amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and alloys thereof. Other suitable semiconductive materials are also within the contemplated scope of the present disclosure. For example, in various embodiments, the second oxide semiconductor layer 206Lb may include In x Ga y Zn z The composition given by MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. The second oxide semiconductor layer 206Lb can be formed by any suitable method (such as ALD, CVD, PECVD, PVD, etc.).

[0116] In an embodiment, the second oxide semiconductor layer 206Lb may be formed on Fig. 10A and Fig. 10B The intermediate structure 1000 is shown. The thickness of the second oxide semiconductor layer 206Lb can be in a range of approximately 2 nanometers to approximately 50 nanometers (e.g., approximately 5 nanometers to approximately 15 nanometers), but other embodiments may include smaller and larger thicknesses. After depositing the second oxide semiconductor layer 206Lb, the intermediate structure 1100 can be selectively annealed. The selective annealing process can be performed using a rapid thermal annealing or furnace annealing process at a temperature in a range of 200 degrees Celsius to 400 degrees Celsius. The annealing can be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0117] Fig. 12A is a vertical cross-sectional view of yet another intermediate structure 1200 that may be used to form the semiconductor circuit 200 according to various embodiments, Fig. 12B yes Fig. 12AA top view of the intermediate structure 1200 is shown. Definition Fig. 12A The vertical plane of view in is given by Fig. 12B The intermediate structure 1200 can be formed by Fig.11A and Fig. 11B The intermediate structure 1100 is formed by depositing an additional interlayer dielectric layer 202L on top of the intermediate structure 1100. A planarization process (e.g., using CMP) may then be performed to remove excess portions of the interlayer dielectric layer 202L and a top portion of the second oxide semiconductor layer 206Lb located above the top surface of the patterned etch stop layer 306. A patterned photoresist 308 may then be formed on the resulting structure. Fig. 12A As shown, the patterned photoresist 308 can mask the side portion 1202 of the second oxide semiconductor layer 206Lb, the patterned etch stop layer 306, and the p-type semiconductor layer 206a, while retaining other unmasked portions of the interlayer dielectric layer 202L and the second oxide semiconductor layer 206Lb. Fig. 12B As shown, the patterned photoresist 308 may include exposed areas 902 that may be etched in subsequent processing operations, as shown in FIG. Fig.13A and Fig. 13B A more detailed description is shown below.

[0118] Fig.13A is a vertical cross-sectional view of yet another intermediate structure 1300 that may be used to form the semiconductor circuit 200 according to various embodiments, Fig. 13B yes Fig.13A A top view of the intermediate structure 1300 is shown. Definition Fig.13A The vertical plane of view in is given by Fig. 13B , and the cross section A-A' in FIG. As shown, the intermediate structure 1300 can be formed by performing an anisotropic etching process to remove the unshielded portion of the second oxide semiconductor layer 206Lb and the interlayer dielectric layer 202L. The patterned photoresist 308 can then be removed by ashing or by dissolving with a solvent. The resulting intermediate structure 1300 includes the electrically insulating structure 202, the p-type semiconductor layer 206a, the patterned etching stop layer 306, and the remaining portion of the second oxide semiconductor layer 206Lb that forms the n-type semiconductor layer 206b. Fig.13A and Fig. 13B As shown, the anisotropic etching process can produce trenches 1002, which can be filled with additional interlayer dielectric layer 202L in subsequent processing operations, as described below with reference to FIG. 14A to FIG. 14C A more detailed description is shown below.

[0119] Fig.14A is a vertical cross-sectional view of yet another intermediate structure 1400 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 14B yes Fig.14A A top view of intermediate structure 1400 is shown. Fig. 14C According to various embodiments Fig.14A and Fig. 14B Another vertical cross-sectional view of the intermediate structure shown. The intermediate structure 1400 can be formed by forming an additional interlayer dielectric layer 202L on the intermediate structure 1300 to fill the trench 1002. Excess portions of the interlayer dielectric layer 202L can be removed using a planarization process (e.g., using CMP). Definition Fig.14A The vertical plane of view in is given by Fig. 14B The cross section A-A' in the figure is represented by Fig. 14C The vertical plane of view in is given by Fig. 14B The cross section C-C' is represented. Fig.14A The cross-sectional view of Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A and Fig. 17B hereinafter is used to describe a process for forming the first source electrode 110a, the second source electrode 110b, the first drain electrode 112a and the second drain electrode 112b. Fig. 14C The cross-sectional view of FIG. 18B to FIG. 24B hereinafter is used to describe a process for forming the gate electrode 116 .

[0120] Fig.15A is a vertical cross-sectional view of yet another intermediate structure 1500 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 15B yes Fig.15A A top view of intermediate structure 1500 is shown. Fig. 15C According to various embodiments Fig.15A and Fig. 15B The intermediate structure 1500 can be formed by forming a patterned photoresist 308 on the intermediate structure 1400. Fig.15A and Fig. 15B As shown, the patterned photoresist 308 may have an opening 1502, which will allow the exposed area of ​​the interlayer dielectric layer 202L to be removed in a subsequent anisotropic etching process, as shown in FIG. FIG. 16A to FIG. 16C A more detailed description is shown below.

[0121] Fig.16A is a vertical cross-sectional view of yet another intermediate structure 1600 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 16B yes Fig.16A A top view of intermediate structure 1600 is shown. Fig. 16C According to various embodiments Fig.16A and Fig. 16BAnother vertical cross-sectional view of the intermediate structure shown. The intermediate structure 1600 can be formed by performing an anisotropic etching process to remove the exposed portion of the interlayer dielectric layer 202L, thereby generating trenches 1002 in the interlayer dielectric layer 202L. As shown, each of the trenches 1002 can be formed adjacent to a corresponding p-type semiconductor layer 206a and n-type semiconductor layer 206b. The trenches 1002 can then be filled with a conductive material to form a first source electrode 110a, a second source electrode 110b, a first drain electrode 112a, and a second drain electrode 112b, as described below with reference to 17A to 17C A more detailed description is shown below.

[0122] Fig.17A is a vertical cross-sectional view of yet another intermediate structure 1700 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 17B yes Fig.17A A top view of intermediate structure 1700 is shown. Fig. 17C According to various embodiments Fig.17A and Fig. 17B 1002. The intermediate structure 1700 may be formed by depositing a conductive material 1702 into the trench 1002. The conductive material 1702 may include a metal liner material and a metal fill material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, ​​TiC, TaC, and / or WC. The thickness of the metal liner material may range from approximately 1 nanometer to approximately 10 nanometers, such as approximately 3 nanometers to approximately 8 nanometers, although lesser and greater thicknesses may also be used.

[0123] The metal fill material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal fill materials within the scope of the present disclosure may also be used. The thickness of the metal fill material may be in the range of approximately 5 nanometers to approximately 500 nanometers (e.g., approximately 20 nanometers to approximately 40 nanometers), but smaller and larger thicknesses may also be used. The metal liner material and the metal fill material may be formed by a suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the scope of the present disclosure. The patterned photoresist 308 may then be removed by ashing or by dissolving with a solvent. Then, the excess portion of the conductive material 1702 may be removed from above the horizontal plane including the top surface of the interlayer dielectric layer 202L by a planarization process such as CMP, but other suitable planarization processes may also be used. The remaining portion of the conductive material 1702 forms the first source electrode 110a, the second source electrode 110b, the first drain electrode 112a and the second drain electrode 112b (for example, at Fig.18A ). In some embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b may include one or more alloys of one or more of W, Mo, Co, Pd, Ti, and mixtures thereof with or without N and / or O, the one or more alloys being deposited by chemical vapor deposition or by atomic layer deposition.

[0124] Fig.18A is a vertical cross-sectional view of yet another intermediate structure 1800 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig.18B yes Fig.18A A top view of intermediate structure 1800 is shown. Fig.18C According to various embodiments Fig.18A and Fig.18B Another vertical cross-sectional view of the intermediate structure shown. The intermediate structure 1800 can be formed by removing the patterned photoresist 308 of the intermediate structure 1700 and planarizing the intermediate structure 1700, and then forming a new patterned photoresist 308 on the resulting structure. Fig.18B and Fig.18C As shown, the patterned photoresist 308 may have an opening 1502, which will allow the exposed area of ​​the interlayer dielectric layer 202L to be removed in a subsequent anisotropic etching process, as shown in FIG. FIG. 19A to FIG. 19C A more detailed description is shown below.

[0125] Fig.19Ais a vertical cross-sectional view of yet another intermediate structure 1900 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig.19B yes Fig.19A A top view of intermediate structure 1900 is shown. Fig.19C According to various embodiments Fig.19A and Fig.19B 19 is another vertical cross-sectional view of the intermediate structure shown. The intermediate structure 1900 can be formed by performing an anisotropic etching process to remove exposed portions of the interlayer dielectric layer 202L, thereby creating trenches 1002 in the interlayer dielectric layer 202L. As shown, each of the trenches 1002 can be formed adjacent to a corresponding p-type semiconductor layer 206a and n-type semiconductor layer 206b. The trenches 1002 can then be filled with a gate dielectric layer 118 and a conductive material to form a gate electrode 116, as described below with reference to FIG. 20A to FIG. 24C A more detailed description is shown below.

[0126] Fig. 20A is a vertical cross-sectional view of yet another intermediate structure 2000 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 20B yes Fig. 20A A top view of intermediate structure 2000 is shown. Fig. 20C According to various embodiments Fig. 20A and Fig. 20B 19. The intermediate structure 2000 may be formed by depositing a gate dielectric layer 118 on the intermediate structure 1900 shown in FIG. 19. The gate dielectric layer 118 may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, tantalum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina, or various other insulating structures (e.g., a multilayer stack structure including alternating insulating layers). Other suitable dielectric materials are also within the scope of the present disclosure. In other embodiments, the gate dielectric layer 118 may include an alternating multilayer structure including silicon oxide and silicon nitride. In other embodiments, the gate dielectric layer 118 may include a ferroelectric material.

[0127] The gate dielectric layer 118 may be formed by any suitable technique, such as ALD, CVD, PECVD, PVD, etc. The thickness of the gate dielectric layer 118 may be in a range of approximately 2 nanometers to approximately 20 nanometers, such as approximately 5 nanometers to approximately 12 nanometers, although other embodiments may include lesser and greater thicknesses. After depositing the gate dielectric layer 118, the intermediate structure 2000 may be optionally annealed. The selective annealing process may be performed using a rapid thermal annealing or furnace annealing process at a temperature in a range of 200 degrees Celsius to 400 degrees Celsius. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0128] Fig.21A is a vertical cross-sectional view of yet another intermediate structure 2100 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 21B yes Fig.21A A top view of intermediate structure 2100 is shown. Fig. 21C According to various embodiments Fig.21A and Fig. 21B 1702. The intermediate structure 2100 may be formed by depositing a conductive material 1702 over the intermediate structure 2000. The conductive material 1702 may include a metal liner material and a metal fill material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, ​​TiC, TaC, and / or WC. The thickness of the metal liner material may range from approximately 1 nanometer to approximately 10 nanometers, such as approximately 3 nanometers to approximately 8 nanometers, although lesser and greater thicknesses may also be used.

[0129] The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the scope of the present disclosure may also be used. The thickness of the metal filler material may be in the range of approximately 5 nanometers to approximately 150 nanometers (e.g., approximately 20 nanometers to approximately 40 nanometers), but smaller and larger thicknesses may also be used. The metal liner material and the metal filler material may be formed by a suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the scope of the present disclosure.

[0130] Fig.22A is a vertical cross-sectional view of yet another intermediate structure 2200 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 22B yes Fig.22A A top view of intermediate structure 2200 is shown. Fig. 22C According to various embodiments Fig.22A and Fig. 22B Another vertical cross-sectional view of the intermediate structure shown. The intermediate structure 2200 can be formed by forming a patterned photoresist 308 over the intermediate structure 2100. The patterned photoresist 308 can then be used to etch the unmasked portions of the conductive material 1702, thereby forming the gate electrode 116.

[0131] Fig.23A is a vertical cross-sectional view of yet another intermediate structure 2300 that may be used to form the semiconductor circuit 200 according to various embodiments, and Fig. 23B yes Fig.23A A top view of intermediate structure 2300 is shown. Fig.23C According to various embodiments Fig.23A and Fig. 23B 23. Another vertical cross-sectional view of the intermediate structure shown. The intermediate structure 2300 can be formed by performing an anisotropic etching process to remove portions of the conductive material 1702 that are not masked by the patterned photoresist 308 of the intermediate structure 2200. The patterned photoresist 308 can then be removed by ashing or by dissolving with a solvent. As shown, the anisotropic etching process can produce gate electrodes 116 that are electrically separated from each other.

[0132] Fig.24A According to various embodiments, by referring to FIG. 3A to FIG. 23C A vertical cross-sectional view of a semiconductor circuit 200 formed by the process described, and Fig. 24B yes Fig.24A A top view of a semiconductor circuit 200 is shown. Fig.24C According to various embodiments Fig.24A and Fig. 24B Another vertical cross-sectional view of the semiconductor circuit shown, and Fig.24D yes FIG. 24A to FIG. 24C A three-dimensional image of the semiconductor circuit shown. For clarity, Fig.24D The view of FIG. 1 shows the semiconductor circuit 200 with the surrounding interlayer dielectric layer 202L and the gate dielectric layer 118 removed. Fig.24A and Fig.24C The view is provided by Fig.24D The double arrows marked with A and C indicate this.

[0133] FIG. 24A to FIG. 24D The semiconductor circuit 200 may be formed from the intermediate structure 2300 by depositing an additional interlayer dielectric layer 202L. Excess portions of the additional interlayer dielectric layer 202L may be removed above the top surface of the gate electrode 116 by a planarization process. Fig.24A and Fig.24CAs shown, the planarization process can produce a planar surface of the interlayer dielectric layer 202L, which is flush with the surface of the gate electrode 116. In this way, in subsequent processing operations, additional circuit components can be formed above the semiconductor circuit 200. For example, additional interlayer dielectric layers 202L and various electrically interconnected structures can be formed above the semiconductor circuit 200. For example, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 can be electrically connected to one or more electrically interconnected structures that will be formed later on the semiconductor circuit 200. Alternatively or additionally, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b and the gate electrode 116 may be electrically connected to the one or more electrical interconnect structures (142, 144, 146, 148) formed in one or more dielectric material layers (136, 138, 140) beneath the semiconductor circuit 200.

[0134] Fig.25 2 is a flow chart illustrating operations of a method 2500 for forming a semiconductor circuit 200 according to various embodiments. In operation 2502, the method 2500 may include: forming an electrically insulating structure 202 having a planar geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b being parallel to each other and each oriented perpendicular to a thickness direction (e.g., Figure 2A , Figure 2B , Fig.13A and Fig. 13B In operation 2504, the method 2500 may include forming a p-type semiconductor layer 206a on the first surface 204a. In operation 2506, the method 2500 may include forming an n-type semiconductor layer 206b on the second surface 204b. In operation 2508, the method 2500 may include forming a gate dielectric layer 118 in contact with the p-type semiconductor layer 206a and the n-type semiconductor layer 206b. In operation 2510, the method 2500 may include forming a first source electrode 110a and a first drain electrode 112a in contact with the p-type semiconductor layer 206a. In operation 2512, the method 2500 may include forming a second source electrode 110b and a second drain electrode 112b in contact with the n-type semiconductor layer 206b. In operation 2514, the method 2500 may include forming a gate electrode 116 in contact with the gate dielectric layer 118.

[0135] The method 2500 may further include configuring the semiconductor circuit 200 as an inverter circuit (200, 200c) by performing operations including electrically connecting the first source electrode 110a to the voltage source 208 and connecting the second source electrode 110b to the ground voltage terminal 210, electrically connecting the gate electrode 116 to the input signal terminal 212, and electrically connecting the first drain electrode 112a and the second drain electrode 112b to the output signal terminal 214. The method 2500 may further include forming the n-type semiconductor layer 206b to include amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of their alloys.

[0136] The method 2500 may further include forming the p-type semiconductor layer 206a to include one or more of NiO, SnO, and Cu2O. The method 2500 may further include forming the gate dielectric layer 118 to include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina. The method 2500 may further include forming the electrically insulating structure 202 to include AlO x , SiO2 and SiN x The method 2500 may further include forming one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b to include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, and Al.

[0137] With reference to all the drawings and according to various embodiments of the present disclosure, an inverter circuit (200, 200c) is provided. The inverter circuit (200, 200c) may include an electrically insulating structure 202, the electrically insulating structure 202 having a planar geometry including a first surface 204a and a second surface 204b, the first surface 204a and the second surface 204b are parallel to each other and are each oriented perpendicular to the thickness direction (e.g. Figure 2A , Figure 2B , Fig.13A and Fig. 13BThe inverter circuit (200, 200c) may further include a p-type semiconductor layer 206a formed on the first surface 204a, an n-type semiconductor layer 206b formed on the second surface 204b, and a gate dielectric layer 118 formed to contact the p-type semiconductor layer 206a and the n-type semiconductor layer 206b. The inverter circuit (200, 200c) may further include a gate electrode 116 formed to contact the gate dielectric layer 118, a first source electrode 110a and a first drain electrode 112a formed to contact the p-type semiconductor layer 206a, and a second source electrode 110b and a second drain electrode 112b formed to contact the n-type semiconductor layer 206b. The first source electrode 110a may be electrically connected to the voltage source 208, and the second source electrode 110b may be connected to the ground voltage terminal 210. The gate electrode 116 may be connected to the input signal terminal 212 , and the first drain electrode 112 a and the second drain electrode 112 b may be electrically connected to the output signal terminal 214 .

[0138] According to various embodiments, the electrically insulating structure 202 may be formed on an interlayer dielectric layer (150, 202L, 302) having a horizontal interface (see, for example, Figure 1 and FIG. 24A to FIG. 24C ), and the electrically insulating structure 202 may have a vertical orientation such that each of the first surface 204a and the second surface 204b is perpendicular to the horizontal interface of the interlayer dielectric layer (150, 202L, 302). According to various embodiments, the interlayer dielectric layer (150, 202L, 302) may further include one or more electrically interconnected structures (142, 144, 146, 148), and one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, the second drain electrode 112b, and the gate electrode 116 may be electrically connected to the one or more electrically interconnected structures (142, 144, 146, 148). In some embodiments, one or both of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b include a metal oxide semiconductor. For example, one or more of the n-type semiconductor layer 206b and the p-type semiconductor layer 206a may include a metal oxide semiconductor including a multilayer structure. In other embodiments, the n-type semiconductor layer 206b may include an alloy including oxygen, a group III element, and a group V element.

[0139] In some embodiments, the n-type semiconductor layer 206b may include amorphous silicon, Al2O5Zn2-doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO xand one or more of their alloys. In other embodiments, the n-type semiconductor layer 206b may include In x Ga y Zn z The composition given by MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. The p-type semiconductor layer 206a may include one or more of NiO, SnO and Cu2O. Other p-type metal oxide semiconductors may also be used in other embodiments. In various embodiments, the gate dielectric layer 118 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide and hafnium dioxide-alumina, and the electrically insulating structure 202 may include AlO x 、SiO2、SiN x or one or more of other electrically insulating materials.

[0140] In some embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, and Al. In other embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b further include one or more alloys of one or more of W, Mo, Co, Pd, Ti, and mixtures thereof with or without N and / or O, the one or more alloys being deposited by chemical vapor deposition or by atomic layer deposition.

[0141] In an embodiment of the present invention, the electrically insulating structure is formed on an interlayer dielectric layer having a horizontal interface, and wherein the electrically insulating structure has a vertical orientation such that each of the first surface and the second surface is perpendicular to the horizontal interface of the interlayer dielectric layer.

[0142] In an embodiment of the present invention, the interlayer dielectric layer further includes one or more electrically interconnected structures, and wherein one or more of the first source electrode, the first drain electrode, the second source electrode, the second drain electrode and the gate electrode are electrically connected to the one or more electrically interconnected structures.

[0143] In an embodiment of the present invention, at least one of the p-type semiconductor layer and the n-type semiconductor layer includes a metal oxide semiconductor.

[0144] In an embodiment of the present utility model, at least one of the n-type semiconductor layer and the p-type semiconductor layer includes a metal oxide semiconductor, and the metal oxide semiconductor includes a multi-layer structure.

[0145] In an embodiment of the present utility model, the n-type semiconductor layer includes an alloy containing oxygen, group III elements, and group V elements.

[0146] In an embodiment of the present utility model, the n-type semiconductor layer includes one or more of amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and their alloys.

[0147] In an embodiment of the present utility model, the n-type semiconductor layer includes a composition given by In x Ga y Zn z MO, where 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of Ti, Al, Ag, Ce, and Sn.

[0148] In an embodiment of the present utility model, the p-type semiconductor layer includes one or more of NiO, SnO, and Cu2O.

[0149] In an embodiment of the present utility model, the gate dielectric layer includes one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide - bauxite.

[0150] In an embodiment of the present utility model, the electrically insulating structure includes AlO x , SiO2, and SiN x and one or more of them.

[0151] In an embodiment of the present utility model, one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode include one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, and Al.

[0152] In an embodiment of the present utility model, one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode further include one or more alloys of W, Mo, Co, Pd, Ti, and their mixtures with one or more of N and / or O or without N and / or O, and the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition.

[0153] According to other embodiments, a semiconductor circuit 200 is provided. The semiconductor circuit 200 may include: a first layer of a p-type metal oxide semiconductor 206a, formed in the interlayer dielectric layer (150, 202L, 302) along a first vertical plane relative to a horizontal interface of the interlayer dielectric layer (150, 202L, 302); and a second layer of an n-type metal oxide semiconductor 206b, formed in the interlayer dielectric layer (150, 202L, 302) along a second vertical plane relative to a horizontal interface of the interlayer dielectric layer (150, 202L, 302), such that the first layer and the second layer are parallel to each other and separated from each other by a portion of the interlayer dielectric layer (150, 202L, 302) (see, for example, Fig.24A and Fig.24C ).

[0154] The semiconductor circuit 200 may further include: a gate electrode 116 having a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; and a gate dielectric layer 118 (see, for example, Figure 2A , Figure 2B and FIG. 24A to FIG. 24D ), separating the first vertical portion of the gate electrode 116 from the first layer and separating the second vertical portion of the gate electrode 116 from the second layer. The semiconductor circuit 200 may further include: a first source electrode 110a and a first drain electrode 112a, formed to contact the p-type metal oxide semiconductor; and a second source electrode 110b and a second drain electrode 112b, formed to contact the n-type metal oxide semiconductor. In another embodiment, the semiconductor circuit 200 may be configured as an inverter circuit (200, 200c), in which the first source electrode 110a is electrically connected to the voltage source 208, and the second source electrode 110b is connected to the ground voltage terminal 210, the gate electrode 116 is electrically connected to the input signal terminal 212, and the first drain electrode 112a and the second drain electrode 112b are electrically connected to the output signal terminal 214 (see, for example Figure 2B and Figure 2C ).

[0155] According to various embodiments, the n-type metal oxide semiconductor may include amorphous silicon, Al2O5Zn2-doped ZnO, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO xand one or more of their alloys, and the p-type metal oxide semiconductor includes one or more of NiO, SnO, and Cu2O. In other embodiments, the gate dielectric layer 118 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-alumina. In addition, according to some embodiments, one or more of the first source electrode 110a, the first drain electrode 112a, the second source electrode 110b, and the second drain electrode 112b may include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al, and one or more of W, Mo, Co, Pd, Ti, and mixtures thereof, with N and / or O or without N and / or O.

[0156] In an embodiment of the present invention, the semiconductor circuit is configured as an inverter circuit, in which: the first source electrode is electrically connected to a voltage source, and the second source electrode is electrically connected to a ground voltage terminal, the gate electrode is electrically connected to an input signal terminal, and the first drain electrode and the second drain electrode are electrically connected to an output signal terminal.

[0157] In an embodiment of the present invention, the n-type metal oxide semiconductor includes amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of their alloys, and wherein the p-type metal oxide semiconductor comprises one or more of NiO, SnO and Cu2O.

[0158] In an embodiment of the present invention, the gate dielectric layer includes one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide and hafnium dioxide-alumina, and wherein one or more of the first source electrode, the first drain electrode, the second source electrode and the second drain electrode include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al and one or more of W, Mo, Co, Pd, Ti and mixtures thereof, with N and / or O or without N and / or O. According to various embodiments of the present disclosure, a method for forming a semiconductor circuit is provided, comprising: forming an electrically insulating structure having a planar geometry including a first surface and a second surface, wherein the first surface and the second surface are parallel to each other and are each oriented in a corresponding plane perpendicular to a thickness direction; forming a p-type semiconductor layer on the first surface; forming an n-type semiconductor layer on the second surface; forming a gate dielectric layer in contact with the p-type semiconductor layer and the n-type semiconductor layer; forming a first source electrode and a first drain electrode in contact with the p-type semiconductor layer; forming a second source electrode and a second drain electrode in contact with the n-type semiconductor layer; and forming a gate electrode in contact with the gate dielectric layer.

[0159] In an embodiment of the present invention, the method further includes configuring the semiconductor circuit as an inverter circuit by performing operations, the operations including: electrically connecting the first source electrode to a voltage source, and electrically connecting the second source electrode to a ground voltage terminal; electrically connecting the gate electrode to an input signal terminal; and electrically connecting the first drain electrode and the second drain electrode to an output signal terminal.

[0160] In an embodiment of the present invention, the method further comprises: forming the n-type semiconductor layer to include amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and its alloys; forming the p-type semiconductor layer to include at least one of NiO, SnO and Cu2O; forming the gate dielectric layer to include at least one of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide and hafnium dioxide-alumina; forming the electrical insulating structure to include AlO x , SiO2 and SiN xat least one of; and forming one or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode to include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti and Al.

[0161] The above-described embodiments provide semiconductor circuits (200, 200c) and methods that may have advantages in terms of manufacturing flexibility, size reduction, and reduction of short channel effects. In this regard, an embodiment semiconductor circuit (e.g., a CMOS inverter (200, 200c)) is provided, which can be formed in a BEOL process and can be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed semiconductor circuit (200, 200c) may include materials that can be processed at low temperatures, thereby not damaging previously fabricated devices (e.g., FEOL devices and MEOL devices). In addition, the embodiment semiconductor circuit may include a p-channel metal oxide semiconductor field effect transistor (pFET) 216 having a vertical channel layer 206a and an n-channel metal oxide semiconductor field effect transistor (nFET) 218 ​​also having a vertical channel layer 206b. Each of the vertical p-channel 206a and the vertical n-channel 206b can be formed on opposite sides of the vertically oriented electrically insulating structure 202, such that the vertical p-channel 206a and the vertical n-channel 206b are closely spaced relative to each other. Using such vertical channels (206a, 206b) can provide a semiconductor circuit (200, 200c) with reduced size relative to alternative structures that do not include the vertical channels (206a, 206b), and can allow for longer channel lengths without increasing device size, which can mitigate short channel effects.

[0162] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. An inverter circuit, characterized in that: include: An electrically insulating structure having a plate geometry including a first surface and a second surface, the first surface and the second surface being parallel to each other and each oriented in a respective plane perpendicular to the thickness direction; A p-type semiconductor layer formed on the first surface; An n-type semiconductor layer is formed on the second surface; a gate dielectric layer formed to contact the p-type semiconductor layer and the n-type semiconductor layer; a gate electrode formed to contact the gate dielectric layer; a first source electrode and a first drain electrode formed to contact the p-type semiconductor layer; as well as A second source electrode and a second drain electrode are formed to contact the n-type semiconductor layer, wherein the first source electrode is electrically connected to a voltage source, and the second source electrode is electrically connected to a ground voltage terminal, wherein the gate electrode is electrically connected to the input signal terminal, and The first drain electrode and the second drain electrode are electrically connected to an output signal terminal.

2. The inverter circuit according to claim 1, characterized in that: The electrical insulation structure is formed on an interlayer dielectric layer having a horizontal interface, and Wherein the electrically insulating structure has a vertical orientation such that each of the first surface and the second surface is perpendicular to the horizontal interface of the interlayer dielectric layer.

3. The inverter circuit according to claim 1, characterized in that: At least one of the p-type semiconductor layer and the n-type semiconductor layer includes a metal oxide semiconductor.

4. The inverter circuit according to claim 1, characterized in that: At least one of the n-type semiconductor layer and the p-type semiconductor layer includes a metal oxide semiconductor including a multi-layer structure.

5. The inverter circuit according to claim 1, characterized in that: The n-type semiconductor layer includes an alloy including oxygen, a group III element, and a group V element.

6. The inverter circuit according to claim 1, characterized in that: The n-type semiconductor layer includes a composition given by In x Ga y Zn z MO, where 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; and M is one of Ti, Al, Ag, Ce, and Sn.

7. The inverter circuit according to claim 1, characterized in that: The p-type semiconductor layer includes one or more of NiO, SnO, and Cu 2 O.

8. The inverter circuit according to claim 1, characterized in that: One or more of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode further include one or more alloys of one or more of W, Mo, Co, Pd, Ti, and mixtures thereof, with N and / or O or without N and / or O, and the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition.

9. A semiconductor circuit, characterized in that: include: A first layer of a p-type metal oxide semiconductor is formed in the interlayer dielectric layer along a first vertical plane relative to a horizontal interface of the interlayer dielectric layer; a second layer of n-type metal oxide semiconductor formed in the interlayer dielectric layer along a second vertical plane relative to the horizontal interface of the interlayer dielectric layer, such that the first layer and the second layer are parallel to each other and separated from each other by a portion of the interlayer dielectric layer; a gate electrode having a first vertical portion parallel to the first layer and a second vertical portion parallel to the second layer; a gate dielectric layer separating the first vertical portion of the gate electrode from the first layer and separating the second vertical portion of the gate electrode from the second layer; a first source electrode and a first drain electrode formed to contact the p-type metal oxide semiconductor; and A second source electrode and a second drain electrode are formed to be in contact with the n-type metal oxide semiconductor.

10. The semiconductor circuit according to claim 9, characterized in that The semiconductor circuit is configured as an inverter circuit, in which: The first source electrode is electrically connected to a voltage source, and the second source electrode is electrically connected to a ground voltage terminal, The gate electrode is electrically connected to the input signal terminal, and The first drain electrode and the second drain electrode are electrically connected to an output signal terminal.

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