Display panel and display device

Abstract

The utility model provides a display panel and a display device, belongs to the technical field of display, and can solve the problem that liquid crystal molecules in an existing liquid crystal layer scatter light rays and irradiate the light rays to a channel region of a semiconductor layer, and a thin film transistor easily generates large leakage current. The display panel is provided with a plurality of pixel areas and non-pixel areas surrounding the pixel areas. The display panel comprises a first substrate, a second substrate and a liquid crystal layer, wherein the first substrate and the second substrate are oppositely arranged, and the liquid crystal layer is located between the first substrate and the second substrate. The first substrate comprises a first substrate and a plurality of thin film transistors located on the first substrate and arranged in a non-pixel area. The thin film transistor includes: a semiconductor layer on a first substrate; the first substrate further comprises a first shading layer located on the side, away from the first substrate, of the semiconductor layer. The orthographic projection of the first shading layer on the first substrate falls on the side, close to the corresponding pixel area, of the orthographic projection of the channel area of the semiconductor layer on the first substrate.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] Liquid crystal display panels are increasingly widely used in production and life due to their thinner, lighter, more portable and better operability, such as mobile phones, computers, car screens, smart wearable products, projectors, etc. Liquid crystal display panels are generally formed by a pair of array substrates and color filter substrates, and a liquid crystal layer is provided between the array substrate and the color filter substrate. The liquid crystal display panel adjusts the light transmittance of the liquid crystal molecules in the liquid crystal layer through the electric field provided by the array substrate, and uses the color filter substrate to filter light to display images. Utility Model Content

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display panel and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display panel having a plurality of pixel areas and a non-pixel area surrounding the pixel areas, wherein the display panel comprises: a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate; the first substrate comprises: a first base, and a plurality of thin film transistors located on the first substrate and arranged in the non-pixel area; the thin film transistors comprise: a semiconductor layer located on the first base; the first substrate further comprises: a first light shielding layer located on a side of the semiconductor layer away from the first base;

[0005] The orthographic projection of the first light shielding layer on the first substrate falls on a side where the orthographic projection of the channel region of the semiconductor layer on the first substrate is close to the corresponding pixel region.

[0006] In some embodiments, the first substrate further comprises: a second light shielding layer located on a side of the semiconductor layer away from the first base;

[0007] The orthographic projection of the second light shielding layer on the first substrate falls on a side where the orthographic projection of the channel region of the semiconductor layer on the first substrate is away from the corresponding pixel region.

[0008] In some embodiments, the first substrate further includes: a third light shielding layer and a fourth light shielding layer located on a side of the semiconductor layer away from the first base;

[0009] The orthographic projection of the third light shielding layer on the first substrate falls on a side of the orthographic projection of the source contact region of the semiconductor layer on the first substrate away from the channel region;

[0010] The orthographic projection of the fourth light shielding layer on the first substrate falls on a side of the orthographic projection of the drain contact region of the semiconductor layer on the first substrate away from the channel region.

[0011] In some embodiments, the orthographic projections of the first light-shielding layer, the third light-shielding layer, and the fourth light-shielding layer all cover a portion of the orthographic projection of the channel region of the semiconductor layer on the first substrate.

[0012] In some embodiments, the first light-shielding layer, the third light-shielding layer and the fourth light-shielding layer are an integrally formed structure.

[0013] In some embodiments, the first substrate further includes: a second light shielding layer, a third light shielding layer, and a fourth light shielding layer located on a side of the semiconductor layer away from the first base;

[0014] The orthographic projection of the second light shielding layer on the first substrate falls on a side where the orthographic projection of the channel region of the semiconductor layer on the first substrate is away from the corresponding pixel region;

[0015] The orthographic projection of the third light shielding layer on the first substrate falls on a side of the orthographic projection of the source contact region of the semiconductor layer on the first substrate away from the channel region;

[0016] The orthographic projection of the fourth light shielding layer on the first substrate falls on a side of the orthographic projection of the drain contact region of the semiconductor layer on the first substrate away from the channel region.

[0017] In some embodiments, the first light-shielding layer, the second light-shielding layer, the third light-shielding layer and the fourth light-shielding layer are an integrally formed structure.

[0018] In some embodiments, the first light shielding layer has a first edge away from the corresponding pixel region, and a second edge and a third edge connected to the first edge; the channel region of the semiconductor layer has a fourth edge close to the corresponding pixel region, and a fifth edge and a sixth edge connected to the fourth edge;

[0019] The distance between the first edge and the fourth edge is greater than or equal to 2 micrometers;

[0020] The distance between the second edge and the fifth edge is greater than or equal to 2 micrometers;

[0021] A distance between the third edge and the sixth edge is greater than or equal to 2 micrometers.

[0022] In some embodiments, the second substrate includes: a second base, a plurality of color filters located on a side of the second base close to the liquid crystal layer, and a black matrix located between adjacent color filters;

[0023] The orthographic projection of the black matrix on the first substrate covers the orthographic projection of the first light shielding layer on the first substrate.

[0024] In some embodiments, the black matrix has a seventh edge close to the corresponding pixel area; the first light shielding layer has an eighth edge close to the corresponding pixel area;

[0025] A distance between the seventh edge and the eighth edge is greater than or equal to 2 micrometers.

[0026] In some embodiments, the first substrate further includes: a common electrode located on a side of the first light shielding layer away from the first base;

[0027] The first light shielding layer overlaps the common electrode.

[0028] In a second aspect, an embodiment of the present disclosure provides a display device, which includes a display panel as provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a planar structure of an exemplary display panel.

[0030] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the display panel along the AA' direction.

[0031] Figure 3 A schematic diagram of the planar structure of a first display panel provided in an embodiment of the present disclosure.

[0032] Figure 4 for Figure 3 The cross-sectional structure diagram of the display panel along the BB' direction is shown.

[0033] Figure 5 A schematic diagram of the planar structure of a second display panel provided in an embodiment of the present disclosure.

[0034] Figure 6 A schematic diagram of the planar structure of a third display panel provided in an embodiment of the present disclosure.

[0035] Figure 7 A schematic diagram of the planar structure of a fourth display panel provided in an embodiment of the present disclosure.

[0036] Figure 8 A schematic diagram of the planar structure of a fifth display panel provided in an embodiment of the present disclosure.

[0037] Fig. 9 A schematic structural diagram of a sixth display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] Figure 1 is a schematic diagram of a planar structure of an exemplary display panel, Figure 2 for Figure 1 The schematic diagram of the cross-sectional structure of the display panel along the AA' direction is as follows: Figure 1 and Figure 2 As shown, the display panel has a plurality of pixel areas P1 and a non-pixel area P2 surrounding the pixel areas P1, and the display panel includes: a first substrate 10 and a second substrate 20 arranged opposite to each other, and a liquid crystal layer 30 located between the first substrate 10 and the second substrate 20. The first substrate 10 may be specifically an array substrate, which may provide a driving electric field for liquid crystal molecules in the liquid crystal layer 30. The second substrate 20 may be specifically a color filter substrate, which may filter light to achieve a colorful display.

[0041] The first substrate 10 includes: a first base 101, a plurality of thin film transistors located on the first base 101 and arranged in the non-pixel area P2; the thin film transistors include: a gate 102, a gate insulating layer 103, a semiconductor layer 104, a source 105 and a drain 106 arranged in sequence along a direction away from the first base 101. The semiconductor layer 104 can be made of semiconductor materials such as low-temperature polysilicon and metal oxide, and has a channel region 104A and a source contact region 104B and a drain contact region 104C respectively located at both ends of the channel region 104A. The source 105 and the drain 106 are arranged in the same layer and are respectively connected to the source contact region 104B and the drain contact region 104C of the semiconductor layer 104.

[0042] The first substrate 10 also includes: a passivation layer 107 covering the source 105 and the drain 106, a common electrode 108 located on the side of the passivation layer 107 away from the first substrate 101, and a pixel electrode 109 located on the side of the passivation layer 107 close to the first substrate 101. The pixel electrode 109 can be arranged in the film layer where the semiconductor layer 104 is located, which can reduce the overall thickness of the first substrate 10. Both the common electrode 108 and the pixel electrode 109 can be made of transparent conductive materials such as indium tin oxide (ITO) to prevent light from being blocked. The common electrode 108 can be a slit electrode and the pixel electrode 109 can be a planar electrode. An electric field can be generated between the two to drive the liquid crystal molecules in the liquid crystal layer 30 to deflect.

[0043] The first substrate 10 further includes: a cross-arranged gate line 110 and a data line 111. The gate line 110 can be connected to the gate electrode 102 of the thin film transistor to transmit a gate control signal. The data line 111 can be connected to the source electrode 105 of the thin film transistor to transmit a data signal and transmit the data signal to the pixel electrode 109.

[0044] The second substrate 20 includes: a second base 201, a plurality of color filters 202 located on the side of the second base 201 close to the liquid crystal layer 30, and a black matrix 203 located between adjacent color filters 202. The color filter 202 can filter light into monochromatic light of different colors to achieve a colorful display. The black matrix 203 can prevent crosstalk between lights of different colors from affecting the display effect.

[0045] The black matrix 203 can also shield the channel region 104A of the semiconductor layer 104 to prevent light from irradiating the channel region 104A of the semiconductor layer 104, causing the thin film transistor to generate a large leakage current, affecting the display effect. In some application scenarios, such as in a projector, the light generated by the backlight source is incident from one side of the second substrate 20, and the light intensity is relatively large. When the light irradiates the liquid crystal molecules in the liquid crystal layer 30, the liquid crystal molecules in the liquid crystal layer 30 scatter the light, causing part of the light to irradiate the channel region 104A of the semiconductor layer 104. This still easily causes the thin film transistor to generate a large leakage current, affecting the display effect. In other scenarios, when there is strong light incident, it will also affect the display effect.

[0046] In order to solve at least one of the above-mentioned technical problems, the embodiments of the present disclosure provide a display panel and a display device. The display panel and the display device provided by the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0047] In a first aspect, an embodiment of the present disclosure provides a display panel. Figure 3A schematic diagram of a planar structure of a first display panel provided in an embodiment of the present disclosure, Figure 4 for Figure 3 The cross-sectional structure diagram of the display panel along the BB' direction is shown in FIG. Figure 3 and Figure 4 As shown, the display panel has a plurality of pixel areas P1 and a non-pixel area P2 surrounding the pixel area P1, and the display panel includes: a first substrate 10 and a second substrate 20 arranged opposite to each other, and a liquid crystal layer 30 located between the first substrate 10 and the second substrate 20; the first substrate 10 includes: a first base 101, and a plurality of thin film transistors located on the first base 101 and arranged in the non-pixel area P2; the thin film transistor includes: a semiconductor layer 104 located on the first base 101; the first substrate 10 also includes: a first shading layer 112 located on a side of the semiconductor layer 104 away from the first base 101; the orthographic projection of the first shading layer 112 on the first base 101 falls on a side of the orthographic projection of the channel area 104A of the semiconductor layer 104 on the first base 101 close to the corresponding pixel area P1.

[0048] The first substrate 101 can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be but is not limited to one or more of glass and metal foil; the flexible substrate can be but is not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0049] The semiconductor layer 104 may be made of semiconductor materials such as low-temperature polysilicon and metal oxide, and has a channel region 104A and a source contact region 104B and a drain contact region 104C respectively located at two ends of the channel region 104A.

[0050] The first light shielding layer 112 can be made of materials such as metal foil, and its surface is relatively smooth, and has a good light reflection effect. The shape of the first light shielding layer 112 can be rectangular, and the orthographic projection of the first light shielding layer 112 on the first substrate 101 falls on the side of the orthographic projection of the channel region 104A of the semiconductor layer 104 on the first substrate 101 close to the corresponding pixel region P1.

[0051] It should be noted that the corresponding pixel area P1 here refers to the pixel area P1 corresponding to the pixel electrode (described later) connected to the thin film transistor. It is understandable that the shape of the first light shielding layer 112 can be a square, parallelogram, trapezoid, triangle, circle, etc. in addition to a rectangle, which will not be listed here one by one.

[0052] In the display panel provided by the embodiment of the present disclosure, the first light shielding layer 112 can shield the channel region 104A of the semiconductor layer 104 near the corresponding pixel region P1, so that the light scattered by the liquid crystal molecules in the liquid crystal layer 30 can be prevented from irradiating the channel region 104A of the semiconductor layer 104, thereby preventing the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel. At the same time, there is a certain gap between the first light shielding layer 112 and the channel region 104A of the semiconductor layer 104, and the channel region 104A is not covered, so that the first light shielding layer 112 can be prevented from affecting the control signal of the thin film transistor, thereby ensuring the performance of the thin film transistor.

[0053] Figure 5 A schematic diagram of a planar structure of a second display panel provided in an embodiment of the present disclosure, Figure 6 A schematic diagram of a planar structure of a third display panel provided in an embodiment of the present disclosure, Figure 5 and Figure 6 The cross-sectional structure of the display panel shown is similar to Figure 4 Similarly, no more display is performed, such as Figure 5 and Figure 6 As shown, the first substrate 10 also includes: a second shading layer 113 located on the side of the semiconductor layer 104 away from the first base 101; the orthographic projection of the second shading layer 113 on the first base 101 falls on the side of the orthographic projection of the channel region 104A of the semiconductor layer 104 on the first base 101 away from the corresponding pixel area P1.

[0054] It should be noted here that Figure 6 In the display panel shown, the first substrate 10 is a single gate pixel structure, that is, a gate line is arranged between every two adjacent rows of pixel areas P1 to control the on and off of a row of thin film transistors. Figure 3 and Figure 5 In the display panel shown, the first substrate 10 is a dual gate pixel structure, that is, two gate lines (described later) are arranged between each two adjacent rows of pixel areas P1, which can respectively control the on and off of the two rows of thin film transistors. In this way, a data line (described later) can be arranged between each two adjacent rows of pixel areas P1, thereby achieving the purpose of reducing the number of data lines and reducing the difficulty of routing.

[0055] The second light shielding layer 113 can be made of the same material and the same process as the first light shielding layer 112 to reduce the process steps and save the preparation cost. The orthographic projection of the second light shielding layer 113 on the first substrate 101 falls on the side of the orthographic projection of the channel region 104A of the semiconductor layer 104 on the first substrate 101 away from the corresponding pixel region P1. The second light shielding layer 113 can block the area of ​​the channel region 104A of the semiconductor layer 104 away from the corresponding pixel region P1, so that the light scattered by the liquid crystal molecules in the liquid crystal layer 30 can be further prevented from irradiating the channel region 104A of the semiconductor layer 104, thereby avoiding the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel.

[0056] At the same time, there is a certain gap between the second light shielding layer 113 and the channel region 104A of the semiconductor layer 104 and the channel region 104A is not covered, so that the second light shielding layer 113 can be prevented from affecting the control signal of the thin film transistor, thereby ensuring the performance of the thin film transistor.

[0057] It should be further explained that the above Figure 5 and Figure 6 It can be seen that the first substrate 10 in the display panel provided by the embodiment of the present disclosure is a Single Gate pixel structure, and can also be a Dual Gate pixel structure, wherein the first light shielding layer 112 and the second light shielding layer 113 can both play a good light shielding effect, and prevent the thin film transistor from generating a large leakage current. In the following description, the first substrate 10 in the display panel is a Dual Gate pixel structure as an example for explanation, and the Single Gate pixel structure can refer to its implementation principle, and will not be described in detail.

[0058] Figure 7 A schematic diagram of a planar structure of a fourth display panel provided in an embodiment of the present disclosure, Figure 7 The cross-sectional structure of the display panel shown is similar to Figure 4 Similarly, no more display is performed, such as Figure 7 As shown, the first substrate 10 also includes: a third light-shielding layer 114 and a fourth light-shielding layer 115 located on the side of the semiconductor layer 104 away from the first base 101; the orthographic projection of the third light-shielding layer 114 on the first base 101 falls on the side of the orthographic projection of the source contact area 104B of the semiconductor layer 104 on the first base 101 away from the channel area 104A; the orthographic projection of the fourth light-shielding layer 115 on the first base 101 falls on the side of the orthographic projection of the drain contact area 104C of the semiconductor layer 104 on the first base 101 away from the channel area 104A.

[0059] The third light shielding layer 114 and the fourth light shielding layer 115 can be made of the same material and the same process as the first light shielding layer 112 to reduce the process steps and save the preparation cost. The orthographic projection of the third light shielding layer 114 on the first substrate 101 falls on the side of the orthographic projection of the source contact area 104B of the semiconductor layer 104 on the first substrate 101 away from the channel area 104A, and the third light shielding layer 114 can shield the area of ​​the source contact area 104B of the semiconductor layer 104 away from the channel area 104A. The orthographic projection of the fourth light shielding layer 115 on the first substrate 101 falls on the side of the orthographic projection of the drain contact area 104C of the semiconductor layer 104 on the first substrate 101 away from the channel area 104A, and the fourth light shielding layer 115 can shield the area of ​​the drain contact area 104C of the semiconductor layer 104 away from the channel area 104A. In this way, the light scattered by the liquid crystal molecules in the liquid crystal layer 30 can be further prevented from irradiating the channel region 104A of the semiconductor layer 104, thereby preventing the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel.

[0060] At the same time, there is a certain gap between the third light-shielding layer 114 and the fourth light-shielding layer 115 and the channel region 104A of the semiconductor layer 104, and the channel region 104A is not covered, which can prevent the third light-shielding layer 114 and the fourth light-shielding layer 115 from affecting the control signal of the thin film transistor, thereby ensuring the performance of the thin film transistor.

[0061] In some embodiments, the first light shielding layer 112 , the third light shielding layer 114 , and the fourth light shielding layer 115 are an integrally formed structure.

[0062] The first light-shielding layer 112, the third light-shielding layer 114 and the fourth light-shielding layer 115 are connected together to form a semi-enclosed structure, which surrounds the channel region 104A of the semiconductor layer 104 and blocks the upper half of the channel region 104A of the semiconductor layer 104 close to the pixel region P1. In this way, light scattered by the liquid crystal molecules in the liquid crystal layer 30 can be further prevented from irradiating the channel region 104A of the semiconductor layer 104, thereby preventing the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel.

[0063] Figure 8 A schematic diagram of a planar structure of a fifth display panel provided in an embodiment of the present disclosure, Figure 8 The cross-sectional structure of the display panel shown is similar to Figure 4 Similar, no longer displayed, with Figure 7 The display panels shown differ in that Figure 8 In the display panel shown, the orthographic projections of the first light shielding layer 112 , the third light shielding layer 114 and the fourth light shielding layer 115 all cover a portion of the orthographic projection of the channel region 104A of the semiconductor layer 104 on the first substrate 101 .

[0064] The first light-shielding layer 112, the third light-shielding layer 114 and the fourth light-shielding layer 115 can only cover part of the channel region 104A of the semiconductor layer 104, so that there is no gap between the first light-shielding layer 112 and the channel region 104A, between the third light-shielding layer 114 and the channel region 104A, and between the fourth light-shielding layer 115 and the channel region 104A. In this way, the area around the channel region 104A can be completely blocked, and light scattered by the liquid crystal molecules in the liquid crystal layer 30 is further prevented from irradiating the channel region 104A of the semiconductor layer 104, thereby preventing the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel.

[0065] Fig. 9 A schematic diagram of the structure of a sixth display panel provided in an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the first substrate 10 further includes: a second light-shielding layer 113, a third light-shielding layer 114 and a fourth light-shielding layer 115 located on the side of the semiconductor layer 104 away from the first base 101; the orthographic projection of the second light-shielding layer 113 on the first base 101 falls on the side of the channel region 104A of the semiconductor layer 104 on the first base 101 away from the corresponding pixel region P1; the orthographic projection of the third light-shielding layer 114 on the first base 101 falls on the side of the source contact region 104B of the semiconductor layer 104 on the first base 101 away from the channel region 104A; the orthographic projection of the fourth light-shielding layer 115 on the first base 101 falls on the side of the drain contact region 104C of the semiconductor layer 104 on the first base 101 away from the channel region 104A.

[0066] The second light shielding layer 113, the third light shielding layer 114 and the fourth light shielding layer 115 can be made of the same material and the same process as the first light shielding layer 112 to reduce the process steps and save the preparation cost. The orthographic projection of the second light shielding layer 113 on the first substrate 101 falls on the side of the orthographic projection of the channel region 104A of the semiconductor layer 104 on the first substrate 101 away from the corresponding pixel region P1. The second light shielding layer 113 can shield the area of ​​the channel region 104A of the semiconductor layer 104 away from the corresponding pixel region P1. The orthographic projection of the third light shielding layer 114 on the first substrate 101 falls on the side of the orthographic projection of the source contact region 104B of the semiconductor layer 104 on the first substrate 101 away from the channel region 104A. The third light shielding layer 114 can shield the area of ​​the source contact region 104B of the semiconductor layer 104 away from the channel region 104A. The orthographic projection of the fourth light shielding layer 115 on the first substrate 101 falls on the side of the orthographic projection of the drain contact area 104C of the semiconductor layer 104 on the first substrate 101 away from the channel area 104A, and the fourth light shielding layer 115 can shield the area of ​​the drain contact area 104C of the semiconductor layer 104 away from the channel area 104A. In this way, it is possible to further prevent the light scattered by the liquid crystal molecules in the liquid crystal layer 30 from irradiating the channel area 104A of the semiconductor layer 104, thereby preventing the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel.

[0067] In some embodiments, the first light shielding layer 112 , the second light shielding layer 113 , the third light shielding layer 114 , and the fourth light shielding layer 115 are an integrally formed structure.

[0068] The first light-shielding layer 112, the second light-shielding layer 113, the third light-shielding layer 114 and the fourth light-shielding layer 115 are connected together to form an annular surrounding structure, which surrounds the channel region 104A of the semiconductor layer 104 and completely blocks the area around the channel region 104A of the semiconductor layer 104. In this way, light scattered by the liquid crystal molecules in the liquid crystal layer 30 can be further prevented from irradiating the channel region 104A of the semiconductor layer 104, thereby preventing the thin film transistor from generating a large leakage current, thereby improving the display effect of the display panel.

[0069] In some embodiments, Figure 3 As shown, the first light-shielding layer 112 has a first edge away from the corresponding pixel area P1, and a second edge and a third edge connected to the first edge; the channel area 104A of the semiconductor layer 104 has a fourth edge close to the corresponding pixel area, and a fifth edge and a sixth edge connected to the fourth edge; the distance a between the first edge and the fourth edge is greater than or equal to 2 microns; the distance b between the second edge and the fifth edge is greater than or equal to 2 microns; and the distance c between the third edge and the sixth edge is greater than or equal to 2 microns.

[0070] There is a certain gap between each edge of the first light-shielding layer 112 and each edge of the channel region 104A. This gap is generally greater than the alignment accuracy, that is, greater than or equal to 2 microns, and does not cover the channel region 104A. This can prevent the first light-shielding layer 112 from affecting the control signal of the thin-film transistor, thereby ensuring the performance of the thin-film transistor.

[0071] Similarly, the second light-shielding layer 113, the third light-shielding layer 114 and the fourth light-shielding layer 115 can also be set in the same way as the first light-shielding layer 112 to prevent the second light-shielding layer 113, the third light-shielding layer 114 and the fourth light-shielding layer 115 from affecting the control signal of the thin-film transistor, thereby ensuring the performance of the thin-film transistor.

[0072] like Figures 3 to 9 As shown, the second substrate 20 includes: a second substrate 201, a plurality of color filters 202 located on the side of the second substrate 201 close to the liquid crystal layer 30, and a black matrix 203 located between adjacent color filters 202; the orthographic projection of the black matrix 203 on the first substrate 101 covers the orthographic projection of the first shading layer 112 on the first substrate 101.

[0073] The second substrate 201 can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be but is not limited to one or more of glass and metal foil; the flexible substrate can be but is not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0074] The color filter 202 can filter light into monochromatic light of different colors to achieve colorful display. The black matrix 203 can prevent crosstalk between lights of different colors from affecting the display effect.

[0075] The black matrix 203 can also shield the channel region 104A of the semiconductor layer 104 to prevent light from irradiating the channel region 104A of the semiconductor layer 104 and causing the thin film transistor to generate a large leakage current, thereby affecting the display effect.

[0076] In some embodiments, Figure 3 As shown, the black matrix 203 has a seventh edge close to the corresponding pixel area P1; the first light shielding layer 112 has an eighth edge close to the corresponding pixel area P1; and the distance d between the seventh edge and the eighth edge is greater than or equal to 2 micrometers.

[0077] The first light shielding layer 112 can be covered by the black matrix 203, which can prevent the light reflected by the first light shielding layer 112 from being directly emitted, entering the user's field of view, and affecting the display effect. The distance between the seventh edge of the black matrix 203 and the eighth edge of the first light shielding layer 112 should be greater than the alignment accuracy, that is, the distance d between the two is greater than or equal to 2 microns. It is understandable that in other structures, the same method as above can also be used for setting, which will not be described in detail here.

[0078] In some embodiments, Figure 4 As shown, the first substrate 10 further includes: a common electrode 108 located on a side of the first light shielding layer 112 away from the first base 101 ; the first light shielding layer 112 overlaps the common electrode 108 .

[0079] The first light-shielding layer 112 can be overlapped with the common electrode 108, and the common voltage transmitted by the common electrode 108 can be transmitted to the first light-shielding layer 112, so as to prevent the first light-shielding layer 112 from being suspended in a state of no voltage input, thereby avoiding the generation of static electricity, and further preventing static electricity from being released to break through the film layer in the thin-film transistor and affecting the performance of the thin-film transistor.

[0080] It should be noted that the display panel further includes: a gate electrode 102, a gate insulating layer 103, a source electrode 105, a drain electrode 106, a passivation layer 107, a pixel electrode 109, a gate line 110, a data line 111 and other structures, which can be arranged in the same manner as in the related art, and can refer to the embodiments of the present disclosure for providing Figure 1 and Figure 2 The description will not be described in detail here.

[0081] In a second aspect, an embodiment of the present disclosure provides a display device, which includes a display panel as provided in any of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, a projector, or any other product with a display function. Other essential components of the display device should be understood by a person of ordinary skill in the art, and will not be elaborated here, nor should they be used as a limitation to the present disclosure.

[0082] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel having a plurality of pixel areas and non-pixel areas surrounding the pixel areas, characterized in that: The display panel comprises: a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate; the first substrate comprises: a first base, and a plurality of thin film transistors located on the first substrate and arranged in the non-pixel area; the thin film transistors comprise: a semiconductor layer located on the first substrate; the first substrate further comprises: a first light shielding layer located on a side of the semiconductor layer away from the first base; The orthographic projection of the first light shielding layer on the first substrate falls on a side where the orthographic projection of the channel region of the semiconductor layer on the first substrate is close to the corresponding pixel region.

2. The display panel according to claim 1, characterized in that: The first substrate further comprises: a second light shielding layer located on a side of the semiconductor layer away from the first base; The orthographic projection of the second light shielding layer on the first substrate falls on a side where the orthographic projection of the channel region of the semiconductor layer on the first substrate is away from the corresponding pixel region.

3. The display panel according to claim 1, characterized in that: The first substrate further includes: a third light shielding layer and a fourth light shielding layer located on a side of the semiconductor layer away from the first base; The orthographic projection of the third light shielding layer on the first substrate falls on a side of the orthographic projection of the source contact region of the semiconductor layer on the first substrate away from the channel region; The orthographic projection of the fourth light shielding layer on the first substrate falls on a side of the orthographic projection of the drain contact region of the semiconductor layer on the first substrate away from the channel region.

4. The display panel according to claim 3, characterized in that: The orthographic projections of the first light-shielding layer, the third light-shielding layer, and the fourth light-shielding layer all cover a portion of the orthographic projections of the channel region of the semiconductor layer on the first substrate.

5. The display panel according to claim 3 or 4, characterized in that: The first light-shielding layer, the third light-shielding layer and the fourth light-shielding layer are an integrally formed structure.

6. The display panel according to claim 1, characterized in that: The first substrate further includes: a second light shielding layer, a third light shielding layer and a fourth light shielding layer located on a side of the semiconductor layer away from the first base; The orthographic projection of the second light shielding layer on the first substrate falls on a side where the orthographic projection of the channel region of the semiconductor layer on the first substrate is away from the corresponding pixel region; The orthographic projection of the third light shielding layer on the first substrate falls on a side of the orthographic projection of the source contact region of the semiconductor layer on the first substrate away from the channel region; The orthographic projection of the fourth light shielding layer on the first substrate falls on a side of the orthographic projection of the drain contact region of the semiconductor layer on the first substrate away from the channel region.

7. The display panel according to claim 6, characterized in that: The first light-shielding layer, the second light-shielding layer, the third light-shielding layer and the fourth light-shielding layer are an integrated structure.

8. The display panel according to claim 1, characterized in that: The first light shielding layer has a first edge away from the corresponding pixel area, and a second edge and a third edge connected to the first edge; the channel area of ​​the semiconductor layer has a fourth edge close to the corresponding pixel area, and a fifth edge and a sixth edge connected to the fourth edge; The distance between the first edge and the fourth edge is greater than or equal to 2 micrometers; The distance between the second edge and the fifth edge is greater than or equal to 2 micrometers; A distance between the third edge and the sixth edge is greater than or equal to 2 micrometers.

9. The display panel according to claim 1, characterized in that: The second substrate comprises: a second base, a plurality of color filters located on a side of the second base close to the liquid crystal layer, and a black matrix located between adjacent color filters; The orthographic projection of the black matrix on the first substrate covers the orthographic projection of the first light shielding layer on the first substrate.

10. The display panel according to claim 9, characterized in that: The black matrix has a seventh edge close to the corresponding pixel area; the first light shielding layer has an eighth edge close to the corresponding pixel area; A distance between the seventh edge and the eighth edge is greater than or equal to 2 micrometers.

11. The display panel according to claim 1, characterized in that: The first substrate further includes: a common electrode located on a side of the first light shielding layer away from the first base; The first light shielding layer overlaps the common electrode.

12. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 11.

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