Array substrate, display panel, display device and head-up display system

Abstract

The array substrate comprises a display area and a peripheral area, the peripheral area is internally provided with a binding area, the display area is internally provided with a plurality of temperature testing areas, and the array substrate comprises a substrate body, a plurality of temperature sensors and a plurality of temperature sensors, the plurality of temperature sensing coils are located on the substrate base plate, and the plurality of temperature sensing coils are located in the plurality of temperature testing areas respectively; the signal transmission parts are located on the substrate and electrically connected with the temperature sensing coils respectively, each signal transmission part comprises a first wire and a second wire, the first wires are electrically connected with the input ends of the temperature sensing coils and extend to the binding area, and the second wires are electrically connected with the input ends of the temperature sensing coils and extend to the binding area. The second wire is electrically connected with the output end of the temperature sensing coil and extends to the binding area; the array substrate further comprises a plurality of signal wires, and the orthographic projection of the temperature sensing coil on the substrate is at least partially overlapped with the orthographic projection of the signal wires on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a display device and a head-up display system. Background Art

[0002] In some usage scenarios of display panels, the display area will be exposed to a fixed-size solar spot, causing a serious local temperature rise, resulting in display abnormalities or hardware damage. In this case, if the temperature sensor detection area does not pass through the spot or the detection area does not cover the entire panel, the specific temperature of the temperature rising area cannot be accurately detected, resulting in temperature recognition errors.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Utility Model Content

[0004] In one aspect, an array substrate is provided.

[0005] The array substrate includes a display area and a peripheral area located around the display area, a plurality of temperature test areas are arranged in the display area, and the plurality of temperature test areas are arranged along a first direction and / or a second direction, a binding area is arranged in the peripheral area, and the binding area is located on one side of the display area along the second direction, and the array substrate includes:

[0006] substrate substrate;

[0007] a plurality of temperature sensing coils located on the substrate, the plurality of temperature sensing coils being located in the plurality of temperature testing regions respectively; and

[0008] A plurality of signal transmission parts located on the substrate, the plurality of signal transmission parts are electrically connected to the plurality of temperature sensing coils respectively, the signal transmission parts include a first routing line and a second routing line, one end of the first routing line is electrically connected to the input end of the temperature sensing coil, the other end of the first routing line extends to the binding area, one end of the second routing line is electrically connected to the output end of the temperature sensing coil, the other end of the second routing line extends to the binding area;

[0009] Among them, the array substrate also includes a plurality of signal lines located on the array substrate, the plurality of signal lines are arranged along the first direction and extend along the second direction, and the orthographic projection of the temperature sensing coil on the base substrate at least partially overlaps with the orthographic projection of the signal lines on the base substrate.

[0010] According to some exemplary embodiments, the display area includes a plurality of sub-pixel opening areas and non-opening areas located between adjacent sub-pixel opening areas, and the sub-pixel opening areas include a light-transmitting area and a non-light-transmitting area;

[0011] Wherein, at least a portion of the temperature sensing coil is located in the non-opening area, and / or at least a portion of the temperature sensing coil is located in the non-light-transmitting area.

[0012] According to some exemplary embodiments, the temperature sensing coil includes a plurality of sensing traces, a plurality of first connecting segments, and a plurality of second connecting segments, the plurality of sensing traces being arranged along the first direction and extending along the second direction;

[0013] Two adjacent sensing lines whose ends are away from the binding area are electrically connected through the first connection segment, and two adjacent sensing lines whose ends are close to the binding area are electrically connected through the second connection segment, and the plurality of first connection segments and the plurality of second connection segments are alternately electrically connected to the two adjacent sensing lines; and

[0014] The orthographic projections of the plurality of sensing lines on the substrate at least partially overlap with the orthographic projections of the plurality of signal lines on the substrate.

[0015] According to some exemplary embodiments, the array substrate comprises a plurality of scan lines located on the base substrate, the plurality of scan lines are arranged along the second direction and extend along the first direction;

[0016] The orthographic projection of the first connecting section on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate; and / or

[0017] The orthographic projection of the second connecting segment on the base substrate is adjacent to and spaced from the orthographic projection of the scanning line on the base substrate.

[0018] According to some exemplary embodiments, at least one first dummy routing segment is further arranged between two adjacent sensing routing lines, the first dummy routing segment is spaced apart from the two adjacent sensing routing lines, and the orthographic projection of the first dummy routing segment on the substrate is adjacent to and spaced apart from the orthographic projection of the scanning line on the substrate.

[0019] According to some exemplary embodiments, among the two temperature sensing coils adjacent to each other along the second direction, at least a portion of the signal transmission portion electrically connected to the temperature sensing coil further away from the binding area is located in the temperature testing area where the temperature sensing coil closer to the binding area is located;

[0020] In two temperature test areas adjacent to each other along the second direction, both temperature test areas include a dummy area, the temperature sensing coil is located in an area of ​​the temperature test area other than the dummy area, an extension length of the temperature sensing coil in one temperature test area is substantially equal to an extension length of the temperature sensing coil in the other temperature test area, and an area of ​​the dummy area closer to the binding area is smaller than an area of ​​the dummy area farther from the binding area; or

[0021] Among two temperature testing areas adjacent to each other along the second direction, only the temperature testing area farther away from the binding area includes a dummy area, the temperature sensing coil is located in an area other than the dummy area in the temperature testing area, and an extension length of the temperature sensing coil in one of the temperature testing areas is substantially equal to an extension length of the temperature sensing coil in the other of the temperature testing areas.

[0022] According to some exemplary embodiments, at least one second dummy routing segment and at least one third dummy routing segment are provided in the dummy area;

[0023] The orthographic projection of the second dummy routing segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate, and the orthographic projection of the second dummy routing segment on the substrate is located between the orthographic projections of the two signal routing lines on the substrate;

[0024] The orthographic projection of the third dummy routing segment on the substrate at least partially overlaps with the orthographic projection of the signal routing segment on the substrate, and the orthographic projection of the third dummy routing segment on the substrate is located between the orthographic projections of the two scanning lines on the substrate.

[0025] According to some exemplary embodiments, the plurality of temperature sensing coils arranged along the second direction include a distal temperature sensing coil farthest from the binding area and at least one proximal temperature sensing coil located on a side of the distal temperature sensing coil close to the binding area;

[0026] In which, the signal transmission part electrically connected to the proximal temperature sensing coil has a compensation coil located in the peripheral area, and among the two proximal temperature sensing coils adjacent to each other along the second direction, the resistance of the compensation coil electrically connected to the proximal temperature sensing coil farther away from the binding area is smaller than the resistance of the compensation coil electrically connected to the proximal temperature sensing coil closer to the binding area.

[0027] According to some exemplary embodiments, the array substrate also includes a gate metal layer located on the base substrate, a source-drain metal layer located on a side of the gate metal layer away from the base substrate, a common electrode layer located on a side of the source-drain metal layer away from the base substrate, and a sensing metal layer located between the source-drain metal layer and the common electrode layer, and the temperature sensing coil and the signal transmission unit are located in the sensing metal layer.

[0028] According to some exemplary embodiments, the common electrode layer includes a common electrode, and an orthographic projection of the common electrode on the base substrate covers at least a portion of an orthographic projection of the temperature sensing coil on the base substrate.

[0029] According to some exemplary embodiments, the plurality of signal lines include a plurality of data lines and a plurality of common electrode lines, and the plurality of data lines and the plurality of common electrode lines are alternately arranged along the first direction;

[0030] The orthographic projection of the sensing line on the base substrate at least partially overlaps with the orthographic projection of the common electrode line on the base substrate.

[0031] According to some exemplary embodiments, the array substrate further includes a pixel electrode layer located on the base substrate, the pixel electrode layer including a plurality of pixel electrodes; and

[0032] The plurality of scan lines include a plurality of scan line groups, the scan line group includes two scan lines, and the orthographic projection of the scan line group on the base substrate is located between the orthographic projections of two adjacent pixel electrodes along the second direction on the base substrate;

[0033] Wherein, at least a part of the orthographic projection of the first connecting segment on the substrate is located between the orthographic projections of two scanning lines in the scanning line group on the substrate; and / or

[0034] At least a portion of the orthographic projection of the second connecting segment on the substrate is located between the orthographic projections of two scanning lines in the scanning line group on the substrate.

[0035] According to some exemplary embodiments, the common electrode line is located in the source-drain metal layer, the array substrate includes a first passivation layer located between the source-drain metal layer and the sensing metal layer, and a second passivation layer located between the sensing metal layer and the common electrode layer, the first passivation layer and the second passivation layer have via holes, the via holes expose a portion of the common electrode line, the common electrode layer includes a common electrode, and the common electrode is electrically connected to the common electrode line through the via holes;

[0036] The sensing trace includes a plurality of sensing segments arranged along the second direction, two adjacent sensing segments are electrically connected via a connecting portion, and an orthographic projection of the connecting portion on the base substrate is spaced apart from an orthographic projection of the via hole on the base substrate.

[0037] According to some exemplary embodiments, the connecting portion is ring-shaped, and an orthographic projection of the via hole on the base substrate is located within an orthographic projection of the connecting portion on the base substrate.

[0038] According to some exemplary embodiments, the plurality of signal traces include a plurality of data traces, and an orthographic projection of the sensing trace on the substrate at least partially overlaps with an orthographic projection of the data trace on the substrate.

[0039] According to some exemplary embodiments, the array substrate further includes a pixel electrode layer located on the base substrate, the pixel electrode layer including a plurality of pixel electrodes; and

[0040] The pixel electrode comprises a first electrode portion and a second electrode portion connected along the second direction, the first electrode portion extends along a third direction, the second electrode portion extends along a fourth direction, and the third direction intersects the fourth direction;

[0041] The orthographic projection of the edge where the first electrode portion is connected to the second electrode portion on the substrate is located within the orthographic projection of the first connecting section on the substrate; and / or

[0042] An orthographic projection of an edge of the first electrode portion connected to the second electrode portion on the base substrate is located within an orthographic projection of the second connecting segment on the base substrate.

[0043] According to some exemplary embodiments, the first routing line includes a first routing line segment located in the display area, one end of the first routing line segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and

[0044] The second routing includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction toward the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

[0045] According to some exemplary embodiments, the first routing line includes a first routing line segment located in the display area, one end of the first routing line segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and

[0046] The second routing includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction away from the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

[0047] According to some exemplary embodiments, the first routing segment includes at least two first routing sub-segments, the two first routing sub-segments are electrically connected via at least one third connecting segment, the orthographic projections of the two first routing sub-segments on the substrate substrate respectively overlap at least partially with the orthographic projections of two adjacent signal routing lines on the substrate substrate, and the orthographic projection of the third connecting segment on the substrate substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate substrate; and / or

[0048] The third routing segment includes at least two third routing sub-segments, the two third routing sub-segments are electrically connected through at least one fourth connecting segment, the orthographic projections of the two third routing sub-segments on the substrate respectively overlap at least partially with the orthographic projections of two adjacent signal routing lines on the substrate, and the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

[0049] According to some exemplary embodiments, the plurality of temperature test areas include at least one special-shaped temperature test area, and of the two sides of the special-shaped temperature test area located on both sides of the second direction, an extension direction of one side is parallel to the first direction, and an extension direction of the other side intersects with the first direction or the other side is a curved side;

[0050] Wherein, the special-shaped temperature test area includes a test area, the shape of the test area is rectangular, the temperature sensing coil is located in the test area, and the lengths of the sensing lines along the second direction are substantially equal;

[0051] or

[0052] The sensing coil is located in the special-shaped temperature test area, and the lengths of at least two sensing lines along the second direction are different from each other.

[0053] According to some exemplary embodiments, the array substrate also includes at least one peripheral temperature sensing coil located in the peripheral area, an input end of the peripheral temperature sensing coil is electrically connected to an input terminal in the binding area through an input trace, and the input trace is used to connect a driving signal provided by the input terminal to the peripheral temperature sensing coil, and an output end of the peripheral temperature sensing coil is electrically connected to an output terminal in the binding area through an output trace, and the output trace is used to transmit a sensing signal generated by the peripheral temperature sensing coil to the output terminal.

[0054] In another aspect, a display panel is provided, comprising the array substrate as described above.

[0055] In another aspect, a display device is provided, comprising the display panel as described above.

[0056] In another aspect, a head-up display system is provided, comprising the display panel as described above and an optical path magnifying element.

[0057] According to some exemplary embodiments, the optical path magnifying element includes a concave mirror. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0059] Figure 1A The figure schematically shows a pixel arrangement plan view of an array substrate according to some embodiments of the present disclosure.

[0060] Figure 1B Schematically illustrates a pixel arrangement plan view of an array substrate according to some other embodiments of the present disclosure.

[0061] Figure 2A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0062] Figure 2B Schematically illustrating a plan view of an array substrate according to some other embodiments of the present disclosure.

[0063] Figure 2C The plan views of array substrates according to some further embodiments of the present disclosure are schematically shown.

[0064] Figure 2D The plan views of array substrates according to some further embodiments of the present disclosure are schematically shown.

[0065] Figure 3 Schematically shows Figure 2A Enlarged view of area S1 in the middle.

[0066] Figure 4 Schematically shows Figure 2A Enlarged view of area S2 in the middle.

[0067] Figure 5 Schematically shows Figure 4 Enlarged view of area S3 in the middle.

[0068] Figure 6 Schematically shows Figure 2A Enlarged view of the middle area S10.

[0069] Figure 7 Schematically shows Figure 4 Enlarged view of area S4 in the middle.

[0070] Figure 8 The array substrate according to one embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of area S5 in the middle.

[0071] Fig. 9 Schematically shows Figure 8 Schematic diagram taken along line AA'.

[0072] Fig. 10A Schematically shows Figure 8 Schematic diagram taken along line BB'.

[0073] Fig. 10B Schematically shows Figure 8 Schematic diagram taken along line CC'.

[0074] Fig.11 The array substrate according to one embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of middle area S6.

[0075] Fig.12 The array substrate according to one embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of middle area S7.

[0076] Fig.13A The array substrate according to another embodiment of the present disclosure is schematically shown in FIG. Figure 7 Enlarged view of the middle area S8.

[0077] Fig. 13B Schematically Figure 7 Magnified view of middle area S9.

[0078] Fig.14 Schematically Figure 7 Enlarged view of the middle area S11.

[0079] Fig.15Schematically illustrates a pixel arrangement plan view of an array substrate according to some other embodiments of the present disclosure.

[0080] Fig.16 The array substrate according to another embodiment of the present disclosure is schematically shown in FIG. Figure 7 Enlarged view of area S5 in the middle.

[0081] Fig.17 The array substrate according to another embodiment of the present disclosure is schematically shown in FIG. Figure 7 Enlarged view of area S5 in the middle.

[0082] Fig.18 The diagram schematically shows a distribution diagram of a temperature test area in a display area of ​​an array substrate according to some embodiments of the present disclosure.

[0083] Fig.19 The diagram schematically shows the distribution of temperature sensing coils in a special-shaped temperature test area of ​​an array substrate according to some embodiments of the present disclosure.

[0084] Fig. 20 The distribution diagram of the temperature sensing coils in the special-shaped temperature test area of ​​the array substrate according to some other embodiments of the present disclosure is schematically shown.

[0085] Fig.21 The planar area of ​​the peripheral temperature sensing coil of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0086] Fig. 22 A schematic diagram of a display panel according to an embodiment of the present disclosure is schematically shown.

[0087] Fig.23 The flowchart of the temperature measurement method of the display panel according to the embodiment of the present disclosure is schematically shown.

[0088] Fig.24 The figure schematically shows a timing diagram of a driving signal in a temperature measurement method of a display panel according to an embodiment of the present disclosure.

[0089] Fig.25 A timing diagram of a driving signal in another temperature measurement method of a display panel according to an embodiment of the present disclosure is schematically shown.

[0090] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0091] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0092] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0093] When an element is described as "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on another element, directly connected to another element or directly coupled to another element, or there may be an intermediate element. However, when an element is described as "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0094] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named a second element, and similarly, a second element may be named a first element.

[0095] Figure 1A The figure schematically shows a pixel arrangement plan view of an array substrate according to some embodiments of the present disclosure. Figure 1B Schematically illustrates a pixel arrangement plan view of an array substrate according to some other embodiments of the present disclosure.

[0096] According to an embodiment of the present disclosure, an array substrate is provided, referring to Figure 1A or Figure 1B The array substrate may include: a base substrate and a plurality of sub-pixels P located on the base substrate. The plurality of sub-pixels P are arranged on the base substrate 10 in an array form, that is, including a plurality of rows of sub-pixels P and a plurality of columns of sub-pixels P. In this document, for the convenience of description, Figure 1A The horizontal direction in is called the first direction X, that is, the row direction. Figure 1A The vertical direction in is called the second direction Y, that is, the column direction.

[0097] For example, the array substrate may include a plurality of scan lines GL extending along a first direction X and arranged along a second direction Y and a plurality of signal lines SL extending along the second direction Y and arranged along the first direction X. The plurality of signal lines SL and the plurality of scan lines GL intersect with each other to define a plurality of sub-pixels P.

[0098] Figure 2A The plan view of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0099] Reference Figure 2A The array substrate includes a display area AA and a peripheral area NA located around the display area AA. A plurality of temperature test areas TA are arrayed in the display area AA. The plurality of temperature test areas TA are arranged along a first direction X and a second direction Y. For example, the shape of the temperature test area TA may be a rectangle, a trapezoid, a triangle, or other shapes. The area of ​​the temperature test area TA is determined according to the actual required temperature test accuracy. The smaller the area of ​​the temperature test area TA, the higher the test accuracy.

[0100] Exemplarily, when the array substrate is applied to a head-up display device, an optical path amplifying element is provided in the head-up display device, and the optical path amplifying element may include a concave mirror. The concave mirror also has the characteristic of optical focusing, and the sunlight irradiated to the array substrate will be converged by the concave mirror to form a solar spot. Based on this, in order to accurately identify the problem of excessive local temperature caused by the irradiation of the solar spot, the area of ​​the temperature test area TA can be set to be approximately equal to the area of ​​the solar spot, or the area of ​​the temperature test area TA can be set to be smaller than the area of ​​the solar spot. For example, the shape of the solar spot is approximately a circle with a diameter of 10 mm. According to the size of the solar spot, the size of the temperature test area TA along the first direction X is set to be less than or equal to 10 mm, and the size of the temperature test area TA along the second direction Y is set to be less than or equal to 10 mm.

[0101] In some embodiments, the array substrate also includes multiple temperature sensing coils 20, and the multiple temperature sensing coils 20 are respectively located in multiple temperature testing areas TA. The multiple temperature sensing coils 20 are respectively used to test the temperatures of the parts of the array substrate located in the multiple temperature testing areas TA, thereby realizing regional temperature detection of the array substrate.

[0102] Continue to refer to Figure 2A , the array substrate includes a plurality of signal transmission parts 30. The signal transmission part 30 includes a first wiring 31 and a second wiring 32. One end of the first wiring 31 is electrically connected to the input end of the temperature sensing coil 20, and the other end of the first wiring 31 extends to the binding area BA and is electrically connected to the input terminal located in the binding area BA. The first wiring 31 is used to receive the driving signal provided by the input terminal and connect the driving signal to the temperature sensing coil 20. One end of the second wiring 32 is electrically connected to the output end of the temperature sensing coil 20, and the other end of the second wiring 32 extends to the binding area BA and is electrically connected to the output terminal located in the binding area BA. The second wiring 32 is used to receive the sensing signal generated by the temperature sensing coil 20 in response to the driving signal and transmit the sensing signal to the output terminal.

[0103] In some embodiments, the positions of the output end and the input end of the temperature sensing coil 20 can be exchanged according to actual needs, that is, the output end of the temperature sensing coil 20 is electrically connected to the first wiring 31, and the input end of the temperature sensing coil 20 is electrically connected to the second wiring 32.

[0104] In some embodiments, the binding area BA is located in the peripheral area NA, and the binding area BA is located at one side of the display area AA along the second direction Y.

[0105] In some embodiments, the input terminal and the output terminal in the binding area are electrically connected to a flexible printed circuit board (FPC), and the flexible printed circuit board is electrically connected to a printed circuit board (PCB), and the temperature detection circuit is arranged on the printed circuit board, that is, the printed circuit board is connected to the temperature sensing coil located in the array substrate through the flexible printed circuit board. The temperature detection circuit arranged in the printed circuit board connects the driving signal to the input end of the temperature sensing coil through the flexible printed circuit board, and obtains the sensing signal output by the output end of the temperature sensing coil through the flexible printed circuit board, and finally the temperature of the portion of the array substrate corresponding to the temperature test area can be obtained according to the sensing signal.

[0106] In some embodiments, the flexible circuit board for transmitting temperature detection related signals and the flexible circuit board for transmitting display related signals may be integrated into one flexible circuit board to reduce the layout space of the flexible circuit board.

[0107] In some embodiments, the temperature detection circuit may also be directly placed in the peripheral area of ​​the array substrate. For example, the input terminal and the output terminal in the binding area are electrically connected to the driver chip, and the temperature detection circuit is disposed in the driver chip.

[0108] According to some exemplary embodiments, the display area includes a plurality of sub-pixel opening areas and a non-opening area between adjacent sub-pixel opening areas, and the sub-pixel opening area includes a light-transmitting area and a non-light-transmitting area. Exemplarily, the temperature sensing coil is arranged in the non-opening area, or a part of the temperature sensing coil is arranged in the non-opening area and another part is arranged in the non-light-transmitting area, or the temperature sensing coil is arranged in the non-light-transmitting area. That is, the temperature sensing coil is arranged in an area of ​​the array substrate that is not used for display, so as to avoid the problem of affecting the display effect due to the arrangement of the temperature sensing coil.

[0109] According to some exemplary embodiments, referring to Figure 2A , multiple temperature test areas TA can be arranged in a close array, and the temperature test areas TA adjacent to each other along the first direction X are directly connected, and the temperature test areas TA adjacent to each other along the second direction Y are directly connected. That is, the display area AA can be divided into multiple temperature test areas TA according to actual test requirements, so as to achieve complete partition temperature monitoring of the portion of the array substrate located in the display area AA.

[0110] Figure 2B Schematically illustrating a plan view of an array substrate according to some other embodiments of the present disclosure.

[0111] According to some exemplary embodiments, only part of the display area can be used as the temperature test area according to actual needs. For example, only the location where the sun spot has a high probability of appearing can be used as the temperature test area to set the temperature sensing coil. Figure 2B, multiple temperature test areas TA are arranged in the display area AA, and there is a certain spacing distance between adjacent temperature test areas TA. According to this arrangement, the arrangement space of the signal transmission part 30 in the peripheral area NA can be reduced, and the area of ​​the binding area BA for arranging the output terminal and the input terminal can also be reduced. In addition, the processing complexity of calculating the corresponding temperature information according to the sensing signal output by each temperature sensing coil 20 is also reduced.

[0112] According to some exemplary embodiments, referring to Figure 2B In order to ensure the wiring uniformity in the display area AA, a dummy line can be set in the interval area between the temperature test areas TA. The setting method of the dummy line is described in detail below.

[0113] According to some exemplary embodiments, referring to Figure 2A Two binding areas BA are arranged in the peripheral area NA, and the two binding areas BA are arranged along the first direction X. The peripheral area NA includes a first peripheral area NA1 and a second peripheral area NA2 respectively located on both sides of the display area AA along the first direction X. A plurality of temperature test areas TA (for example, Figure 2A The 9 temperature test areas TA arranged in 3 rows and 3 columns on the left side are electrically connected to the input terminal and the output terminal in the binding area BA closer to the first peripheral area NA1. At the same time, the signal transmission part 30 is electrically connected to the end of the temperature sensing coil 20 close to the first peripheral area NA1. Similarly, multiple temperature test areas TA (for example, Figure 2A The 9 temperature test areas TA) arranged in 3 rows * 3 columns on the right side shown in the figure are electrically connected to the input terminals and output terminals in the binding area BA closer to the second peripheral area NA2. At the same time, the signal transmission part 30 is electrically connected to one end of the temperature sensing coil 20 close to the second peripheral area NA2.

[0114] Figure 2C The plan views of array substrates according to some further embodiments of the present disclosure are schematically shown.

[0115] According to some exemplary embodiments, referring to Figure 2C Two binding areas BA are arranged in the peripheral area NA, and the two binding areas BA are arranged along the first direction X. The peripheral area NA includes a first peripheral area NA1 and a second peripheral area NA2 respectively located on both sides of the display area AA along the first direction X. A plurality of temperature test areas TA (for example, Figure 2AThe 9 temperature test areas TA arranged in 3 rows and 3 columns on the left side are electrically connected to the input terminal and the output terminal in the binding area BA closer to the first peripheral area NA1. At the same time, the signal transmission part 30 is electrically connected to the end of the temperature sensing coil 20 away from the first peripheral area NA1. Similarly, multiple temperature test areas TA closer to the second peripheral area NA2 (for example, Figure 2A The 9 temperature test areas TA) arranged in 3 rows * 3 columns on the right side shown in the figure are electrically connected to the input terminals and output terminals in the binding area BA closer to the second peripheral area NA2. At the same time, the signal transmission part 30 is electrically connected to the end of the temperature sensing coil 20 away from the second peripheral area NA2.

[0116] It should be supplemented that the connection position of the temperature sensing coil and the signal transmission part can be set in combination with the position of the binding area, and can be set on the principle of reducing the length of the first routing line and the second routing line in the signal transmission part as much as possible, thereby reducing the routing resistance of the signal transmission part.

[0117] According to some exemplary embodiments, in the plurality of temperature sensing coils arranged along the second direction, the connection positions of the plurality of temperature sensing coils and the signal transmission unit may also be arranged alternately along the first direction. For example, in two temperature sensing coils adjacent to each other along the second direction, the outlet end of one temperature sensing coil is located on one side of the first direction, that is, one end of the temperature sensing coil along the first direction is electrically connected to the signal transmission unit, and the outlet end of the other temperature sensing coil is located on the other side of the first direction, that is, the other end of the temperature sensing coil along the first direction is electrically connected to the signal transmission unit. According to some exemplary embodiments, the display area includes an effective display area and a dummy display area located around the effective display area. In actual display, the sub-pixels in the effective display area are used for display, while the sub-pixels in the dummy display area are not used for display. The temperature test area close to the peripheral area is located in the effective display area, that is, the temperature sensing coil is also located in the effective display area, and the temperature sensing coil is used to test the temperature of the part actually used for display in the array substrate.

[0118] According to some exemplary embodiments, based on actual temperature testing requirements, the dummy display area can also be used as part of the temperature testing area, a part of the temperature testing area close to the peripheral area is located in the dummy display area, and the remaining part is located in the effective display area, that is, a part of the temperature sensing coil is located in the dummy display area and the remaining part is located in the effective display area.

[0119] According to some exemplary embodiments, a portion of the temperature test area close to the peripheral area is located in the dummy display area, and the remaining portion is located in the effective display area. The temperature sensing coil is only arranged in the effective display area, and the portion of the temperature test area located in the dummy display area is used to set the dummy routing.

[0120] Figure 3 Schematically shows Figure 2A Enlarged view of area S1 in the middle.

[0121] Reference Figure 3 The orthographic projection of the temperature sensing coil 20 on the substrate at least partially overlaps with the orthographic projection of the signal line SL on the substrate. By overlapping the temperature sensing coil 20 with the signal line SL located in the non-opening area, it is beneficial to reduce the area of ​​the non-opening area, thereby improving the aperture ratio of the array substrate.

[0122] According to some exemplary embodiments, referring to Figure 3 The temperature sensing coil 20 has a serpentine routing structure, and the temperature sensing coil 20 includes a plurality of sensing routing lines 21, a plurality of first connecting segments 22, and a plurality of second connecting segments 23. The plurality of sensing routing lines 21 are arranged along the first direction X and extend along the second direction Y. The ends of two adjacent sensing routing lines 21 away from the binding area are electrically connected through the first connecting segment 22, and the ends of two adjacent sensing routing lines 21 close to the binding area are electrically connected through the second connecting segment 23. The plurality of first connecting segments 22 and the plurality of second connecting segments 23 are electrically connected to the two adjacent sensing routing lines 21 alternately.

[0123] Figure 4 Schematically shows Figure 2A Enlarged view of area S2 in the middle.

[0124] For example, refer to Figure 4 The temperature sensing coil 20 has 12 sensing lines arranged in sequence along the first direction X, and the first sensing line and the second sensing line, the third sensing line and the fourth sensing line, the fifth sensing line and the sixth sensing line, the seventh sensing line and the eighth sensing line, the ninth sensing line and the tenth sensing line, and the eleventh sensing line and the twelfth sensing line are electrically connected through the first connection section respectively; the second sensing line and the third sensing line, the fourth sensing line and the fifth sensing line, the sixth sensing line and the seventh sensing line, the eighth sensing line and the ninth sensing line, and the tenth sensing line and the eleventh sensing line are electrically connected through the second connection section respectively.

[0125] It should be understood that the number of sensing lines is related to the area of ​​the temperature test region and the pixel arrangement of the array substrate. Here, only 12 sensing lines are used to exemplify the connection method of each sensing line in the temperature sensing coil. The array substrate provided in the embodiment of the present disclosure does not limit the number of sensing lines.

[0126] Continue to refer to Figure 3 The orthographic projections of the plurality of sensing lines 21 on the substrate at least partially overlap with the orthographic projections of the plurality of signal lines SL on the substrate. For example, the orthographic projections of the plurality of sensing lines 21 on the substrate are respectively located within the orthographic projections of the plurality of signal lines SL on the substrate.

[0127] According to some exemplary embodiments, referring to Figure 3 , the orthographic projection of the first connecting segment 22 on the substrate substrate is adjacent to and spaced from the orthographic projection of the scanning line GL on the substrate substrate. That is, the first connecting segment 22 and the scanning line GL do not overlap, so as to avoid the signal in the first connecting segment 22 interfering with the scanning signal transmitted in the scanning line GL. At the same time, the spacing between the orthographic projection of the first connecting segment 22 on the substrate substrate and the orthographic projection of the scanning line GL on the substrate substrate should not be too large, so as to avoid the loss of the aperture ratio.

[0128] According to some exemplary embodiments, referring to Figure 3 , the orthographic projection of the second connecting segment 23 on the substrate substrate is adjacent to and spaced from the orthographic projection of the scanning line GL on the substrate substrate. That is, the second connecting segment 23 and the scanning line GL do not overlap, so as to avoid the signal in the second connecting segment 23 interfering with the scanning signal transmitted in the scanning line GL. At the same time, the spacing between the orthographic projection of the second connecting segment 23 on the substrate substrate and the orthographic projection of the scanning line GL on the substrate substrate should not be too large, so as to avoid the loss of the aperture ratio.

[0129] According to some exemplary embodiments, referring to Figure 3 At least one first dummy routing segment 24 is further arranged between two adjacent sensing routing lines 21. The first dummy routing segment 24 is arranged at intervals from the two adjacent sensing routing lines 21, and the orthographic projection of the first dummy routing segment 24 on the substrate is adjacent to and spaced from the orthographic projection of the scanning line GL on the substrate. The first dummy routing segment 24 is arranged at substantially the same position as the first connecting segment 22 and the second connecting segment 23 in the corresponding sub-pixel. By adding the first dummy routing segment 24 at the same position in the sub-pixel where the first connecting segment 22 and the second connecting segment 23 are not arranged, the wiring in different sub-pixels is kept consistent, thereby improving the display uniformity.

[0130] For example, in the area where the temperature sensing coil is disposed, a first dummy wiring segment 24 is additionally disposed in all sub-pixels that are not provided with the first connecting segment 22 and the second connecting segment 23 .

[0131] According to some exemplary embodiments, the distance between the orthographic projection of the first dummy routing segment 24 on the substrate and the orthographic projection of the nearest scan line GL on the substrate is substantially equal to the distance between the orthographic projection of the first connecting segment 22 on the substrate and the orthographic projection of the nearest scan line GL on the substrate.

[0132] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate substrate close to the binding area, and the orthographic projection of the first connecting segment 22 on the substrate substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate substrate close to the binding area.

[0133] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate substrate is located on a side where the orthographic projection of the nearest scan line GL on the substrate substrate is away from the binding area, and the orthographic projection of the first connecting segment 22 on the substrate substrate is located on a side where the orthographic projection of the nearest scan line GL on the substrate substrate is away from the binding area.

[0134] According to some exemplary embodiments, the distance between the orthographic projection of the first dummy routing segment 24 on the substrate and the orthographic projection of the nearest scan line GL on the substrate is substantially equal to the distance between the orthographic projection of the second connecting segment 23 on the substrate and the orthographic projection of the nearest scan line GL on the substrate.

[0135] According to some exemplary embodiments, the orthographic projection of the first virtual routing segment 24 on the substrate substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate substrate close to the binding area, and the orthographic projection of the second connecting segment 23 on the substrate substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate substrate close to the binding area.

[0136] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate substrate is located on a side where the orthographic projection of the nearest scan line GL on the substrate substrate is away from the binding area, and the orthographic projection of the second connecting segment 23 on the substrate substrate is located on a side where the orthographic projection of the nearest scan line GL on the substrate substrate is away from the binding area.

[0137] According to some exemplary embodiments, in combination with reference Figure 2A With reference Figure 4 , among the two temperature sensing coils 20 adjacent to each other in the second direction Y, at least a portion of the signal transmission portion 30 electrically connected to the temperature sensing coil 20 further away from the binding area BA is located in the temperature test area TA where the temperature sensing coil 20 closer to the binding area BA is located. Figure 4Among the three temperature sensing coils 20 schematically shown in the figure, a part of the signal transmission part 30 electrically connected to the uppermost temperature sensing coil 20 is arranged in the two temperature test areas TA where the middle and lowermost temperature sensing coils 20 are located, and a part of the signal transmission part 30 electrically connected to the middle temperature sensing coil 20 is arranged in the temperature test area TA where the lowermost temperature sensing coil 20 is located. Therefore, part of the space in part of the temperature test area TA will be occupied by the signal transmission part 30, and the area occupied by the signal transmission part 30 is larger in the temperature test area TA closer to the binding area BA. In order to ensure that the resistance values ​​of the temperature sensing coils 20 in different temperature test areas TA are basically equal, it is necessary to set a dummy area TA1 in part of the temperature test area TA, and the temperature sensing coil 20 is arranged in the area other than the dummy area TA1 in the temperature test area TA.

[0138] For example, combined with reference Figure 2A and Figure 4 , Figure 4 The schematic diagram shows three temperature test areas TA arranged along the second direction Y. For a clear description, the temperature test area TA closest to the binding area is indicated as the temperature test area TA located at the bottom, the temperature test area TA farthest from the binding area is indicated as the temperature test area TA located at the top, and the remaining temperature test areas TA are indicated as the temperature test areas TA located in the middle. Figure 4 The temperature test area TA at the bottom and the temperature test area TA at the middle are schematically illustrated, and the temperature test area TA at the bottom is closer to the binding area than the temperature test area TA at the middle. In the two temperature test areas TA adjacent to each other along the second direction Y, the extension length of the temperature sensing coil 20 in one temperature test area TA is substantially equal to the extension length of the temperature sensing coil 20 in the other temperature test area TA, and the areas occupied by the two temperature sensing coils 20 are also substantially equal. However, since the area occupied by the signal transmission part 30 in the temperature test area TA at the bottom is larger, a dummy area TA1 is set in the temperature test area TA at the middle, that is, in the two temperature test areas TA adjacent to each other along the second direction Y (the temperature test area TA at the bottom and the temperature test area TA at the middle), the dummy area TA1 is set only in the temperature test area TA that is farther away from the binding area BA.

[0139] For example, refer to Figure 4 ,by Figure 4The uppermost temperature test area TA and the middle temperature test area TA are schematically illustrated, and the uppermost temperature test area TA is farther away from the binding area than the middle temperature test area TA. In the two temperature test areas TA adjacent to each other along the second direction Y, the extension length of the temperature sensing coil 20 in one temperature test area TA is substantially equal to the extension length of the temperature sensing coil 20 in the other temperature test area TA, and the areas occupied by the two temperature sensing coils 20 are also substantially equal. However, since part of the area of ​​the middle temperature test area TA is occupied by the signal connection part 30, the signal transmission part 30 is not provided in the uppermost temperature test area TA, and therefore, a larger dummy area TA1 needs to be provided in the upper temperature test area TA. That is, in the two temperature test areas TA adjacent to each other along the second direction Y (the uppermost temperature test area TA and the middle temperature test area TA), both temperature test areas TA include a dummy area TA1, and the area of ​​the dummy area TA1 closer to the binding area BA is smaller than the area of ​​the dummy area TA1 farther away from the binding area BA.

[0140] In some embodiments, reference Figure 4 , among the multiple temperature test areas TA adjacent to each other along the second direction Y, the temperature test area TA closest to the binding area is not provided with a dummy area TA1, and the remaining temperature test areas TA are all provided with dummy areas TA1. Moreover, in the temperature test areas TA other than the temperature test area TA closest to the binding area, the area of ​​the dummy area TA1 in the temperature test area TA closer to the binding area is smaller.

[0141] In some embodiments, reference Figure 4 The signal transmission portion 30 is located at one side of the temperature sensing coil 20 along the first direction X, and the dummy area TA1 is located at the other side of the temperature sensing coil 20 along the first direction X.

[0142] Figure 5 Schematically shows Figure 4 Enlarged view of area S3 in the middle.

[0143] According to some exemplary embodiments, in order to ensure the wiring consistency between the area where the temperature sensing coil is set and the dummy area, a dummy routing segment is set in the dummy area. Figure 4 and Figure 5, at least one second dummy routing segment 25 and at least one third dummy routing segment 26 are arranged in the dummy area TA1. The arrangement position of the second dummy routing segment 25 is consistent with the first connecting segment and the second connecting segment, and the orthographic projection of the second dummy routing segment 25 on the substrate is adjacent to and spaced from the orthographic projection of the scanning line GL on the substrate. The arrangement position of the third dummy routing segment 26 is consistent with the sensing routing, and the orthographic projection of the third dummy routing segment 26 on the substrate at least partially overlaps with the orthographic projection of the signal routing line SL on the substrate.

[0144] According to some exemplary embodiments, the lengths of the second dummy routing segment 25 and the third dummy routing segment 26 should not be too long, otherwise there will be a risk of electrostatic shock. For example, the orthographic projection of the second dummy routing segment 25 on the substrate substrate is located between the orthographic projections of two adjacent signal routing lines SL on the substrate substrate, and the orthographic projection of the third dummy routing segment 26 on the substrate substrate is located between the orthographic projections of two adjacent scanning lines GL on the substrate substrate.

[0145] According to some exemplary embodiments, the orthographic projection of the third dummy routing segment on the substrate substrate may be located between the orthographic projections of two non-adjacent scan lines on the substrate substrate, that is, the orthographic projection of the third dummy routing segment on the substrate substrate overlaps with the orthographic projection of at least one scan line on the substrate substrate. The length of the third dummy routing segment along the second direction is set according to actual needs. For example, the length of the third dummy routing segment along the second direction may be substantially equal to the length of the temperature test area along the second direction.

[0146] According to some exemplary embodiments, among the plurality of temperature sensing coils arranged along the second direction, the lengths of the signal transmission parts electrically connected to different temperature sensing coils are different, and thus the resistances of the different signal transmission parts are also different. In order to prevent the resistance differences between different signal transmission parts from affecting the accuracy of temperature detection, a compensation coil is provided in at least a portion of the signal transmission parts for resistance compensation. Figure 2A The plurality of temperature sensing coils 20 arranged along the second direction Y include a distal temperature sensing coil 20A farthest from the binding area BA and at least one proximal temperature sensing coil 20B located on the side of the distal temperature sensing coil 20A close to the binding area BA. The signal transmission unit 30 electrically connected to the proximal temperature sensing coil 20B has a compensation coil located in the peripheral area. The signal transmission unit 30 includes a fan-out trace 34 located in the peripheral area NA. The fan-out trace 34 electrically connects the portion of the signal transmission unit 30 located in the display area AA to the binding area. The compensation coil is arranged in the fan-out trace 34.

[0147] Furthermore, in two adjacent proximal temperature sensing coils 20B along the second direction, the resistance of the compensation coil electrically connected to the proximal temperature sensing coil 20B farther from the binding area BA is smaller than the resistance of the compensation coil electrically connected to the proximal temperature sensing coil 20B closer to the binding area BA. In this way, the resistance of the signal transmission unit 30 electrically connected to each proximal temperature sensing coil 20B after compensation is consistent with the resistance of the signal transmission unit 30 electrically connected to the distal temperature sensing coil 20A.

[0148] Figure 6 Schematically shows Figure 2A Enlarged view of the middle area S10.

[0149] Reference Figure 6 , schematically shows a partial structure of five signal transmission parts 30 located in the peripheral area, and the signal transmission part 30 on the far left is electrically connected to the far-end temperature sensing coil, and thus no compensation coil is provided. The remaining four signal transmission parts 30 are electrically connected to the near-end temperature sensing coils, respectively, and thus all are provided with compensation coils 33. Further, the four signal transmission parts 30 with compensation coils 33 from left to right are electrically connected to the four near-end temperature sensing coils from far to near the binding area, respectively, and the extension length of the compensation coil 33 in the signal transmission part 30 electrically connected to the near-end temperature sensing coil farther from the binding area is shorter than the extension length of the compensation coil 33 in the signal transmission part 30 electrically connected to the near-end temperature sensing coil closer to the binding area, and therefore, the resistance of the compensation coil 33 in the signal transmission part 30 electrically connected to the near-end temperature sensing coil farther from the binding area is shorter than the resistance of the compensation coil 33 in the signal transmission part 30 electrically connected to the near-end temperature sensing coil closer to the binding area.

[0150] According to some exemplary embodiments, referring to Figure 6 The compensation coil 33 includes a first compensation coil 331 and a second compensation coil 332. The first compensation coil 331 is disposed in the first wiring 21, and the second compensation coil 332 is disposed in the second wiring 22. The first compensation coil 331 and the second compensation coil 332 are disposed adjacent to each other along the first direction X. The extension length of the first compensation coil 331 is substantially equal to the extension length of the second compensation coil 332.

[0151] According to some exemplary embodiments, referring to Figure 6 The first compensation coil 331 and the second compensation coil 332 are serpentine structures reciprocatingly wound along the first direction X.

[0152] Figure 7 Schematically shows Figure 4 Enlarged view of area S4 in the middle. Figure 8 The array substrate according to one embodiment of the present disclosure is schematically shown in FIG. Figure 7Enlarged view of area S5 in the middle. Fig. 9 Schematically shows Figure 8 Schematic diagram taken along line AA'. Fig. 10A Schematically shows Figure 8 Schematic diagram taken along line BB'. Fig. 10B Schematically shows Figure 8 Schematic diagram taken along line CC'.

[0153] According to some exemplary embodiments, in combination with reference Fig. 9 , Fig. 10A and Fig. 10B The array substrate also includes a gate metal layer Gate located on the base substrate 10, a gate insulating layer GI located on the side of the gate metal layer Gate away from the base substrate 10, a source-drain metal layer SD located on the side of the gate insulating layer GI away from the base substrate 10, a first passivation layer PV1 located on the side of the source-drain metal layer SD away from the base substrate, a sensing metal layer METAL located on the side of the first passivation layer PV1 away from the base substrate, a second passivation layer PV2 located on the side of the sensing metal layer METAL away from the base substrate, and a common electrode layer COM located on the side of the second passivation layer PV2 away from the base substrate.

[0154] For example, the temperature sensing coil and the signal transmission portion are located in the sensing metal layer METAL.

[0155] For example, the first dummy routing segment, the second dummy routing segment, and the third dummy routing segment are located in the sensing metal layer METAL.

[0156] According to some exemplary embodiments, referring to Fig. 9 , the common electrode layer COM includes a common electrode 50, and the orthographic projection of the common electrode 50 on the base substrate 10 covers at least a part of the orthographic projection of the temperature sensing coil 20 on the base substrate 10. For example, the orthographic projection of the common electrode 50 on the base substrate 10 covers the orthographic projection of the temperature sensing trace on the base substrate 10. In the display panel manufactured by the array substrate provided by the embodiment of the present disclosure, the array substrate also has a liquid crystal layer and a color filter substrate, and here, the common electrode 50 can be used as a shielding structure of the temperature sensing coil 20 to prevent the signal in the temperature sensing coil 20 from interfering with the electric field driving the deflection of the liquid crystal molecules, thereby effectively avoiding the occurrence of light leakage caused by abnormal deflection of the liquid crystal molecules.

[0157] According to some exemplary embodiments, referring to Figure 1A , Figure 1B and Figure 8, shows a dual scan line drive type array substrate, the plurality of signal lines SL include a plurality of data lines DL and a plurality of common electrode lines CL, for example, the plurality of data lines DL and the plurality of common electrode lines CL are alternately arranged along a first direction X. And both the plurality of data lines DL and the plurality of common electrode lines CL cross the plurality of scan lines GL, respectively, to define a plurality of sub-pixels P.

[0158] For example, a scan line group is arranged between two adjacent sub-pixels in the second direction Y, and the scan line group includes two scan lines GL, which can be represented by a first scan line GL1 and a second scan line GL2, respectively. A first sub-pixel P1 and a second sub-pixel P2 adjacent to each other in the first direction X can form a sub-pixel group, and a data line DL is arranged between two adjacent sub-pixel groups in the first direction X. A common electrode line CL is arranged between two sub-pixels P1 and P2 in the sub-pixel group.

[0159] Reference Figure 1A and or Figure 1B In the sub-pixels of the same row, the thin film transistors of the sub-pixels in odd columns are connected to the same scan line, such as the first scan line GL1, and the thin film transistors of the sub-pixels in even columns are connected to the same scan line, such as the second scan line GL2. In two adjacent columns of sub-pixels, the thin film transistors of the sub-pixels in the adjacent two columns can be connected to the same data line DL. For example, referring to Figure 1A , the data lines DL connected to the thin film transistors of two adjacent columns of sub-pixels are located on the same side of the two columns of sub-pixels along the first direction X. Or, referring to Figure 1B The data line DL connected to the thin film transistors of two adjacent columns of sub-pixels is located between the two columns of sub-pixels. Figure 8 The connection method between the data lines and the sub-pixels in the array substrate shown is Figure 1B The connection method shown in the figure.

[0160] When the dual scan line driven array substrate is working, valid signals can be input row by row on the first scan line GL1 and the second scan line GL2 to turn on the corresponding thin film transistors. Specifically, when the thin film transistors in the odd columns of a row are turned on, the pixel voltage is input to the thin film transistors in the odd columns through the data line DL, and the pixel voltage is transmitted to the pixel electrode to display the corresponding gray scale. When the thin film transistors in the even columns of a row are turned on, the pixel voltage is input to the thin film transistors in the even columns through the data line DL, and the pixel voltage is transmitted to the pixel electrode to display the corresponding gray scale. In the dual scan line driving mode, the number of scan lines is doubled and the number of data lines is reduced by half, which can reduce the cost of the driver IC; at the same time, the charging time is also reduced to half of that in the single scan line driving mode, and the charging efficiency needs to be improved.

[0161] According to some exemplary embodiments, referring to Figure 8 and Fig. 9 The orthographic projection of the sensing line 21 on the substrate at least partially overlaps with the orthographic projection of the common electrode line CL on the substrate. The orthographic projection of the sensing line 21 on the substrate is spaced from the orthographic projection of the data line DL on the substrate.

[0162] According to some exemplary embodiments, referring to Figure 8 and Fig. 9 , the array substrate further includes a pixel electrode layer PIX located between the gate insulating layer GI and the first passivation layer PV1, the pixel electrode layer PIX includes a plurality of pixel electrodes 60, and the orthographic projection of the scan line group on the substrate substrate is located between the orthographic projections of two pixel electrodes 60 adjacent along the second direction Y on the substrate substrate. Among them, at least a portion of the orthographic projection of the first connecting segment 22 on the substrate substrate is located between the orthographic projections of two scan lines GL in the scan line group on the substrate substrate, for example, the entire orthographic projection of the first connecting segment 22 on the substrate substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate substrate. Similarly, at least a portion of the orthographic projection of the second connecting segment 23 on the substrate substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate substrate, for example, the entire orthographic projection of the second connecting segment 23 on the substrate substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate substrate.

[0163] According to some exemplary embodiments, referring to Fig. 10A and Fig. 10B , the common electrode line CL is located in the source-drain metal layer SD, the array substrate further includes a first passivation layer PV1 located between the source-drain metal layer SD and the sensing metal layer METAL, and a second passivation layer PV2 located between the sensing metal layer METAL and the common electrode layer COM, the first passivation layer PV1 and the second passivation layer PV2 have via holes V1, the via holes V1 expose a portion of the common electrode line CL, the common electrode layer COM includes a common electrode 50, and the common electrode 50 is electrically connected to the common electrode line CL through the via holes V1. Figure 8 The sensing line 21 includes a plurality of sensing segments 211 arranged along the second direction Y. The orthographic projection of the sensing segment 211 on the substrate is located between the orthographic projections of two adjacent scanning line groups on the substrate. Two adjacent sensing segments 211 are electrically connected via a connecting portion 212. The orthographic projection of the connecting portion 212 on the substrate is spaced from the orthographic projection of the via hole V1 on the substrate, that is, the connecting portion 212 is arranged to avoid the via hole V1.

[0164] According to some exemplary embodiments, referring to Figure 8, the connecting portion 212 is annular, and the orthographic projection of the via hole V1 on the base substrate is located within the orthographic projection of the connecting portion 212 on the base substrate. For example, the connecting portion 212 is annular.

[0165] Fig.11 The array substrate according to one embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of middle area S6.

[0166] According to some exemplary embodiments, referring to Fig.11 At least one first dummy routing segment 24 is further arranged between two adjacent sensing routing lines 21. The first dummy routing segment 24 is arranged at intervals from the two adjacent sensing routing lines 21, and the orthographic projection of the first dummy routing segment 24 on the substrate is located between the orthographic projections of the two scanning lines GL in the scanning line group on the substrate.

[0167] Fig.12 The array substrate according to one embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of middle area S7.

[0168] According to some exemplary embodiments, referring to Fig.12 In order to ensure the wiring consistency between the area where the temperature sensing coil is provided and the dummy area, at least one second dummy routing segment 25 and at least one third dummy routing segment 26 are provided in the dummy area TA1. At least part of the orthographic projection of the second dummy routing segment 25 on the substrate is located between the orthographic projections of the two scanning lines GL in the scanning line group on the substrate. For example, the orthographic projections of the second dummy routing segment 25 on the substrate are all located between the orthographic projections of the two scanning lines GL in the scanning line group on the substrate, and the orthographic projection of the third dummy routing segment 26 on the substrate at least partially overlaps with the orthographic projection of the common electrode line CL on the substrate.

[0169] According to some exemplary embodiments, the lengths of the second dummy routing segment 25 and the third dummy routing segment 26 should not be too long, otherwise there will be a risk of electrostatic shock. Therefore, the orthographic projection of the second dummy routing segment 25 on the substrate is located between the orthographic projections of two adjacent common electrode lines CL on the substrate, and the orthographic projection of the third dummy routing segment 26 on the substrate is located between the orthographic projections of two adjacent scanning line groups on the substrate.

[0170] According to some exemplary embodiments, in combination with reference Figure 2A The first wiring 31 includes a first wiring segment 311 located in the display area AA, one end of the first wiring segment 311 is electrically connected to the input end of the temperature sensing coil 20 and extends along the second direction Y toward the binding area BA.

[0171] The second routing line 32 includes a second routing segment 321 and a third routing segment 322 located in the display area AA, one end of the second routing segment 321 is electrically connected to the output end of the temperature sensing coil 20 and extends along the first direction X towards the direction close to the first routing segment 311, and one end of the third routing segment 322 is electrically connected to the second routing segment 321 and extends along the second direction Y towards the direction close to the binding area BA.

[0172] Figure 2D The plan views of array substrates according to some further embodiments of the present disclosure are schematically shown.

[0173] According to some exemplary embodiments, referring to Figure 2D The first wiring 31 includes a first wiring segment 311 located in the display area AA, one end of the first wiring segment 311 is electrically connected to the input end of the temperature sensing coil 20 and extends along the second direction Y toward the binding area BA.

[0174] The second routing line 32 includes a second routing line segment 321 and a third routing line segment 322 located in the display area AA, one end of the second routing line segment 321 is electrically connected to the output end of the temperature sensing coil 20 and extends in the first direction X in a direction away from the first routing line segment 311, and one end of the third routing line segment 322 is electrically connected to the second routing line segment 321 and extends in the second direction Y in a direction close to the binding area BA. That is, the first routing line 31 and the second routing line 32 are electrically connected to the two ends of the temperature sensing coil 20 along the first direction respectively, and the first routing line segment 311 and the third routing line segment 322 electrically connected to the temperature sensing coil 20 farther away from the binding area BA are located on both sides of the temperature sensing coil 20 closer to the binding area BA along the first direction X. According to this configuration, the length of the second routing line segment 321 in the second routing line 32 can be shortened, that is, the resistance of the second routing line 32 can be reduced. For example, in the second routing line 32 electrically connected to the temperature sensing coil 20 closest to the binding area BA, the portion of the second routing line 32 located in the display area AA may include only a third routing segment 322, that is, one end of the third routing segment 322 is electrically connected to the output end of the temperature sensing coil 20 and extends along the second direction Y to the peripheral area NA.

[0175] Fig.13A The array substrate according to another embodiment of the present disclosure is schematically shown in FIG. Figure 7 Enlarged view of the middle area S8. Fig. 13B Schematically Figure 7 Magnified view of middle area S9.

[0176] According to some exemplary embodiments, referring to Fig.13A On the side of the sensing coil away from the binding area, two adjacent sensing wires 21 are electrically connected through a first connecting segment 22. A first dummy wire segment 24 is also provided between the two adjacent sensing wires 21.

[0177] According to some exemplary embodiments, referring to Figure 7 and Fig. 13B On the side of the sensing coil close to the binding area, two adjacent sensing wires 21 are electrically connected via a second connecting segment 23. A first dummy wire segment 24 is also provided between the two adjacent sensing wires 21. Fig. 13B A portion of the second routing segment 321 is also illustrated, and at least a portion of the orthographic projection of the second routing segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate. For example, at least a portion of the orthographic projection of the second routing segment on the substrate is located between the orthographic projections of two scan lines in the scan line group on the substrate.

[0178] Fig.14 Schematically Figure 7 Enlarged view of the middle area S11.

[0179] According to some exemplary embodiments, referring to Fig.14 The first routing segment 311 includes at least two first routing sub-segments 3111, and the two first routing sub-segments 3111 are electrically connected through at least one third connecting segment 3112. The third routing segment 322 includes at least two third routing sub-segments 3221, and the two third routing sub-segments 3221 are electrically connected through at least one fourth connecting segment 3222. This configuration can reduce the resistance of the first routing segment and the third routing segment, thereby improving the accuracy of temperature detection.

[0180] According to some exemplary embodiments, the orthographic projections of the two first routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate substrate, for example, the orthographic projections of the two first routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent common electrode lines on the substrate substrate. The orthographic projections of the two third routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate substrate, for example, the orthographic projections of the two third routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent common electrode lines on the substrate substrate.

[0181] According to some exemplary embodiments, at least a portion of the orthographic projection of the third connecting segment on the substrate substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate substrate. For example, at least a portion of the orthographic projection of the third connecting segment on the substrate substrate is located between the orthographic projections of two scan lines in the scan line group on the substrate substrate. At least a portion of the orthographic projection of the fourth connecting segment on the substrate substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate substrate. For example, at least a portion of the orthographic projection of the fourth connecting segment on the substrate substrate is located between the orthographic projections of two scan lines in the scan line group on the substrate substrate.

[0182] According to some exemplary embodiments, the orthographic projections of the two first routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate substrate, respectively, and at least a portion of the orthographic projection of the third connecting segment on the substrate substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate substrate.

[0183] According to some exemplary embodiments, the orthographic projections of the two third routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate substrate, and the orthographic projection of the fourth connecting segment on the substrate substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate substrate.

[0184] Fig.15 Schematically illustrates a pixel arrangement plan view of an array substrate according to some other embodiments of the present disclosure. Fig.16 The array substrate according to another embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of area S5 in the middle. Fig.17 The array substrate according to another embodiment of the present disclosure is schematically shown in FIG. Figure 7 Magnified view of area S5 in the middle.

[0185] According to some exemplary embodiments, referring to Fig.15 , Fig.16 and Fig.17 The array substrate is a single scan line driven array substrate, and the plurality of signal lines SL include a plurality of data lines DL. For example, the plurality of data lines DL and the plurality of scan lines GL respectively cross to define a plurality of sub-pixels P.

[0186] According to some exemplary embodiments, referring to Fig.16 , the orthographic projection of the sensing line 21 on the substrate at least partially overlaps with the orthographic projection of the data line DL on the substrate. The side of the adjacent sensing lines 21 away from the binding area is electrically connected through the first connecting segment 22, and the orthographic projection of the first connecting segment 22 on the substrate is adjacent to and spaced from the orthographic projection of the scanning line GL on the substrate. Similarly, the side of the adjacent sensing lines close to the binding area is electrically connected through the second connecting segment, and the orthographic projection of the second connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate.

[0187] According to some exemplary embodiments, referring to Fig.17 , the orthographic projection of the sensing trace 21 on the substrate at least partially overlaps with the orthographic projection of the data line DL on the substrate.

[0188] According to some exemplary embodiments, referring to Fig.17, the pixel electrode 60 includes a first electrode portion 61 and a second electrode portion 62 connected along a second direction Y, the first electrode portion 61 extends along a third direction, the second electrode portion 62 extends along a fourth direction, and the third direction intersects with the fourth direction. That is, the sub-pixel is a dual-domain structure, and the boundary between the two domains is a dark area. Therefore, the first connecting segment and the second connecting segment can be set in this area. Specifically, the side of the adjacent sensing wiring 21 away from the binding area is electrically connected through the first connecting segment 22, and the orthographic projection of the edge connected to the first electrode portion 61 and the second electrode portion 62 on the substrate substrate is located within the orthographic projection of the first connecting segment 22 on the substrate substrate. Similarly, the orthographic projection of the edge connected to the first electrode portion and the second electrode portion on the substrate substrate can be located within the orthographic projection of the second connecting segment on the substrate substrate.

[0189] According to some exemplary embodiments, Fig.17 On the basis of the structure of the illustrated array substrate, a first dummy trace can be provided in the temperature sensing coil, and the first dummy trace is provided in substantially the same manner as the first connecting section and the second connecting section, so as to ensure the wiring uniformity in the temperature test area. That is, in the temperature sensing coil, at least one first dummy trace segment is provided between two adjacent sensing traces, and the orthographic projection of the first dummy trace segment on the base substrate covers the edge where the first electrode portion is connected to the second electrode portion.

[0190] Fig.18 The diagram schematically shows a distribution diagram of a temperature test area in a display area of ​​an array substrate according to some embodiments of the present disclosure.

[0191] According to some exemplary embodiments, the display area is irregular in shape, and at least one temperature test area in the display area is irregular in shape. Fig.18 , the upper edge of the display area is a curved edge. The temperature test area TA located at the lower side is in the shape of a rectangle, and the temperature test area TA located at the uppermost side is an asymmetric temperature test area TAA. Of the two sides of the asymmetric temperature test area TAA located on both sides of the second direction Y, the extension direction of one side is parallel to the first direction X, and the extension direction of the other side intersects with the first direction X or the other side is a curved side.

[0192] Fig.19 The diagram schematically shows the distribution of temperature sensing coils in a special-shaped temperature test area of ​​an array substrate according to some embodiments of the present disclosure.

[0193] According to some exemplary embodiments, referring to Fig.19The special-shaped temperature test area TAA includes a test area TAA1, the test area TAA1 is rectangular, the temperature sensing coil 20 is located in the test area, and the lengths of the sensing traces 21 along the second direction Y are substantially equal. A dummy trace segment can be set in the area other than the test area TAA1 in the special-shaped temperature test area TAA to ensure wiring consistency.

[0194] Fig. 20 The distribution diagram of the temperature sensing coils in the special-shaped temperature test area of ​​the array substrate according to some other embodiments of the present disclosure is schematically shown.

[0195] According to some exemplary embodiments, referring to Fig. 20 The sensing coil is located in the special-shaped temperature test area TAA, and the lengths of at least two sensing lines 21 along the second direction Y are different from each other. That is, the contour shape of the sensing line 21 is consistent with the special-shaped temperature test area TAA.

[0196] According to some exemplary embodiments, referring to Figure 2A The array substrate also includes at least one peripheral temperature sensing coil 20N located in the peripheral area NA. The input end of the peripheral temperature sensing coil 20N is electrically connected to the binding area BA through an input wiring. The input wiring is used to connect the driving signal provided by the binding area BA to the peripheral temperature sensing coil 20N. The output end of the peripheral temperature sensing coil 20N is electrically connected to the binding area BA through an output wiring. The output wiring is used to transmit the sensing signal generated by the peripheral temperature sensing coil 20N to the binding area BA.

[0197] Fig.21 The planar area of ​​the peripheral temperature sensing coil of the array substrate according to some embodiments of the present disclosure is schematically shown.

[0198] According to some exemplary embodiments, referring to Fig.21 The peripheral temperature sensing coil 20N includes a first portion 20N1 and a second portion 20N2 adjacent to each other along a first direction, and the first portion 20N1 and the second portion 20N2 are electrically connected. The first portion 20N1 has a serpentine structure reciprocatingly wound along the first direction X, and the second portion 20N2 has a serpentine structure reciprocatingly wound along the first direction X.

[0199] In some embodiments, the structure of the peripheral temperature sensing coil located in the peripheral area can be consistent with the structure of the temperature sensing coil located in the display area, so that the resistance of the peripheral temperature sensing coil is basically equal to the resistance of the temperature sensing coil, so that the same processing procedure can be used to obtain corresponding temperature information according to the sensing signal output by the peripheral temperature sensing coil and the sensing signal output by the temperature sensing coil, that is, the processing complexity of calculating the corresponding temperature information according to the sensing signal is reduced. Fig. 22A schematic diagram of a display panel according to an embodiment of the present disclosure is schematically shown.

[0200] The display panel may include an array substrate 1 and an opposite substrate 2 disposed opposite to the array substrate 1. The display panel may further include a liquid crystal layer 3 located between the array substrate 1 and the opposite substrate 2. The array substrate 1 may be the above-mentioned array substrate, that is, a temperature sensing coil is disposed in the array substrate.

[0201] For example, the counter substrate 2 may be a color filter substrate. Specifically, it may include a black matrix BM, and the orthographic projection of the black matrix BM on the base substrate 10 covers at least a portion of the orthographic projection of the temperature sensing coil 20 on the base substrate 10. Exemplarily, the orthographic projection of the black matrix BM on the base substrate 10 covers the orthographic projection of the sensing trace 21 on the base substrate 10.

[0202] According to an embodiment of the present disclosure, a display device is also provided, which may include the display panel as described above. For example, the display device may be any product or component with a display function, such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a car display, an e-book, or the like.

[0203] According to an embodiment of the present disclosure, a head-up display system is also provided, which includes a display panel as described above and an optical path magnifying element. For example, the head-up display system can be used in a car, and the display panel is used to generate graphics and control brightness. The optical path magnifying element is used to magnify the display image and eliminate the distortion caused by the car windshield. Since the virtual image of the display panel is reflected from the windshield, it can bring a visual experience that the image is suspended outside the windshield, presenting a holographic image effect. According to some exemplary embodiments, the optical path magnifying element may include a concave mirror.

[0204] Fig.23 The flowchart of the temperature measurement method of the display panel according to the embodiment of the present disclosure is schematically shown.

[0205] According to an embodiment of the present disclosure, a temperature measurement method for the display panel as above is also provided, referring to Fig.23 , the temperature measurement method includes the following steps:

[0206] In step S10, a driving signal is input to an input terminal of the temperature sensing coil.

[0207] In step S20, a sensing signal outputted from the output end of the temperature sensing coil is obtained.

[0208] In step S30, the temperature of the temperature test area where the temperature sensing coil is located is obtained according to the sensing signal.

[0209] According to some exemplary embodiments, before the display panel is officially used, the display panel is placed in an environment with different temperatures, and a driving signal is input to the input end of the temperature sensing coil in the display panel, sensing signals corresponding to different temperatures are measured, and a standard temperature curve is generated. Obtaining the temperature of the temperature test area where the temperature sensing coil is located according to the sensing signal includes obtaining the temperature of the temperature test area where the temperature sensing coil is located according to the standard temperature curve and the sensing signal.

[0210] Fig.24 The figure schematically shows a timing diagram of a driving signal in a temperature measurement method of a display panel according to an embodiment of the present disclosure. Fig.25 A timing diagram of a driving signal in another temperature measurement method of a display panel according to an embodiment of the present disclosure is schematically shown.

[0211] According to some exemplary embodiments, referring to Fig.25 , inputting a driving signal to the input end of the temperature sensing coil includes: when the display panel is in the display stage t1, the data signal Source switches between a high level signal and a low level signal, at this time, inputting a first driving signal DS1 to the input end of the temperature sensing coil, the first driving signal DS1 is a common electrode voltage signal, when the display panel is in the non-display stage t2, the data signal Source is a low level signal, at this time, inputting a second driving signal DS2 to the input end of the temperature sensing coil, the voltage value of the second driving signal DS2 is greater than the voltage value of the first driving signal DS1; obtaining a sensing signal output from the output end of the temperature sensing coil includes: when the display panel is in the non-display stage t2, obtaining a sensing signal output by the temperature sensing coil in response to the second driving signal DS2. In this temperature measurement method, since a common electrode voltage signal with a lower voltage value is connected to the temperature sensing coil in the display stage t1, it can effectively prevent the voltage signal of the temperature sensing coil from affecting other display signals in the display panel and causing poor display.

[0212] According to some exemplary embodiments, referring to Fig.24 , inputting a driving signal to the input end of the temperature sensing coil includes: inputting a second driving signal DS2 to the input end of the temperature sensing coil regardless of whether the display panel is in the display stage t1 or the non-display stage t2; obtaining a sensing signal output from the output end of the temperature sensing coil includes: obtaining a sensing signal output by the temperature sensing coil in response to the second driving signal DS2 when temperature data needs to be obtained. For example, the sensing signal output by the temperature sensing coil in response to the second driving signal DS2 can be obtained in the display stage t1, and the sensing signal output by the temperature sensing coil in response to the second driving signal DS2 can also be obtained in the non-display stage t2.

[0213] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate, and these features and advantages can be referred to the above description of the display substrate, which will not be repeated here.

[0214] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0215] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, characterized in that: The array substrate includes a display area and a peripheral area located around the display area, a plurality of temperature test areas are arranged in the display area, and the plurality of temperature test areas are arranged along a first direction and / or a second direction, a binding area is arranged in the peripheral area, and the binding area is located on one side of the display area along the second direction, and the array substrate includes: substrate substrate; a plurality of temperature sensing coils located on the substrate, the plurality of temperature sensing coils being located in the plurality of temperature testing regions respectively; and A plurality of signal transmission parts located on the substrate, the plurality of signal transmission parts are electrically connected to the plurality of temperature sensing coils respectively, the signal transmission parts include a first routing line and a second routing line, one end of the first routing line is electrically connected to the input end of the temperature sensing coil, the other end of the first routing line extends to the binding area, one end of the second routing line is electrically connected to the output end of the temperature sensing coil, the other end of the second routing line extends to the binding area; Among them, the array substrate also includes a plurality of signal lines located on the array substrate, the plurality of signal lines are arranged along the first direction and extend along the second direction, and the orthographic projection of the temperature sensing coil on the base substrate at least partially overlaps with the orthographic projection of the signal lines on the base substrate.

2. The array substrate according to claim 1, characterized in that: The display area includes a plurality of sub-pixel opening areas and a non-opening area located between adjacent sub-pixel opening areas, and the sub-pixel opening area includes a light-transmitting area and a non-light-transmitting area; Wherein, at least a portion of the temperature sensing coil is located in the non-opening area, and / or at least a portion of the temperature sensing coil is located in the non-light-transmitting area.

3. The array substrate according to claim 1 or 2, characterized in that: The temperature sensing coil includes a plurality of sensing traces, a plurality of first connecting segments, and a plurality of second connecting segments, wherein the plurality of sensing traces are arranged along the first direction and extend along the second direction; One end of two adjacent sensing lines away from the binding area is electrically connected through the first connection segment, and one end of two adjacent sensing lines close to the binding area is electrically connected through the second connection segment, and the plurality of first connection segments and the plurality of second connection segments are alternately electrically connected to the two adjacent sensing lines; as well as The orthographic projections of the plurality of sensing lines on the substrate at least partially overlap with the orthographic projections of the plurality of signal lines on the substrate.

4. The array substrate according to claim 3, characterized in that: The array substrate comprises a plurality of scan lines located on the base substrate, the plurality of scan lines are arranged along the second direction and extend along the first direction; The orthographic projection of the first connecting section on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate; and / or The orthographic projection of the second connecting segment on the base substrate is adjacent to and spaced from the orthographic projection of the scanning line on the base substrate.

5. The array substrate according to claim 4, characterized in that: At least one first dummy routing segment is also arranged between two adjacent sensing routing lines, and the first dummy routing segment is spaced apart from the two adjacent sensing routing lines, and the orthographic projection of the first dummy routing segment on the substrate is adjacent to and spaced apart from the orthographic projection of the scanning line on the substrate.

6. The array substrate according to claim 4 or 5, characterized in that: In two of the temperature sensing coils adjacent to each other along the second direction, at least a portion of the signal transmission portion electrically connected to the temperature sensing coil further away from the binding area is located in the temperature testing area where the temperature sensing coil closer to the binding area is located; In two temperature test areas adjacent to each other along the second direction, both temperature test areas include a dummy area, the temperature sensing coil is located in an area of ​​the temperature test area other than the dummy area, an extension length of the temperature sensing coil in one temperature test area is substantially equal to an extension length of the temperature sensing coil in the other temperature test area, and an area of ​​the dummy area closer to the binding area is smaller than an area of ​​the dummy area farther from the binding area; or Among two temperature testing areas adjacent to each other along the second direction, only the temperature testing area farther away from the binding area includes a dummy area, the temperature sensing coil is located in an area other than the dummy area in the temperature testing area, and an extension length of the temperature sensing coil in one of the temperature testing areas is substantially equal to an extension length of the temperature sensing coil in the other of the temperature testing areas.

7. The array substrate according to claim 6, characterized in that: At least one second dummy routing segment and at least one third dummy routing segment are arranged in the dummy area; The orthographic projection of the second dummy routing segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate, and the orthographic projection of the second dummy routing segment on the substrate is located between the orthographic projections of the two signal routing lines on the substrate; The orthographic projection of the third dummy routing segment on the substrate at least partially overlaps with the orthographic projection of the signal routing segment on the substrate, and the orthographic projection of the third dummy routing segment on the substrate is located between the orthographic projections of the two scanning lines on the substrate.

8. The array substrate according to any one of claims 1, 2, 4, 5 and 7, characterized in that: The plurality of temperature sensing coils arranged along the second direction include a distal temperature sensing coil farthest from the binding area and at least one proximal temperature sensing coil located on a side of the distal temperature sensing coil close to the binding area; In which, the signal transmission part electrically connected to the proximal temperature sensing coil has a compensation coil located in the peripheral area, and among the two proximal temperature sensing coils adjacent to each other along the second direction, the resistance of the compensation coil electrically connected to the proximal temperature sensing coil farther away from the binding area is smaller than the resistance of the compensation coil electrically connected to the proximal temperature sensing coil closer to the binding area.

9. The array substrate according to any one of claims 4, 5 and 7, characterized in that: The array substrate also includes a gate metal layer located on the base substrate, a source-drain metal layer located on a side of the gate metal layer away from the base substrate, a common electrode layer located on a side of the source-drain metal layer away from the base substrate, and a sensing metal layer located between the source-drain metal layer and the common electrode layer, and the temperature sensing coil and the signal transmission unit are located in the sensing metal layer.

10. The array substrate according to claim 9, characterized in that: The common electrode layer includes a common electrode, and an orthographic projection of the common electrode on the base substrate covers at least a portion of an orthographic projection of the temperature sensing coil on the base substrate.

11. The array substrate according to claim 9, characterized in that: The plurality of signal lines include a plurality of data lines and a plurality of common electrode lines, and the plurality of data lines and the plurality of common electrode lines are alternately arranged along the first direction; The orthographic projection of the sensing trace on the base substrate at least partially overlaps with the orthographic projection of the common electrode line on the base substrate.

12. The array substrate according to claim 11, characterized in that: The array substrate further comprises a pixel electrode layer located on the base substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes; and The plurality of scan lines include a plurality of scan line groups, the scan line group includes two scan lines, and the orthographic projection of the scan line group on the base substrate is located between the orthographic projections of two adjacent pixel electrodes along the second direction on the base substrate; Wherein, at least a part of the orthographic projection of the first connecting segment on the substrate is located between the orthographic projections of two scanning lines in the scanning line group on the substrate; and / or At least a portion of the orthographic projection of the second connecting segment on the substrate is located between the orthographic projections of two scanning lines in the scanning line group on the substrate.

13. The array substrate according to claim 11 or 12, characterized in that: The common electrode line is located in the source-drain metal layer, the array substrate includes a first passivation layer located between the source-drain metal layer and the sensing metal layer, and a second passivation layer located between the sensing metal layer and the common electrode layer, the first passivation layer and the second passivation layer have via holes, the via holes expose a portion of the common electrode line, the common electrode layer includes a common electrode, and the common electrode is electrically connected to the common electrode line through the via holes; The sensing trace includes a plurality of sensing segments arranged along the second direction, two adjacent sensing segments are electrically connected via a connecting portion, and an orthographic projection of the connecting portion on the base substrate is spaced apart from an orthographic projection of the via hole on the base substrate.

14. The array substrate according to claim 13, characterized in that: The connecting portion is ring-shaped, and the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the connecting portion on the base substrate.

15. The array substrate according to claim 9, characterized in that: The plurality of signal lines include a plurality of data lines, and an orthographic projection of the sensing line on the substrate at least partially overlaps with an orthographic projection of the data line on the substrate.

16. The array substrate according to claim 3, characterized in that: The array substrate further comprises a pixel electrode layer located on the base substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes; and The pixel electrode comprises a first electrode portion and a second electrode portion connected along the second direction, the first electrode portion extends along a third direction, the second electrode portion extends along a fourth direction, and the third direction intersects the fourth direction; The orthographic projection of the edge where the first electrode portion and the second electrode portion are connected on the base substrate is located within the orthographic projection of the first connecting section on the base substrate; and / or An orthographic projection of an edge of the first electrode portion connected to the second electrode portion on the base substrate is located within an orthographic projection of the second connecting segment on the base substrate.

17. The array substrate according to any one of claims 4, 5, 7, 10-12, 14 and 15, characterized in that: The first wiring includes a first wiring segment located in the display area, one end of the first wiring segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and The second routing includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction toward the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

18. The array substrate according to any one of claims 4, 5, 7, 10-12, 14 and 15, characterized in that: The first wiring includes a first wiring segment located in the display area, one end of the first wiring segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and The second routing includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction away from the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

19. The array substrate according to claim 17, characterized in that: The first routing segment includes at least two first routing sub-segments, the two first routing sub-segments are electrically connected via at least one third connecting segment, the orthographic projections of the two first routing sub-segments on the substrate respectively overlap at least partially with the orthographic projections of two adjacent signal routing lines on the substrate, and the orthographic projection of the third connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate; and / or The third routing segment includes at least two third routing sub-segments, the two third routing sub-segments are electrically connected through at least one fourth connecting segment, the orthographic projections of the two third routing sub-segments on the substrate respectively overlap at least partially with the orthographic projections of two adjacent signal routing lines on the substrate, and the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

20. The array substrate according to claim 18, characterized in that: The first routing segment includes at least two first routing sub-segments, the two first routing sub-segments are electrically connected via at least one third connecting segment, the orthographic projections of the two first routing sub-segments on the substrate respectively overlap at least partially with the orthographic projections of two adjacent signal routing lines on the substrate, and the orthographic projection of the third connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate; and / or The third routing segment includes at least two third routing sub-segments, the two third routing sub-segments are electrically connected through at least one fourth connecting segment, the orthographic projections of the two third routing sub-segments on the substrate respectively overlap at least partially with the orthographic projections of two adjacent signal routing lines on the substrate, and the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

21. The array substrate according to any one of claims 4, 5, 7, 10-12, 14, 15, 16, 19 and 20, characterized in that: The multiple temperature test areas include at least one special-shaped temperature test area, and of the two sides of the special-shaped temperature test area located on both sides of the second direction, one side extends in a direction parallel to the first direction, and the other side extends in a direction intersecting with the first direction or the other side is a curved side; Wherein, the special-shaped temperature test area includes a test area, the shape of the test area is rectangular, the temperature sensing coil is located in the test area, and the lengths of the sensing lines along the second direction are substantially equal; or The sensing coil is located in the special-shaped temperature test area, and the lengths of at least two sensing lines along the second direction are different from each other.

22. The array substrate according to any one of claims 1, 2, 4, 5, 7, 10, 11, 12, 14, 15, 16, 19 and 20, characterized in that: The array substrate also includes at least one peripheral temperature sensing coil located in the peripheral area, the input end of the peripheral temperature sensing coil is electrically connected to the input terminal in the binding area through an input trace, and the input trace is used to connect the driving signal provided by the input terminal to the peripheral temperature sensing coil, and the output end of the peripheral temperature sensing coil is electrically connected to the output terminal in the binding area through an output trace, and the output trace is used to transmit the sensing signal generated by the peripheral temperature sensing coil to the output terminal.

23. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1-22.

24. A display device, characterized in that: The display device comprises the display panel according to claim 23.

25. A head-up display system, characterized in that: The head-up display system comprises the display panel according to claim 23 and an optical path amplifying element.

26. The head-up display system according to claim 25, characterized in that: The optical path magnifying element includes a concave mirror.

Images