Communication control circuit and display device

Abstract

According to the communication control circuit and the display device provided by the utility model, the communication control circuit is arranged between the first equipment and the second equipment, so that the I2C communication path between the first equipment and the second equipment is selectively cut off or connected through the communication control circuit according to the isolation control signal, and when the second equipment does not need to communicate with the first equipment, the communication between the first equipment and the second equipment is realized. According to the invention, the I2C communication path between the first device and the second device is cut off when the first device performs I2C communication with the second device, and the I2C communication path between the first device 10 and the second device is connected when the second device performs I2C communication with the first device, so that the I2C communication between the first device and the second device can be flexibly controlled according to actual requirements, and the problem of signal conflict is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display, and in particular to a communication control circuit and a display device. Background Art

[0002] Multiple devices can communicate with each other through a serial communication bus (Inter-Integrated Circuit, I 2 C) to achieve communication. When devices communicate with each other, I 2 If multiple devices want to participate in the communication, it is easy to make the I 2 C bus, affecting the normal operation of the system. Utility Model Content

[0003] The present invention provides a communication control circuit and a display device, which can improve I 2 C bus signal conflict problem.

[0004] The utility model embodiment provides a communication control circuit, wherein the communication control circuit is connected to the I 2 The communication control circuit is a circuit between a first device and a second device connected by a C bus communication, and the communication control circuit includes a first isolation unit and a second isolation unit. The first isolation unit is electrically connected between a first data signal port of the first device and a second data signal port of the second device, and the second isolation unit is electrically connected between a first clock signal port of the first device and a second clock signal port of the second device. At least one of the first isolation unit and the second isolation unit includes at least two transistors connected in sequence; the control end of each of the transistors is configured to receive an isolation control signal to control the working state of the transistor.

[0005] The present utility model also provides a display device, the display device comprising any of the above-mentioned communication control circuits and a third device, the third device being configured to communicate with the display device via the I 2 The I C bus is connected to the second device for communication. 2 When the first device and the second device communicate with each other, the communication control circuit is configured to cut off the I2C connection between the first device and the second device according to the isolation control signal. 2 C communication.

[0006] The utility model provides a communication control circuit and a display device, wherein a communication control circuit is arranged between a first device and a second device, so that the communication control circuit selectively cuts off or connects the I2C between the first device and the second device according to an isolation control signal. 2C communication path, so as to cut off the I2C communication path between the first device and the second device when the second device does not need to communicate with the first device. 2 C communication path, and the second device needs to communicate with the first device 2 When communicating with the first device 10, the I2C between the second device 10 is connected. 2 C communication path so that the I 2 C communication can be flexibly controlled according to actual needs, thereby improving the problem of signal conflict. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1A to Figure 1B The first device and the second device provided in the embodiment of the utility model are connected through I 2 Schematic diagram of C bus communication connection;

[0009] Figure 2 It is a schematic diagram of setting a communication control circuit between a first device and a second device provided by an embodiment of the utility model;

[0010] Figure 3A to Figure 3C It is a structural schematic diagram of a communication control circuit provided by an embodiment of the utility model;

[0011] Figure 4A to Figure 4C It is a timing diagram of data signals and clock signals provided by the embodiment of the utility model;

[0012] Figure 5 It is a schematic diagram of the structure of a display device provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the utility model, and are not used to limit the utility model. In the utility model, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0014] Specifically, Figure 1A to Figure 1B The first device and the second device provided in the embodiment of the utility model are connected through I 2 A schematic diagram of a C bus communication connection, in which a first device 10 and a second device 20 can communicate via I 2 C bus communication. 2 The C bus includes a data signal line SDA and a clock signal line SCL.

[0015] Optionally, the I 2 In addition to the first device 10 and the second device 20, other devices can also be added to the C bus, such as Figure 1A As shown, a third device 30 may be added so that the second device 20 can also be connected via I 2 C bus communicates with the third device 30.

[0016] The first device 10, the second device 20 and the third device 30 can all be connected to the network. 2 For example, when one of the first device 10, the second device 20, and the third device 30 is used as an I 2 When the master device of I C communication controls the entire communication process, the other two devices act as I 2 C communication slave device, participates in I 2 C communication process data transmission.

[0017] As an example, the first device 10 includes a system-level driver chip, the second device 20 includes a timing controller, and the third device 30 includes a flash memory, a power management chip, a level converter, and the like.

[0018] Please continue reading Figure 1A, the first device 10 includes a first data output terminal SDA1, a first clock output terminal SCL1 and a first write protection terminal WP1, and the second device 20 includes a second data output terminal SDA2, a second clock output terminal SCL2 and a second write protection terminal WP2. 2 In the C communication scenario, the first data signal port SDA1 of the first device 10 is electrically connected to the second data output terminal SDA2 of the second device 20 through the data signal line SDA, the first clock signal port SCL1 of the first device 10 is electrically connected to the second clock signal port SCL2 of the second device 20 through the clock signal line SCL, and the first write protection terminal WP1 of the first device 10 is electrically connected to the second write protection terminal WP2 of the second device 20.

[0019] In the above communication scenario, when the second device 20 also needs to communicate with the third device 30 2 C communication, the third device 30 includes a third data signal port SDA3 connected to the second data signal port SDA2 of the second device 20 through the data signal line SDA, and a third clock output terminal SCL3 connected to the second clock signal port SCL2 of the second device 20 through the clock signal line SCL. At this time, the communication between the second device 20 and the third device 30 needs to occupy the I 2 At the same time, since the communication between the first device 10 and the second device 20 also needs to use I 2 C bus and the second data output terminal SDA2 and the second clock output terminal SCL2 of the second device 20. Therefore, when the second device 20 has communication needs with the first device 10 and the third device 30, I 2 Signal conflicts may occur on the C bus and between the second data output terminal SDA2 and the second clock output terminal SCL2 of the second device 20.

[0020] For this reason, Figure 1B As shown, in the embodiment of the utility model, a communication control circuit 40 is set between the first device 10 and the second device 20. The communication control circuit 40 is located between the first device 10 and the second device 20, and the communication control circuit 40 is configured to selectively cut off or connect the I between the first device 10 and the second device 20 according to the isolation control signal SCS. 2 C communication path, so that when the second device 20 does not need to communicate with the first device 10, the I between the first device 10 and the second device 20 is cut off. 2 C communication path, and the second device 20 needs to communicate with the first device I 2 When the I2C communication is performed, the I2C between the first device 10 and the second device 20 is connected.2 C communication path, so that the I between the first device 10 and the second device 20 2 The C communication path can be flexibly controlled according to actual needs, thereby improving the problem of signal conflict.

[0021] Optionally, the first data output terminal SDA1 of the first device 10 is electrically connected to the data signal line SDA through the communication control circuit 40, the first clock output terminal SCL1 of the first device 10 is electrically connected to the clock signal line SCL through the communication control circuit 40, the second data output terminal SDA2 of the second device 20 is electrically connected to the data signal line SDA, and the second clock output terminal SCL2 of the second device 20 is electrically connected to the clock signal line SCL, so that the first device 10 and the second device 20 do not need to be I 2 C communication, the first device 10 and the second device 20 can still communicate with the device mounted on the I 2 Other devices on the C bus (such as the third device 30) perform I 2 C communication.

[0022] Figure 2 The present invention provides a schematic diagram of a communication control circuit provided between a first device and a second device, wherein the communication control circuit 40 includes two isolation units 40A, and the two isolation units 40A are configured to control the I between the first device 10 and the second device 20 according to the isolation control signal SCS. 2 C Communication path connectivity status.

[0023] Optionally, the two isolation units 40A include a first isolation unit 401 and a second isolation unit 402 .

[0024] The first isolation unit 401 is electrically connected between the first data signal port SDA1 of the first device 10 and the second data signal port SDA2 of the second device 20 .

[0025] The second isolation unit 402 is electrically connected between the first clock signal port SCL1 of the first device 10 and the second clock signal port SCL2 of the second device 20 .

[0026] By providing the first isolation unit 401 between the first data signal port SDA1 and the second data signal port SDA2, and providing the second isolation unit 402 between the first clock signal port SCL1 and the second clock signal port SCL2, the I2C between the first device 10 and the second device 20 is reduced. 2 C communication can be flexibly controlled according to actual needs.

[0027] Figure 3A to Figure 3C 1 is a schematic diagram of the structure of the communication control circuit provided by an embodiment of the utility model, each of the isolation units 40A may include at least one switch device, the switch device is controlled by the isolation control signal SCS, the switch device is electrically connected between signal ports outputting the same type and receives the isolation control signal SCS, so as to control the working state of the switch device through the isolation control signal SCS, so that the communication state between the first device 10 and the second device 20 can be flexibly controlled, for example, the level of the isolation control signal SCS can be controlled according to actual conditions to cut off or connect the I between the first device 10 and the second device 20. 2 C communication path, thereby realizing flexible control of the communication status between the first device 10 and the second device 20.

[0028] Optionally, the switch device includes a transistor, which includes a thin film transistor, a metal oxide semiconductor transistor, etc.

[0029] Optionally, see Figure 3A , the first isolation unit 401 and the second isolation unit 402 may each include a transistor Ts. The transistor Ts included in the first isolation unit 401 includes a control end configured to receive the isolation control signal SCS, and a first source-drain end electrically connected to the first data signal port SDA1, and a second source-drain end electrically connected to the second data signal port SDA2. The transistor Ts included in the second isolation unit 402 includes a control end configured to receive the isolation control signal SCS, a first source-drain end electrically connected to the first clock signal port SCL1, and a second source-drain end electrically connected to the second clock signal port SCL2. The transistor Ts is turned on or off according to the isolation control signal SCS to cut off or connect the I between the first device 10 and the second device 20. 2 C communication path. The control terminal may be a gate of a transistor, and the first source-drain terminal and the second source-drain terminal may be a source and a drain of the transistor, respectively. For example, when the first source-drain terminal is a source, the second source-drain terminal is a drain; when the first source-drain terminal is a drain, the second source-drain terminal is a source, which may be determined according to the type of the transistor.

[0030] based on Figure 3A In this way, there may be leakage current when the transistor is turned off. Therefore, when the transistor Ts is turned off by the isolation control signal SCS, the body diode inside the transistor Ts may be turned on, resulting in the existence of leakage current, so that the I between the first device 10 and the second device 20 2There is still a signal conflict on the C communication path, and the I / O between the first device 10 and the second device 20 and other devices (such as the third device 30) cannot be effectively resolved. 2 Therefore, to further solve this problem, at least one of the isolation units 40A includes at least two transistors Ts connected in sequence, such as Figure 3B to Figure 3C As shown. The control terminals of the two transistors Ts connected to each other are configured to receive the isolation control signal SCS, and the control terminals of the transistors Ts are configured to receive the isolation control signal SCS to control the working state of the transistors. In this way, since the isolation unit 40A includes two transistors Ts, even under the influence of leakage current, the leakage current flowing through one transistor will further reduce the influence of the leakage current after flowing through another transistor, which can effectively reduce the I between the second device 20 and other devices (such as the third device 30) caused by the existence of the leakage current. 2 C communication caused by the signal conflict problem.

[0031] Optionally, the first isolation unit 401 includes at least two transistors Ts, such as Figure 3B As shown, taking the first isolation unit 401 including a first transistor Ts1 and a second transistor Ts2 as an example, the first source-drain terminal of the first transistor Ts1 is electrically connected to the first data signal port SDA1, the first source-drain terminal of the second transistor Ts2 is electrically connected to the second data signal port SDA2, and the second source-drain terminal of the first transistor Ts1 is electrically connected to the second source-drain terminal of the second transistor Ts2.

[0032] By making the first isolation unit 401 include at least the first transistor Ts1 and the second transistor Ts2, when the first device 10 and the second device 20 are not communicating, the first device 10 can further improve the I between the second device 20 and other devices (such as the third device 30) caused by the leakage current. 2 C communication caused by the signal conflict problem.

[0033] Optionally, the second isolation unit 402 includes at least two transistors Ts, and the at least two transistors Ts include a third transistor Ts3 and a fourth transistor Ts4. A first source-drain terminal of the third transistor Ts3 is electrically connected to the first clock signal port SCL1, a first source-drain terminal of the fourth transistor Ts4 is electrically connected to the second clock signal port SCL2, and a second source-drain terminal of the third transistor Ts3 is electrically connected to a second source-drain terminal of the fourth transistor Ts4.

[0034] By making the second isolation unit 402 include at least the third transistor Ts3 and the fourth transistor Ts4, when the first device 10 and the second device 20 are not communicating, the first device 10 can further improve the I between the second device 20 and other devices (such as the third device 30) due to the influence of leakage current. 2 C communication caused by the signal conflict problem.

[0035] It can be understood that the first isolation unit 401 can also be provided with at least one transistor between the second source-drain terminal of the first transistor Ts1 and the second source-drain terminal of the second transistor Ts2, and the control terminals of the plurality of transistors are configured to receive the isolation control signal SCS. If the first isolation unit 401 further includes a fifth transistor, the control terminal of the fifth transistor can be configured to receive the isolation control signal SCS, the first source-drain terminal of the fifth transistor can be electrically connected to the second source-drain terminal of the first transistor Ts1, and the second source-drain terminal of the fifth transistor is electrically connected to the second source-drain terminal of the second transistor Ts2, so as to further improve the influence of leakage current. Similarly, at least one transistor can also be provided between the second source-drain terminal of the third transistor Ts3 and the second source-drain terminal of the fourth transistor Ts4 in the second isolation unit 402, so as to further improve the influence of leakage current.

[0036] Optionally, in order to reduce the impact of leakage current and reduce costs, each of the isolation units 40A may include two transistors Ts.

[0037] Optionally, the transistor Ts included in each isolation unit 40A is an oxide transistor, so as to utilize the low leakage current characteristic of the oxide transistor to further reduce the influence of the leakage current.

[0038] Optionally, the conduction direction of the body diode of the transistor Ts in each of the isolation units 40A may be controlled to further reduce the influence of the leakage current.

[0039] Optionally, in at least one of the isolation units 40A, the conduction directions of the body diodes in the two transistors connected to each other are opposite, so that the leakage current between the first device 10 and the second device 20 is blocked by the body diodes of the two transistors Ts. That is, since the conduction directions of the body diodes in the two transistors Ts are opposite, even under the influence of the leakage current, at most only one of the two body diodes is turned on and the other is turned off, which can effectively prevent the first device 10 from causing the I between the second device 20 and other devices (such as the third device 30) to be blocked due to the existence of the leakage current. 2 C communication caused by the signal conflict problem.

[0040] For example, see Figure 3C , the source of the first transistor Ts1 may be connected to the first data signal port SDA1, the source of the second transistor Ts2 may be connected to the second data signal port SDA2, and the drains of the first transistor Ts1 and the second transistor Ts2 may be connected to each other.

[0041] For another example, the drain of the first transistor Ts1 may be connected to the first data signal port SDA1, the drain of the second transistor Ts2 may be connected to the second data signal port SDA2, and the sources of the first transistor Ts1 and the second transistor Ts2 may be connected to each other.

[0042] For example, see Figure 3C , the source of the third transistor Ts3 may be connected to the first clock signal port SCL1, the source of the fourth transistor Ts4 may be connected to the second clock signal port SCL2, and the drains of the third transistor Ts3 and the fourth transistor Ts4 may be connected to each other.

[0043] For another example, the drain of the third transistor Ts3 may be connected to the first clock signal port SCL1, the drain of the fourth transistor Ts4 may be connected to the second clock signal port SCL2, and the sources of the third transistor Ts3 and the fourth transistor Ts4 may be connected to each other.

[0044] That is, the first source-drain terminal is a source, and the second source-drain terminal is a drain; or the first source-drain terminal is a drain, and the second source-drain terminal is a source.

[0045] Please continue reading Figure 3B to Figure 3C At least two transistors Ts included in the same isolation unit 40A can be controlled by the same isolation control signal SCS to reduce the number of signals required to be matched by the communication control circuit 40.

[0046] Optionally, the plurality of transistors Ts included in the same isolation unit 40A may also be controlled by the isolation control signal SCS from different signal sources, so that the plurality of transistors Ts may be independently controlled.

[0047] Please continue reading Figure 3A to Figure 3C The transistors Ts included in the plurality of isolation units 40A may be controlled by the same isolation control signal SCS to reduce the number of signals required to be matched by the communication control circuit 40 .

[0048] Optionally, the transistors Ts included in a plurality of the isolation units 40A may also be controlled by different isolation control signals SCS, so that the transistors Ts corresponding to each isolation unit 40A may be independently controlled.

[0049] Please continue reading Figure 1B and Figure 3A to Figure 3C , the first device 10 can be reused to generate the isolation control signal SCS to reduce the number of circuits corresponding to the communication control circuit 40.

[0050] If the first device 10 is controlled to generate the isolation control signal SCS alone, the internal design of the first device 10 needs to be adjusted, which is not conducive to cost control and increases the control difficulty. Therefore, the signal generated by the first device 10 can be used as the isolation control signal SCS to achieve control of the communication control circuit 40 without affecting the cost and control difficulty.

[0051] Optionally, the control terminal of each transistor Ts is electrically connected to the first write protection terminal WP1 of the first device 10, and the first device 10 is configured to output the isolation control signal SCS from the first write protection terminal WP1. That is, the first write protection signal output by the first device 10 from the first write protection terminal WP1 is multiplexed as the isolation control signal SCS to control the on / off state of the I2C communication path between the first device 10 and the second device 20 according to the level state of the first write protection signal.

[0052] Optionally, when the first device 10 and the second device 20 communicate, the first write protection signal has a high level. Accordingly, the transistor electrically connected to the first write protection terminal WP1 in the communication control circuit 40 is an N-type transistor, so that when the first device 10 and the second device 20 communicate, the first data signal port SDA1 is electrically connected to the second data signal port SDA2, and the first clock signal port SCL1 is electrically connected to the second clock signal port SCL2. That is, Figure 3A In the communication control circuit 40 shown in FIG. 1 , the transistor Ts is an N-type transistor; Figure 3A In the communication control circuit 40 shown, the two transistors Ts of the same isolation unit 40A are N-type transistors.

[0053] It can be understood that when the first device 10 and the second device 20 communicate, when the first write protection signal has a low level, the transistor Ts electrically connected to the first write protection terminal WP1 in the communication control circuit 40 is a P-type transistor.

[0054] Please continue reading Figure 3A to Figure 3C, the first isolation unit 401 includes a first resistor R1 and a second resistor R2. The first resistor R1 is connected in series between the first data signal port SDA1 and the first voltage terminal V1, and the second resistor R2 is connected in series between the second data signal port SDA2 and the first voltage terminal V1. The second isolation unit 402 includes a third resistor R3 and a fourth resistor R4, the third resistor R3 is connected in series between the first clock signal port SCL1 and the first voltage terminal V1, and the fourth resistor R4 is connected in series between the second clock signal port SCL2 and the first voltage terminal V1. Through the first resistor R1 to the fourth resistor R4 and the first voltage terminal V1, I 2 C bus provides a high level.

[0055] Optionally, the first voltage terminal V1 may correspond to a power management chip, and the voltage supplied by the first voltage terminal V1 may be 3.3V.

[0056] Optionally, when the first device 10 communicates with the second device 20, the communication state of the second device 20 with the other device may be changed to an interrupt state. Optionally, the communication state of the second device 20 with the other device may be controlled to be an interrupt state according to the level state of the isolation control signal SCS.

[0057] Optionally, at least one switch transistor may be provided between the third data signal port SDA3 and the data signal line SDA, and at least one switch transistor may be provided between the third clock signal port SCL3 and the clock signal line SCL, and the control end of the switch transistor is configured to receive the isolation control signal SCS. When the transistor included in the communication control circuit 40 is turned on, the switch transistor may be turned off according to the isolation control signal SCS, so that when the first device 10 communicates with the second device 20, the communication state of the second device 20 with other devices becomes an interrupted state.

[0058] Optionally, when the second device 20 communicates with other devices, the communication control circuit 40 is configured to cut off the communication path between the first device 10 and the second device 20. Optionally, the level state of the isolation control signal SCS can be controlled according to the communication state between the second device 20 and other devices, thereby controlling the on / off state of the communication path between the first device 10 and the second device 20.

[0059] Optionally, when the second device 20 communicates with other devices, the isolation control signal SCS has an invalid level, so as to control the disconnection of the communication path between the first device 10 and the second device 20 when the second device 20 communicates with other devices. When the second device 20 communicates with the first device 10, the isolation control signal SCS has a valid level.

[0060] It can be understood that the communication control circuit is not limited to being located between the first device 10 and the second device 20 , but can also be located between the second device 20 and the third device 30 .

[0061] Figure 4A to Figure 4C It is a timing diagram of data signal and clock signal provided by the embodiment of the utility model. Among them, Figure 4A It corresponds to Figure 3A The timing diagram of Figure 4B It corresponds to Figure 3B to Figure 3C Timing diagram; SDA_S is the signal output by the first data signal port SDA1, SCL_S is the signal output by the first clock signal port SCL1, SDA_T is the signal output by the second data signal port SDA2, and SCL_T is the signal output by the second clock signal port SCL2.

[0062] Please continue reading Figure 3A and Figure 4A , only one transistor Ts is set between the first device 10 and the second device 20, and when the isolation control signal SCS has an invalid level, due to the body diode effect of the transistor Ts, the turn-off effect of the transistor Ts is not good, the signal SDA_S output by the first data signal port SDA1 and the signal SDA_T output by the second data signal port SDA2 have similar change rules, and the signal SCL_S output by the first clock signal port SCL1 and the signal SCL_T output by the second clock signal port SCL2 have similar change rules.

[0063] It can be understood that the transistor Ts is an N-type transistor, and the isolation control signal SCS has an invalid level, that is, the isolation control signal SCS has a low level. The transistor Ts is a P-type transistor, and the isolation control signal SCS has an invalid level, that is, the isolation control signal SCS has a high level.

[0064] Please continue reading Figure 3B to Figure 3C and Figure 4B to Figure 4C , the working principle of the communication control circuit 40 is explained.

[0065] Please continue reading Figure 3B to Figure 3C and Figure 4BWhen the isolation control signal SCS has an invalid level, the first transistor Ts1 to the fourth transistor Ts4 are turned off, the signal SDA_S output by the first data signal port SDA1 and the signal SDA_T output by the second data signal port SDA2 are independent of each other, the signal SCL_S output by the first clock signal port SCL1 and the signal SCL_T output by the second clock signal port SCL2 are independent of each other, and the communication control circuit 40 implements signal isolation between the first device 10 and the second device 20, which can prevent I 2 C bus, causing signal conflicts and interference.

[0066] Please continue reading Figure 3B to Figure 3C and Figure 4C When the isolation control signal SCS has a valid level, the first transistor Ts1 to the fourth transistor Ts4 are turned on, the signal SDA_S output by the first data signal port SDA1 is the same as the signal SDA_T output by the second data signal port SDA2, the signal SCL_S output by the first clock signal port SCL1 is the same as the signal SCL_T output by the second clock signal port SCL2, and the communication control circuit 40 realizes the communication connection between the first device 10 and the second device 20.

[0067] It should be noted that Figure 4A to Figure 4C The timing shown is for exemplary purposes only and is not intended to limit the signal frequency, waveform, and amplitude of the present application.

[0068] Figure 5 The utility model also provides a display device, comprising any of the above-mentioned communication control circuits 40 and a third device 30 .

[0069] The third device 30 is configured to 2 The I2C bus is connected to the second device 20 for communication. 2 When the first device 10 and the second device 20 communicate with each other, the communication control circuit 40 is configured to cut off the I2C connection between the first device 10 and the second device 20 according to the isolation control signal SCS. 2 C communication.

[0070] Optionally, the first isolation unit 401 includes a first input-output terminal and a second input-output terminal, the second isolation unit 402 includes a third input-output terminal and a fourth input-output terminal, the first input-output terminal is electrically connected to the first data signal port SDA1, the second input-output terminal is electrically connected to the second data signal port SDA2, the third input-output terminal is electrically connected to the first clock signal port SCL1, and the fourth input-output terminal is electrically connected to the second clock signal port SCL2. The third device 30 is electrically connected to the second input-output terminal and the fourth input-output terminal. When the two signal isolation units 40A disconnect the communication transmission path between the first device 10 and the second device 20 according to the isolation control signal SCS, the second device 20 can communicate with the third device 30.

[0071] Optionally, the first device 10 includes a system-level driver chip, the second device 20 includes a timing controller, and the third device 30 includes a non-volatile memory, a power management chip, a level converter, and the like.

[0072] Because in the display device, the timing controller uses I 2 C communicates with system-level control chips, power management driver chips and other devices. However, since there is no memory management device in the power management driver chip, the timing controller needs to read the data in the non-volatile memory to write it into the register of the power management driver chip. In addition, during the vertical blanking interval, the timing controller will monitor whether the settings of the power management chip are incorrect. Therefore, I 2 The I C bus will be continuously occupied. If the system-level chip needs to upgrade the timing controller code, it is easy to cause I 2 C bus, resulting in abnormal display.

[0073] The present application provides a display device including the communication control circuit 40. When the system-level chip needs to perform a code upgrade on the timing controller, the isolation control signal SCS has a valid level to control the communication control circuit 40 to realize the electrical connection between the system-level chip and the timing controller, so that the system-level chip communicates with the timing controller. When the system-level chip does not need to perform a code upgrade on the timing controller, the isolation control signal SCS has an invalid level to disconnect the communication connection between the system-level chip and the timing controller, so that the system-level chip does not communicate with the timing controller, so that I 2 The signals on the C bus are independent of each other, which is beneficial to improve the 2 C bus caused by signal conflicts.

[0074] Optionally, when the first device 10 needs to communicate with the second device 20, the communication state between the second device 20 and the third device 30 may be changed to an interrupted state.

[0075] Optionally, the first device 10 may be integrated on a first circuit board B1, and at least one of the second device 20, the third device 30 and the communication control circuit 40 may be integrated on a second circuit board B2.

[0076] Optionally, the display device further includes a display panel DP, and the display panel DP is electrically connected to the first circuit board B1 and the second circuit board B2 via a third circuit board B3. The first circuit board B1 and the second circuit board B2 may be connected by connecting wires such as a flexible circuit board B4, the second circuit board B2 and the third circuit board B3 may be connected by connecting wires such as a flexible circuit board B4, and the third circuit board B3 and the display panel DP may be connected by a flexible circuit board or a chip-on-film B5.

[0077] Understandably, Figure 5 The display device shown is only for illustrative purposes, and those skilled in the art can set the number of circuit boards according to requirements. That is, the display device can include at least one of the first circuit board B1, the second circuit board B2, and the third circuit board B3 according to requirements. Accordingly, the positions of the first device 10 to the third device 30 and the communication control circuit 40 can be set according to requirements.

[0078] Optionally, the display panel DP includes a passive light-emitting display panel, a self-luminous display panel, etc. Optionally, the passive light-emitting display panel includes a liquid crystal display panel, etc. The self-luminous display panel includes a display panel with a light-emitting device as a sub-pixel. The light-emitting device includes at least one of a micro light-emitting diode, a sub-millimeter light-emitting diode, an organic light-emitting diode, etc.

[0079] This article uses specific examples to illustrate the principles and implementation methods of the utility model. The description of the above embodiments is only used to help understand the method and core idea of ​​the utility model. At the same time, for technical personnel in this field, according to the idea of ​​the utility model, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the utility model.

Claims

1. A communication control circuit, characterized in that: Connect via I 2 C bus communication connection between a first device and a second device, the communication control circuit comprises: A first isolation unit electrically connected between the first data signal port of the first device and the second data signal port of the second device; and A second isolation unit, electrically connected between the first clock signal port of the first device and the second clock signal port of the second device; At least one of the first isolation unit and the second isolation unit includes at least two transistors connected in sequence; and a control terminal of each of the transistors is configured to receive an isolation control signal to control a working state of the transistor.

2. The communication control circuit according to claim 1, characterized in that: The body diodes in the two transistors connected to each other are conducted in opposite directions.

3. The communication control circuit according to claim 1 or 2, characterized in that: The first isolation unit includes at least two transistors, and the at least two transistors include a first transistor and a second transistor, the first source and drain terminals of the first transistor are electrically connected to the first data signal port, the first source and drain terminals of the second transistor are electrically connected to the second data signal port, and the second source and drain terminals of the first transistor are electrically connected to the second source and drain terminals of the second transistor.

4. The communication control circuit according to claim 1 or 2, characterized in that: The second isolation unit includes at least two of the transistors, and the at least two of the transistors include a third transistor and a fourth transistor. The first source and drain end of the third transistor is electrically connected to the first clock signal port, the first source and drain end of the fourth transistor is electrically connected to the second clock signal port, and the second source and drain end of the third transistor is electrically connected to the second source and drain end of the fourth transistor.

5. The communication control circuit according to claim 3, characterized in that: The first source-drain terminal is a source, and the second source-drain terminal is a drain.

6. The communication control circuit according to claim 1, characterized in that: The control terminal of each of the transistors is electrically connected to a first write protection terminal of the first device, and the first device is configured to output the isolation control signal from the first write protection terminal.

7. The communication control circuit according to claim 1, characterized in that: The transistor is an N-type transistor.

8. The communication control circuit according to claim 1, characterized in that: The first isolation unit includes a first resistor and a second resistor, the first resistor is connected in series between the first data signal port and the first voltage terminal, and the second resistor is connected in series between the second data signal port and the first voltage terminal; The second isolation unit includes a third resistor and a fourth resistor, the third resistor is connected in series between the first clock signal port and the first voltage terminal, and the fourth resistor is connected in series between the second clock signal port and the first voltage terminal.

9. A display device, characterized in that: include: The communication control circuit according to any one of claims 1 to 8; as well as a third device, the third device being configured to transmit the signal to the 2 C bus is communicatively connected with the second device; Wherein, the second device and the third device perform I 2 When the first device and the second device communicate with each other, the communication control circuit is configured to cut off the I2C connection between the first device and the second device according to the isolation control signal. 2 C communication.

10. The display device according to claim 9, characterized in that: The first device is a system-level driver chip, the second device is a timing controller, and the third device is a flash memory or a power management driver chip.

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