Latch integrating circuit suitable for analog-to-digital converter

Abstract

The utility model relates to a latch integrating circuit suitable for an analog-to-digital converter, which comprises an MCU unit, an integrating unit and a latch unit, the control end of the MCU unit is connected with the controlled end of the latch unit, the output end of the latch unit is connected with the input end of the integrating unit, and the output end of the integrating unit is a signal output end. According to the utility model, the accuracy of the integral unit can be improved.

Description

Technical Field

[0001] The utility model relates to a latch integration circuit suitable for an analog-to-digital converter. Background Art

[0002] The rapid development of computer technology, communication technology and microelectronics technology has greatly promoted the development of analog to digital converters (ADCs). The output of an analog to digital converter can be regarded as a description of an analog signal.

[0003] After searching, the patent: analog-to-digital converter (CN202111304548.1) includes a charge distribution and holding module, a common-mode voltage compensation module and a comparator. The charge distribution and holding module samples the signal to be converted and performs subtraction processing with the target reference voltage to provide a positive output voltage and a negative output voltage. The comparator compares the positive output voltage and the negative output voltage to obtain a logic signal, which corresponds to the comparison result between the target reference voltage and the signal to be converted. The common-mode voltage compensation module compensates for the distributed charge of the charge distribution and holding module to pull the output common-mode voltage of the charge distribution and holding module to the expected value.

[0004] At present, the oversampling analog-to-digital converter is a commonly used analog-to-digital converter, and the ∑-Δ ADC (Sigma-Delta analog-to-digital converter) is widely used. The ∑-Δ ADC may include an anti-aliasing filter, a ∑-Δ modulator, and a downsampling filter. Specifically, the analog signal first passes through the anti-aliasing filter to attenuate the noise and components outside the frequency band, and then the ∑-Δ modulator performs oversampling and noise shaping processing on the analog signal output by the anti-aliasing filter, and converts it into a high-speed, low-resolution bit stream (i.e., a 1-bit data stream). Finally, the bit stream passes through the downsampling filter to filter out the high-frequency noise outside the signal frequency band and the downsampling extraction processing, and is converted into a low-speed, high-resolution digital signal and outputs it. It can be understood that the output result of the downsampling filter is the description of the analog signal. However, the traditional analog-to-digital converter has the problem that the description of the analog signal is not fine enough and there are limitations.

[0005] In view of the above-mentioned defects, the designers have actively carried out research and innovation in order to create a new structure of latch integration circuit suitable for analog-to-digital converters, making it more valuable for industrial use. Utility Model Content

[0006] In order to solve the above technical problems, the purpose of the utility model is to provide a latch integration circuit suitable for an analog-to-digital converter.

[0007] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0008] A latch integration circuit suitable for an analog-to-digital converter comprises an MCU unit, an integration unit and a latch unit, wherein a control end of the MCU unit is connected to a controlled end of the latch unit, an output end of the latch unit is connected to an input end of the integration unit, and an output end of the integration unit is a signal output end;

[0009] The integration unit includes a chip IC1B, a sixth pin of the chip IC1B is connected to a fifth pin of the chip IC1B through a capacitor C5, a sixth pin of the chip IC1B is connected to a seventh pin of the chip IC1B through a capacitor C1, capacitor C1 is connected to capacitors C6 and C11 in parallel, a sixth pin and a fifth pin of the chip IC1B are connected to an input signal through resistors R1 and R2, respectively, a sixth pin and a fifth pin of the chip IC1B are connected to an input end of the latch unit through resistors R18 and R19, respectively, and a fifth pin of the chip IC1B is grounded through capacitors C4, C7 and C11 in parallel.

[0010] Preferably, in the latch integrator circuit suitable for an analog-to-digital converter, the chip model of the MCU unit is LPC1115.

[0011] Preferably, in the latch integration circuit suitable for an analog-to-digital converter, the chip model of the chip IC1B is OP07.

[0012] Preferably, the latch integration circuit suitable for an analog-to-digital converter, the latch unit includes a chip IC5, the first pin, the fourth pin and the fourteenth pin of the chip IC5 are connected to the second pin of the chip IC5 through a capacitor C21, the third pin of the chip IC5 is connected to the output end of the MCU unit, and the fifth pin and the sixth pin of the chip IC5 are connected to the input end of the integration unit.

[0013] Preferably, in the latch integration circuit suitable for an analog-to-digital converter, the chip model of the chip IC5 is 74LS279.

[0014] By means of the above solution, the utility model has at least the following advantages:

[0015] The utility model can improve the accuracy of the output signal of the integration unit by cooperating the signal output by the latch unit each time with the integration unit.

[0016] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the utility model in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a principle block diagram of the utility model;

[0019] Figure 2 It is the actual circuit diagram of the utility model. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0022] Example

[0023] like Figure 1 and Figure 2 As shown, a latch integration circuit suitable for an analog-to-digital converter comprises an MCU unit 1, an integration unit 2 and a latch unit 3, wherein the control end of the MCU unit 1 is connected to the controlled end of the latch unit 3, the output end of the latch unit 3 is connected to the input end of the integration unit 2, and the output end of the integration unit 2 is a signal output end;

[0024] The integration unit 2 includes a chip IC1B, a sixth pin of the chip IC1B is connected to a fifth pin of the chip IC1B through a capacitor C5, a sixth pin of the chip IC1B is connected to a seventh pin of the chip IC1B through a capacitor C1, capacitor C1 is connected to capacitors C6 and C11 in parallel, a sixth pin and a fifth pin of the chip IC1B are connected to an input signal through resistors R1 and R2, respectively, a sixth pin and a fifth pin of the chip IC1B are connected to an input end of the latch unit 3 through resistors R18 and R19, respectively, and a fifth pin of the chip IC1B is grounded through capacitors C4, C7 and C11 in parallel.

[0025] The chip model of the MCU unit 1 in the present invention is LPC1115.

[0026] The chip model of the chip IC1B in the present invention is OP07.

[0027] The latch unit 3 in the utility model includes a chip IC5, wherein the first pin, the fourth pin and the fourteenth pin of the chip IC5 are connected to the second pin of the chip IC5 through a capacitor C21, the third pin of the chip IC5 is connected to the output end of the MCU unit 1, and the fifth pin and the sixth pin of the chip IC5 are connected to the input end of the integration unit 2, wherein the chip model of the chip IC5 is 74LS279.

[0028] The working principle of the utility model is as follows:

[0029] During specific operation, the control signal of the MCU unit controls the latch unit, transmits the signal of the latch unit to the integration unit, and also combines (integrates) the original input signal of the integration unit. Finally, the input signal is combined with the latch signal each time through the integration unit to output a more accurate output signal.

[0030] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0031] In the description of this application, it should be noted that the terms "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0032] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or vertical, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0033] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principle of the present invention, and these improvements and modifications should also be regarded as within the protection scope of the present invention.

Claims

1. A latch integrator circuit suitable for an analog-to-digital converter, characterized in that: It comprises an MCU unit (1), an integration unit (2) and a latch unit (3), wherein the control end of the MCU unit (1) is connected to the controlled end of the latch unit (3), the output end of the latch unit (3) is connected to the input end of the integration unit (2), and the output end of the integration unit (2) is a signal output end; The integration unit (2) comprises a chip IC1B, wherein the sixth pin of the chip IC1B is connected to the fifth pin of the chip IC1B via a capacitor C5, the sixth pin of the chip IC1B is connected to the seventh pin of the chip IC1B via a capacitor C1, the capacitor C1 is connected to a capacitor C6 and a capacitor C11 connected in parallel, the sixth pin and the fifth pin of the chip IC1B are connected to an input signal via a resistor R1 and a resistor R2 respectively, the sixth pin and the fifth pin of the chip IC1B are connected to an input end of the latch unit (3) via a resistor R18 and a resistor R19 respectively, and the fifth pin of the chip IC1B is grounded via a capacitor C4, a capacitor C7 and a capacitor C11 connected in parallel.

2. A latch integrator circuit suitable for an analog-to-digital converter according to claim 1, characterized in that: The chip model of the MCU unit (1) is LPC1115.

3. The latch integration circuit suitable for an analog-to-digital converter according to claim 1, characterized in that: The chip model of the chip IC1B is OP07.

4. The latch integration circuit suitable for an analog-to-digital converter according to claim 1, characterized in that: The latch unit (3) comprises a chip IC5, wherein the first pin, the fourth pin and the fourteenth pin of the chip IC5 are connected to the second pin of the chip IC5 via a capacitor C21, the third pin of the chip IC5 is connected to the output end of the MCU unit (1), and the fifth pin and the sixth pin of the chip IC5 are connected to the input end of the integration unit (2).

5. The latch integration circuit suitable for an analog-to-digital converter according to claim 4, characterized in that: The chip model of the chip IC5 is 74LS279.

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