Memory module and module equipment

Abstract

The utility model discloses a memory module and module equipment. The memory module comprises a circuit board, a first functional unit and a second functional unit, the circuit board comprises a first layer board and a second layer board which are laminated and attached, the first function unit is arranged on the first layer board, the second function unit is arranged on the second layer board, and the first function unit and the second function unit are overlapped; wherein the interconnection structures used for electrically connecting the first layer plate and the second layer plate are all arranged outside an overlapping area, and the overlapping area is an overlapping area of the first function unit and the second function unit. The utility model provides a scheme for reducing the size of the memory module and ensuring the performance.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, and in particular to a memory module and a module device. Background Art

[0002] With the development of electronic technology, the application scenarios of various electronic products are becoming increasingly diverse. In order to meet the needs of different scenarios, miniaturization is one of the important development directions.

[0003] Currently, memory modules in various products are often designed in accordance with the JEDEC (Joint Electron Device Engineering Council) standard size. However, taking the DDR5 RDIMM (Registered Dual In-line Memory Module) module as an example, according to the JEDEC standard MO-329E, its external dimensions are 133.35mm*31.25mm, and its height of 31.25mm can no longer meet the needs of small-size systems. There is an urgent need for a memory module design solution that can be used in small-size systems. Utility Model Content

[0004] In view of the above problems, the present invention is proposed to provide a memory module and module device that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, a memory module is provided, comprising:

[0006] A circuit board, a first functional unit and a second functional unit;

[0007] The circuit board comprises a first layer board and a second layer board which are laminated and bonded together, the first functional unit is arranged on the first layer board, the second functional unit is arranged on the second layer board, and the first functional unit and the second functional unit at least partially overlap;

[0008] Wherein, the interconnection structure for electrically connecting the first layer board and the second layer board is arranged outside the overlapping area, and the overlapping area is the area where the first functional unit and the second functional unit overlap.

[0009] Optionally, a first group of blind holes is opened in the first layer board, and the first functional units are interconnected in the first layer board through the first group of blind holes; a second group of blind holes is opened in the second layer board, and the second functional units are interconnected in the second layer board through the second group of blind holes.

[0010] Optionally, the first group of blind holes and the second group of blind holes are arranged in the overlapping area; the circuit board is provided with through holes for electrically connecting the first layer board and the second layer board, and the through holes are located outside the overlapping area.

[0011] Optionally, the first functional unit is a power management chip, and the second functional unit is a registered clock driver.

[0012] Optionally, the first functional unit also includes a large current routing and / or a low-frequency switching signal routing corresponding to the power management chip; the second functional unit also includes a high-speed digital signal routing corresponding to the registered clock driver.

[0013] Optionally, the memory module further includes: a serial detection hub, which is disposed on the first layer board and is electrically connected to the power management chip.

[0014] Optionally, the memory module further includes: a serial detection hub, and a power supply end of the serial detection hub is connected in series with a ferrite bead.

[0015] Optionally, the memory module further includes: a serial detection hub and a bus, a matching resistor is connected in series to a source end of the bus, and the source end is an end of the bus electrically connected to the serial detection hub.

[0016] Optionally, the resistance of the matching resistor is greater than 20 ohms and less than 50 ohms.

[0017] In a first aspect, a module device is provided, comprising: a memory module as described in any one of the first aspects.

[0018] The technical solution provided in the embodiment of the utility model has at least the following technical effects or advantages:

[0019] The memory module and module device provided by the embodiment of the utility model are provided with a circuit board including a first layer board and a second layer board, and the first functional unit and the second functional unit are respectively arranged on different layers, in an overlapping state. Compared with the existing tiled arrangement of the first functional unit and the second functional unit, this can effectively reduce the size of the memory module and is suitable for the needs of small-size systems. Furthermore, an interconnection structure for electrically connecting the first layer board and the second layer board is also provided, and both are located outside the overlapping area of ​​the two functional units, which can reduce signal interference between the two functional units, and the performance of the memory module is taken into account while reducing the size.

[0020] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not considered to be limiting of the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0022] Figure 1 A front view of a DDR5 RDIMM designed according to the JEDEC standard is shown as an example;

[0023] Figure 2 for Figure 1 Schematic diagram of the reverse side;

[0024] Figure 3 A schematic diagram of a memory module in an embodiment of the present application;

[0025] Figure 4 A front schematic diagram of a DDR5 RDIMM designed in an embodiment of the present application;

[0026] Figure 5 for Figure 4 The reverse side example diagram of ;

[0027] Figure 6 A schematic diagram of a serial detection hub and its peripheral circuits in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the dimensions of a DDR5 RDIMM prepared according to the existing JEDEC standard;

[0029] Figure 8 A schematic diagram of the dimensions of a DDR5 RDIMM prepared in an embodiment of the present application;

[0030] Fig. 9 It is a schematic diagram of the structure of the module device in the embodiment of the present application. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0032] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0033] See also Figure 1 and Figure 2 , Figure 1 The front view of a DDR5 RDIMM designed according to the JEDEC standard is shown as an example. Figure 2 for Figure 1 The units marked with UA and UB in the figure are all storage units, and the first functional unit 110 (for example, a power management chip) and the second functional unit 120 (for example, a register clock driver) are arranged flat on the circuit board 130. Due to the space limitation on the circuit board 130, the size of the memory module cannot be reduced, and its height of 31.25 mm makes it impossible to install it in a small-sized system.

[0034] The present application embodiment provides a memory module, see Figure 3 , Figure 3 Schematic diagram of the memory module in the embodiment of the present application. It includes a circuit board 130, a first functional unit 110 and a second functional unit 120. The circuit board 130 includes a first layer board 131 and a second layer board 132 that are laminated and bonded. The first functional unit 110 is arranged on the first layer board 131, and the second functional unit 120 is arranged on the second layer board 132. The first functional unit 110 and the second functional unit 120 at least partially overlap. Among them, the interconnection structure 140 for electrically connecting the first layer board 131 and the second layer board 132 are all arranged outside the overlapping area, which is the area where the first functional unit 110 and the second functional unit 120 overlap.

[0035] It should be noted that the memory module can be an RDIMM, a Single In-line Memory Module (SIMM), or a Load Reduced DIMM (LRDIMM), which is not limited here. The first functional unit 110 and the second functional unit 120 can be any functional unit except a storage unit, for example, they can be a power management chip and a register clock driver, or a serial detection hub and a buffer, respectively, which is not limited here. The interconnection structure 140 can be a through-hole structure, or a copper pillar structure or an interlayer routing structure, which is not limited here.

[0036] Specifically, the first functional unit 110 and the second functional unit 120 are respectively arranged on different layers of the circuit board 130, and are arranged in an overlapping manner, so that the circuit board area occupied by the first functional unit 110 and the second functional unit 120 is reduced, thereby reducing the size of the memory module so that it can be used in a small-size system. In addition, by not providing an interconnection structure such as a through hole connecting the first layer 131 and the second layer 132 in the overlapping area of ​​the two functional units, the signal interference between different layers can be shielded in the overlapping area to prevent affecting the operation of the two functional units, thereby ensuring the performance of the memory module.

[0037] In an optional embodiment, if Figure 3 As shown, a first group of blind holes 301 may be provided in the first layer board 131, and the first functional units 110 are interconnected in the first layer board 131 through the first group of blind holes 301. A second group of blind holes 302 may be provided in the second layer board 132, and the second functional units 120 are interconnected in the second layer board 132 through the second group of blind holes 302. The first group of blind holes 301 are holes only provided in the first layer board 131, and both ends thereof are located in the first layer board 131, and play the role of routing in the first layer board 131. The second group of blind holes 302 are holes only provided in the second layer board 132, and both ends thereof are located in the second layer board 132, and play the role of routing in the second layer board 132. Specifically, blind holes are provided to respectively realize the interconnection of the first functional unit 110 and the interconnection of the second functional unit 120, so that interference between the two functional units can be avoided while realizing the interconnection.

[0038] In an optional embodiment, if Figure 3As shown, a first group of blind holes 301 and a second group of blind holes 301 may also be provided in the overlapping area of ​​the first functional unit 110 and the second functional unit 120. That is to say, the first group of blind holes 301 is entirely or partially located in the overlapping area, and the second group of blind holes 302 is also entirely or partially located in the overlapping area. In addition, the circuit board 130 is also provided with a plurality of through holes for electrically connecting the first layer board 131 and the second layer board 132, and the plurality of through holes are located outside the overlapping area of ​​the two functional units. Specifically, the through hole, i.e., the interconnection structure 140, is used to realize the electrical connection between the first layer board 131 and the second layer board 132. Arranging it outside the overlapping area can realize the electrical connection requirements between different layer boards on the one hand, and avoid signal interference in the overlapping area on the other hand, thereby ensuring the performance of the memory module.

[0039] In an optional embodiment, the circuit board 130 may be prepared in the following manner: first, N layers of sheet material are pressed into a first layer board 131, wherein the N layers of sheet material are conductor layers (such as copper layers, alloy conductor layers) and insulating dielectric layers stacked at intervals. N layers of sheet material of the same number and material are pressed into a second layer board 132. Then, a first group of blind holes 301 are opened on the first layer board 131 (the first group of blind holes 301 at this time may pass through the first layer board 131), and a second group of blind holes 302 are opened on the second layer board 132 (the second group of blind holes 302 at this time may pass through the second layer board 132). Next, the first layer board 131 and the second layer board 132 are bonded with glue and then pressed into the final circuit board 130. Finally, through holes are opened on the circuit board 130 to achieve electrical connection between different layers. In this way, the first functional unit 110 prepared in the first layer board 131 and the second functional unit 120 prepared in the second layer board 132 can be isolated and shielded by the insulating medium between the first layer board 131 and the second layer board 132, and can also realize intra-layer electrical interconnection through the blind holes in the respective layers, and realize inter-layer electrical interconnection through the through holes arranged outside the overlapping area. That is, the interference between the functional units is reduced, the interconnection is realized, and the performance is guaranteed.

[0040] In an optional implementation, the first functional unit 110 can be set as a power management chip (PowerManagement IC, PMIC), and the second functional unit 120 can be set as a registering clock driver (Registering Clock Driver, RCD). Since the area occupied by the power management chip and the registering clock driver is relatively large, and the related wiring of the power management chip transmits large current or low-frequency switching signals, and the related wiring of the registering clock driver transmits high-speed digital signals, these two units are respectively set on different layers (front and back) of the circuit board in the manner provided by the present application to reduce the area, and the interconnection structure 140 for interlayer electrical connection is set outside the overlapping area of ​​the two functional units, or is set in the peripheral area of ​​the two functional units to reduce interference between signals, which can effectively take into account the size reduction requirements and performance requirements of the memory module.

[0041] In an optional embodiment, the first functional unit 110 also includes a high current routing and / or a low frequency switching signal routing corresponding to the power management chip. The second functional unit 120 also includes a high speed digital signal routing corresponding to the register clock driver. Alternatively, the first functional unit 110 may also include a peripheral circuit of the power management chip, and the second functional unit 120 may also include a peripheral circuit of the register clock driver. In this way, the high speed digital signal routing and the high current routing (or low frequency switching signal routing) are respectively arranged on different layers, which can further reduce signal interference.

[0042] In an optional embodiment, the memory module may further include a serial detection hub (SPD Hub), which is the master device of the local bus of the memory module and is used to integrate the functions of the electrically erasable programmable read-only storage medium and the bus converter. The serial detection hub is arranged in the first layer board 131 and is electrically connected to the power management chip. For details, please refer to Figure 4 and Figure 5 , Figure 4 This is a front view of a DDR5 RDIMM designed in an embodiment of the present application. Figure 5 for Figure 4 The reverse side example diagram. Figure 4 and Figure 5 The first functional unit 110 is a power management chip and its peripheral circuits, and the second functional unit 120 is a registered clock driver and its peripheral circuits. Since part of the output end of the power management chip is connected to the serial detection hub 401, in order to reduce interconnection interference, the serial detection hub 401 is set in the same layer board of the power management chip. Of course, the serial detection hub 401 can also be set in the same layer board as the registered clock driver, which is not limited here.

[0043] In an optional implementation, the power supply end of the serial detection hub 401 of the memory module may be connected in series with a ferrite bead 402. Figure 6 As shown, the serial detection hub 401 can have two power supply lines VIO (for example, 1.0V, used to power the storage unit) and VSPD (for example, 1.8V, used to power the bus converter), and ferrite beads 402 are connected in series at both power supply ends to eliminate high-frequency AC noise coupled to the DC power supply to ensure the stable operation of the local bus of the memory module in the system environment.

[0044] In an optional embodiment, if Figure 6 As shown, the serial detection hub of the memory module can be set as a master device and electrically connected to the source end of the bus 601, and a matching resistor 403 is connected in series at the source end of the bus. The matching resistor 403 can effectively eliminate signal reflection and improve the working stability of the local bus of the memory module under the system environment. Among them, the resistance value of the matching resistor 403 can be set to be greater than 20 ohms and less than 50 ohms, for example, 33 ohms.

[0045] Specifically, by connecting a ferrite bead 402 in series at the power supply end of the serial detection hub 401, and / or connecting a matching resistor 403 in series at the source end of the bus, the interference to the high-speed signal caused by stacking the power management chip and the registered clock driver on different layers of the circuit board can be effectively alleviated, thereby ensuring the performance of the memory module.

[0046] Combine the following Figure 4 and Figure 5 A specific example is used to help understand the layout idea of ​​the memory module provided by the present application. The units marked with UA and UB in the figure are all storage units.

[0047] like Figure 4 As shown, the clock driver RCD is arranged on the front of the circuit board, located in the second layer, and the peripheral circuit of the clock driver is also arranged in the second layer. There is no through hole in the clock driver and its peripheral circuit area, and the area is electrically connected in the second layer through a second group of blind holes.

[0048] like Figure 5 As shown, the power management chip PMIC and the serial detection hub SPDHUB are both arranged on the reverse side of the circuit board, located in the first layer board. Figure 5 L5 and L6 in the figure are ferrite beads 402, and R156 and R157 are matching resistors 403. The peripheral circuits of the power management chip and the serial detection hub (such as Figure 5 L2, L3, L4 and surrounding components in the first layer are also arranged in the first layer. Among them, no through holes are set in the power management chip and its surrounding circuit area, and this area is electrically connected in the first layer through the first group of blind holes.

[0049] In this way, a combination of through holes and blind holes is used, and blind holes are used for electrical connection in the peripheral area of ​​the power management chip and the registered clock driver (or blind holes are used for electrical connection in the overlapping area of ​​the power management chip and the registered clock driver). This can effectively reduce the interference problems caused by the stacking design of the power management chip and the registered clock driver, reduce the module size while ensuring performance.

[0050] See also Figure 7 and Figure 8 , Figure 7 The following is a schematic diagram of the dimensions of a DDR5 RDIMM prepared according to the existing JEDEC standard. The corresponding memory module dimensions are 133.35mm*31.25mm. Figure 8 The following is a schematic diagram of the dimensions of the DDR5 RDIMM prepared in the embodiment of the present application. The corresponding memory module has an external dimension of 133.35 mm*18.75 mm. It can be seen that the memory module solution provided by the present application can significantly reduce its external dimension and can be applied to small-size systems.

[0051] In addition, the present application arranges the first functional unit and the second functional unit on different layers, and arranges the interconnection structure for electrically connecting the first layer and the second layer outside the overlapping area of ​​the two functional units, which can reduce the signal interference between the two functional units, and on the basis of reducing the size, the performance of the memory module is also taken into account, and can support data rate applications up to 5600Mbps.

[0052] Based on the same concept, the present application also provides a module device, characterized in that: Fig. 9 As shown, it includes: the memory module 901 provided in the above embodiment.

[0053] Since the principle and structure of the memory module included in the module device introduced in the embodiment of the present application have been described in detail in the above embodiment, they will not be repeated here. All module devices including the memory module of the embodiment of the present utility model belong to the scope of protection of the present utility model.

[0054] The technical solution provided in the embodiment of the utility model has at least the following technical effects or advantages:

[0055] The memory module and module device provided by the embodiment of the utility model are provided with a circuit board including a first layer board and a second layer board, and the first functional unit and the second functional unit are respectively arranged on different layers, in an overlapping state. Compared with the existing tiled arrangement of the first functional unit and the second functional unit, this can effectively reduce the size of the memory module and is suitable for the needs of small-size systems. Furthermore, an interconnection structure for electrically connecting the first layer board and the second layer board is also provided, and both are located outside the overlapping area of ​​the two functional units, which can reduce signal interference between the two functional units, and the performance of the memory module is taken into account while reducing the size.

[0056] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general purpose systems may also be used together with the teachings based thereon. Based on the above description, it is apparent that the structure required for constructing such systems is. In addition, the present invention is not directed to any particular programming language either. It should be understood that various programming languages ​​may be utilized to implement the content of the present invention described herein, and the description of the above specific languages ​​is intended to disclose the best mode of implementation of the present invention.

[0057] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0058] Those skilled in the art will appreciate that the modules in the system or device in the embodiment can be adaptively changed and set in one or more devices different from the embodiment. The modules or units or components in the embodiment can be combined into one module or unit or component, and in addition they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner can be combined in any combination. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) can be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0059] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present invention and to form different embodiments.

[0060] It should be noted that the above embodiments illustrate the utility model rather than limit the utility model, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation to the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "one" or "an" before a component does not exclude the presence of multiple such components. The utility model can be implemented by means of hardware including several different components and by means of appropriately programmed computers. In a unit claim that lists several devices, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Claims

1. A memory module, characterized in that: include: A circuit board, a first functional unit and a second functional unit; The circuit board comprises a first layer board and a second layer board which are laminated and bonded together, the first functional unit is arranged on the first layer board, the second functional unit is arranged on the second layer board, and the first functional unit and the second functional unit at least partially overlap; Wherein, the interconnection structure for electrically connecting the first layer board and the second layer board is arranged outside the overlapping area, and the overlapping area is the area where the first functional unit and the second functional unit overlap.

2. The memory module according to claim 1, wherein: A first group of blind holes is provided in the first layer board, and the first functional units are interconnected in the first layer board through the first group of blind holes; A second group of blind holes is opened in the second layer board, and the second functional units are interconnected in the second layer board through the second group of blind holes.

3. The memory module according to claim 2, wherein: The first group of blind holes and the second group of blind holes are arranged in the overlapping area; The circuit board is provided with a through hole for electrically connecting the first layer board and the second layer board, and the through hole is located outside the overlapping area.

4. The memory module according to claim 1, wherein: The first functional unit is a power management chip, and the second functional unit is a register clock driver.

5. The memory module according to claim 4, wherein: The first functional unit further includes a high current routing and / or a low frequency switch signal routing corresponding to the power management chip; The second functional unit also includes a high-speed digital signal routing corresponding to the registered clock driver.

6. The memory module according to claim 4, wherein: Also includes: The serial detection hub is arranged on the first layer board and is electrically connected to the power management chip.

7. The memory module according to claim 4, wherein: Also includes: A serial detection hub, wherein a ferrite bead is connected in series at the power supply end of the serial detection hub.

8. The memory module according to claim 4, wherein: Also includes: A serial detection hub and a bus, a matching resistor is connected in series to a source end of the bus, and the source end is an end of the bus electrically connected to the serial detection hub.

9. The memory module according to claim 8, wherein: The resistance of the matching resistor is greater than 20 ohms and less than 50 ohms.

10. A module device, characterized in that: include: The memory module according to any one of claims 1 to 9.

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