Multi-path parallel semi-dynamic register circuit, chip and electronic equipment

Abstract

The utility model provides a multi-path parallel semi-dynamic register circuit, a chip and electronic equipment, and relates to the field of integrated circuit design. The multi-path parallel semi-dynamic register circuit comprises a plurality of data storage structures, wherein each data storage structure comprises at least one semi-dynamic register; the semi-dynamic register comprises a first dynamic latch structure and a second static latch structure; the first dynamic latch structure and the second static latch structure are in data connection; the first dynamic latch structure stores charges based on parasitic capacitance of an electrode node; the second static latch structure comprises a data transmission path and a feedback loop; the input end of the pulse clock circuit is connected with a clock source, and the output end of the pulse clock circuit is connected with the clock end of each semi-dynamic register. The multi-path parallel semi-dynamic register circuit has better effects on the occupied chip area and the data stability.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a multi-channel parallel semi-dynamic register circuit, chip and electronic device. Background Art

[0002] Currently, in a circuit using multiple registers, multiple registers are connected in parallel and controlled using the same clock to reduce the chip area occupied by the clock circuit that controls each register.

[0003] However, in a circuit with multiple registers connected in parallel, the registers will also occupy a large area or have problems with low data stability. For example, registers are divided into dynamic registers and static registers. If static registers are used in parallel, the chip area required for the static register structure is too large, making the overall circuit area larger. Dynamic registers have leakage problems. If multiple channels are connected in parallel, the data transmitted by the circuit may be lost due to leakage, affecting data stability. Utility Model Content

[0004] In view of this, the present application aims to provide a multi-channel parallel semi-dynamic register circuit, chip and electronic device, so that the circuit with multiple registers in parallel has better effects in terms of occupied chip area and data stability.

[0005] In a first aspect, an embodiment of the present application provides a multi-way parallel semi-dynamic register circuit, comprising: a plurality of data storage structures, each data storage structure comprising at least one semi-dynamic register; the semi-dynamic register comprising a first dynamic latch structure and a second static latch structure; a data connection between the first dynamic latch structure and the second static latch structure; the first dynamic latch structure stores charge based on the parasitic capacitance of the electrode node; the second static latch structure comprises a data transmission path and a feedback loop; a pulse clock circuit, the input end of which is connected to a clock source, and the output end is simultaneously connected to the clock end of each of the semi-dynamic registers.

[0006] In an embodiment of the present application, a multi-channel parallel semi-dynamic register circuit uses a plurality of semi-dynamic registers in parallel, and the semi-dynamic register includes a two-stage latch structure, which is a first dynamic latch structure and a second static latch structure. The first dynamic latch structure is a latch structure used by the dynamic register, which stores data based on the parasitic capacitance of the electrode node and has the characteristic of occupying a small area. The second static latch structure is a latch structure used by the static register, which includes a feedback loop, which can make data storage more stable. Therefore, compared with the static register, the semi-dynamic register will occupy a smaller area due to the existence of the first dynamic latch structure. Due to the second static latch structure, compared with the dynamic register, the data can be stably stored, reducing the time for the data to be affected by leakage, and improving the stability of data storage. As a result, the semi-dynamic register enables the data stability ability of the data storage structure and the occupied chip area to have a better effect. In addition, since the first dynamic latch structure and the second static latch structure are different types of latch structures, the control clock required is more complex, and each half of the dynamic register usually requires a corresponding clock circuit for control, which will also make the occupied area too large. In an embodiment of the present application, multiple data storage structures including semi-dynamic registers are connected in parallel and controlled by using the same pulse clock circuit output clock. This can reduce the control difficulty of different semi-dynamic registers, and reduce the number of clock circuits and the chip area occupied.

[0007] In one embodiment, the wiring distance between each of the data storage structures and the pulse clock circuit is less than a preset distance.

[0008] In some layout tools, the layout is usually performed based on the convenience of a certain part of the sequential logic, which makes some non-critical paths redundant or longer, affecting the routing distance between the data storage structure and the pulse clock circuit on these paths, and the routing distance affects the time when the clock signal is output to each data storage structure, thereby affecting the accuracy of the control of the data stored in each semi-dynamic register. In an embodiment of the present application, the routing distance between each of the data storage structures and the pulse clock circuit is made less than a preset distance, so as to reduce the excessive impact of the routing distance on the clock signal when the semi-dynamic registers of the multi-way data storage structure are connected in parallel, thereby improving the accuracy of the data stored in the multi-way parallel semi-dynamic register circuit.

[0009] In one embodiment, the data storage structures are evenly arranged at different positions in a target area, and the target area is an area where the data storage structures are arranged.

[0010] In an embodiment of the present application, various data storage structures are evenly arranged in the target area. On the one hand, it can facilitate circuit layout and routing. On the other hand, it can ensure that each data storage structure has a better distance from the pulse clock circuit, thereby reducing the impact of delay.

[0011] In one embodiment, the pulse clock circuit includes a pulse clock adjustment circuit, which is used to adjust the source clock signal output by the clock source to obtain a pulse clock signal; the pulse clock signal includes a first level and a second level; the first level is less than half of the signal period of the source clock signal and greater than the minimum pulse width condition for storing data in the first dynamic latch structure; the first level is used to make the electrode node of the first dynamic latch structure in a state of storing data; the second level is used to make the second static latch structure temporarily store data; the pulse clock adjustment circuit is also connected to the clock end of the first dynamic latch structure and the clock end of the second static latch structure, respectively, to output the pulse clock signal to the first dynamic latch structure and the second static latch structure.

[0012] In the embodiment of the present application, the source clock signal is adjusted by the pulse clock adjustment circuit module to obtain a pulse clock signal for controlling the semi-dynamic register to store data. The first level of the pulse clock signal is used to control the electrode node of the first dynamic latch structure to be in the state of storing data nodes, and because the time of the first level is less than half of the clock cycle and greater than the minimum pulse width condition for storing data in the first dynamic latch structure, that is, under the premise of satisfying the first dynamic latch structure to store data, the duration of the first level is reduced, so that the time for the first dynamic latch structure to store data is reduced, thereby reducing the influence of leakage on the data in the first dynamic latch structure, thereby reducing the influence of leakage on the stability of the stored data, which can further reduce the influence of leakage on data storage and improve the stability of data storage.

[0013] In one embodiment, the pulse clock adjustment circuit includes a pulse width modulation circuit; the pulse width modulation circuit is used to modulate the duty cycle of the first level in the source clock signal to obtain the pulse clock signal.

[0014] Pulse width modulation can adjust the duty cycle of the high level within a clock cycle. Therefore, in an embodiment of the present application, a pulse width modulation circuit can be set to modulate the duty cycle of the first level to obtain a pulse clock signal. This method is easy to implement and can effectively reduce circuit complexity.

[0015] In one embodiment, the pulse clock adjustment circuit includes: a cutting edge circuit; the cutting edge circuit is used to generate a cutting edge signal, and to perform logical processing on the source clock signal according to the cutting edge signal during the first level duration of the source clock signal, so as to generate a falling edge during the first level period of the source clock signal to obtain the pulse clock signal.

[0016] In the embodiment of the present application, the cutting edge circuit can perform logic processing on the source clock signal, generate a falling edge during the first level period of the source clock signal and maintain the low level unchanged until the next rising edge arrives, so that the duration of the first level in the pulse clock signal is shorter than the duration of the first level in the source clock signal. Compared with pulse width modulation, the pulse clock signal may change with transmission in a scenario with a large number of semi-dynamic register levels, and the pulse clock signal processed by the cutting edge circuit has better stability.

[0017] In one embodiment, the first dynamic latch structure includes a transmission gate; the transmission gate includes a first NMOS and a first PMOS; the gates of the first NMOS and the first PMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the sources of the first NMOS and the first PMOS are connected to the port of input data, and the drains of the first NMOS and the first PMOS are used to output data.

[0018] In the embodiment of the present application, the transmission gate can store data in the parasitic capacitance of the storage node, so the transmission gate can be configured in the first dynamic chip structure to store data. The transmission gate only needs two devices, the first NMOS and the first PMOS, to be implemented, which can effectively reduce the chip area occupied by the first dynamic latch structure.

[0019] In one embodiment, the second static latch structure includes a data transmission path and a feedback loop, the data transmission path includes a second PMOS, a third PMOS, a third NMOS, and a second NMOS; the source of the second PMOS is connected to a power supply, the drain of the second PMOS is connected to the source of the third PMOS, the drain of the third PMOS is connected to the drain of the third NMOS, the source of the third NMOS is connected to the drain of the second NMOS, and the source of the second NMOS is grounded; the gates of the second NMOS and the second NMOS are used to input data; the gates of the third PMOS and the third NMOS are respectively connected to different clock terminals, and the different clock terminals are used to output opposite clock signals; The feedback loop includes: a fifth PMOS, a sixth PMOS, a seventh PMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; the gates of the fifth NMOS and the fifth PMOS are connected to the drain of the third PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to a power supply; the source of the fifth NMOS is grounded; the drain of each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to a power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the third PMOS; the sixth PMOS and the third NMOS are connected to the same clock terminal; the sixth NMOS and the third PMOS are connected to the same clock terminal.

[0020] In the embodiment of the present application, the fifth PMOS, the sixth PMOS, the seventh PMOS, the fifth NMOS, the sixth NMOS, and the seventh NMOS are connected as above, and under the control of the clock, a feedback loop at the drain of the third NMOS can be formed to stably store data. Compared with the second stage, the dynamic latch structure is also used, because the static structure feedback loop can stably maintain the data, so that the leakage current is much smaller than the feedback current, which is almost negligible, so that the static structure almost does not have the problem of dynamic leakage data loss. Therefore, the second stage uses a static latch structure to reduce or even ignore the impact of leakage on the data storage of the second static latch structure, effectively reducing the possibility of data loss and improving the stability of data storage.

[0021] In a second aspect, an embodiment of the present application provides a chip comprising a multi-way parallel semi-dynamic register circuit as described in any one of the first aspect.

[0022] In one embodiment, in the multi-way parallel semi-dynamic register circuit, the number of the data storage structures matches the data bit width of the chip.

[0023] In the embodiment of the present application, the number of data storage structures matches the data bit width of the chip, so the multi-way parallel semi-dynamic register circuit can store a complete instruction of the chip, thereby improving the accuracy of the chip operation.

[0024] In a third aspect, an embodiment of the present application provides an electronic device, comprising the chip as described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of the structure of a multi-channel parallel semi-dynamic register circuit provided in one embodiment of the present application;

[0027] Figure 2 It is a schematic diagram of the structure of the existing static register and dynamic register;

[0028] Figure 3 A schematic diagram of a first latch structure provided in an embodiment of the present application;

[0029] Figure 4 A circuit diagram of a semi-dynamic register provided in one embodiment of the present application;

[0030] Figure 5 A circuit diagram of a multi-channel parallel semi-dynamic register circuit provided in an embodiment of the present application;

[0031] Figure 6 A schematic diagram of the layout of a multi-channel parallel semi-dynamic register circuit provided in one embodiment of the present application.

[0032] Icons: data storage structure 110; semi-dynamic register 111; pulse clock circuit 120. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present application more clear, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application and are not used to limit the present application.

[0034] See also Figure 1 , Figure 1The schematic diagram of the structure of a multi-channel parallel semi-dynamic register circuit provided in one embodiment of the present application is as follows: The multi-channel parallel semi-dynamic register circuit provided in one embodiment of the present application comprises a data storage structure 110 and a pulse clock circuit 120 .

[0035] In the multi-channel parallel semi-dynamic register circuit, a plurality of data storage structures 110 are included. Each data storage structure 110 includes at least one register. In the embodiment of the present application, the register used is a semi-dynamic register 111 .

[0036] In the embodiment of the present application, the semi-dynamic register 111 includes two-level latch structures, namely a first dynamic latch structure and a second static latch structure.

[0037] The first dynamic latch structure and the second static latch structure are data connected. Data connection means that the two are connected and data can be transmitted. In the embodiment of the present application, the first dynamic latch structure and the second static latch structure can be directly connected.

[0038] See also Figure 2 , Figure 2 The schematic diagram of the existing dynamic register and static register structure. The existing dynamic register includes a two-stage latch structure, wherein the transmission gate is the first-stage structure, the middle-stage three-state latch circuit is the second-stage structure, and the last-stage inverter circuit is the output stage. The two-stage latch structure constitutes two electrode nodes, and the charge is stored at the electrode nodes. The first electrode node is the output node of the transmission gate, that is, the connection between the transmission gate and the gate of the PMOS and NMOS of the second-stage structure. The parasitic capacitance is formed at the output node to store the charge, and the second electrode node is the output node of the three-state gate. The latch structure of the dynamic register has the characteristic of occupying a small chip area. Therefore, in the embodiment of the present application, the first dynamic latch structure can store charges based on the electrode nodes, thereby realizing data storage.

[0039] Accordingly, the first dynamic latch structure may include a transmission gate. Figure 3 , Figure 3 A schematic diagram of a transmission gate provided in an embodiment of the present application, wherein CKN and CKP are two clock terminals for transmitting opposite clock signals, the gate of the first NMOS is connected to CKN, the gate of the first PMOS is connected to CKP, and D is a port for inputting data. That is, the gates of the first NMOS and the first PMOS are the clock terminals of the transmission gate, which are used to connect to the pulse clock circuit 120.

[0040] As shown in Figure 3, the transmission gate includes a first NMOS and a first PMOS; the gates of the first NMOS and the first PMOS are respectively connected to different clock terminals, and the different clock terminals are used to output opposite clock signals; the source of the first NMOS and the first PMOS is connected to the port for inputting data, and the drain of the first NMOS and the first PMOS is used to output data. Among them, the drain of the first NMOS and the first PMOS is used to connect to a structure with parasitic capacitance.

[0041] The transmission gate has a state with a very high off-resistance, in which the transmission gate can act as a switch to store data on the parasitic capacitance formed by the electrode node, thereby storing the data on the parasitic capacitance at the electrode node S0 (ie, the drain of the first NMOS and the first PMOS).

[0042] Similarly, the tri-state gate has similar characteristics to the transmission gate. The tri-state gate has a high impedance state. In the high impedance state, the tri-state gate can also be used as a switch to store data on the parasitic capacitor at the output node of the tri-state gate. Therefore. In another embodiment of the present application, the first dynamic latch structure may also include a tri-state gate. The specific structure of the tri-state gate can refer to the prior art and will not be expanded here.

[0043] Please continue reading Figure 2 ,like Figure 2 The static register shown, the existing static register includes a two-level latch structure, each level of the latch structure includes a data transmission path and a feedback loop for data storage, the feedback loop can store data, so that the data storage has higher stability.

[0044] Regardless of whether the first dynamic latch structure is a tri-state gate or a transmission gate, compared to Figure 2 The static latch structure of the static register shown in the figure and the first dynamic latch structure occupy a smaller area. Among them, since the transmission gate uses fewer devices, the use of the transmission gate can further reduce the chip area compared to the tri-state gate. The above is only an example, and the first dynamic latch structure can also use a circuit with similar functions, which will not be expanded here.

[0045] However, since the dynamic latch structure of the dynamic register is susceptible to leakage, which may lead to data loss, in an embodiment of the present application, the other level latch structure of the register used can be set to a second static latch structure, in which a data transmission path and a feedback loop are provided to stably store data through the data transmission path and the feedback loop.

[0046] In the embodiment of the present application, the second static latch structure 120 may include two parts, namely a data transmission path and a feedback loop. Figure 4 , Figure 4A circuit diagram of a data storage structure 110 provided in one embodiment of the present application. P2 to P7 represent the second PMOS to the seventh PMOS, respectively, and N2 to N7 represent the second NMOS to the seventh NMOS, respectively. P2, P3, N3, and N2 constitute a data transmission path, and P5, P6, P7, N5, N6, and N7 constitute a feedback loop. Parasitic capacitance is formed at the gates of P2 and N2.

[0047] like Figure 4 As shown, in a feasible implementation, the data transmission path of the second static latch structure may include: the source of the second PMOS is connected to the power supply, the drain of the second PMOS is connected to the source of the third PMOS, the drain of the third PMOS is connected to the drain of the third NMOS, the source of the third NMOS is connected to the drain of the second NMOS, and the source of the second NMOS is grounded; the gates of the second NMOS and the second NMOS are used to input data;

[0048] The gates of the third PMOS and the third NMOS serve as clock terminals of the second static latch structure and are respectively connected to different clock terminals of the pulse clock circuit 120, and the different clock terminals of the pulse clock circuit 120 are used to output opposite clock signals;

[0049] The feedback loop includes: a fifth PMOS, a sixth PMOS, a seventh PMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; the gates of the fifth NMOS and the fifth PMOS are connected to the drain of the third PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to the power supply; the source of the fifth NMOS is grounded; each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the next device in sequence; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the third PMOS; the sixth PMOS and the third NMOS are connected to the same clock terminal; the sixth NMOS and the third PMOS are connected to the same clock terminal.

[0050] like Figure 4 As shown, data can be stored in the feedback loop, the connection between the output stage and the feedback loop is node S1, the time at the data S1 can be controlled by the clock signal, and the S1 node can output the data through P4 and N4 of the output stage circuit. Among them, P4 is the fourth PMOS, N4 is the fourth NMOS, the gates of P4 and N4 are connected to the node S1, the source of P4 is connected to the power supply, the drain of P4 is connected to the drain of N4, and the source of N4 is grounded.

[0051] by Figure 4As an example, the working state of the semi-dynamic register 111 is described. The first dynamic latch structure 110 temporarily stores data at a high level, and the second static latch structure 120 temporarily stores data at a low level.

[0052] Different clock signals include CKP and CKN. CKP is input to P1, P6, and N3 respectively, and CKN is input to N1, P3, and N6 respectively.

[0053] State 1: When the pulse clock signal is at a low level, CKP=0, CKN=1. At this time, P3 / N3 is closed, P5 / N5 / P6 / N6 / P7 / N7 forms a feedback loop to the S1 node to lock the data, and the output Q is stable. At this time, P1 / N1 is turned on, and the input D is directly transmitted to the S0 node through N1 / P1.

[0054] State 2: When the rising edge of the pulse clock signal arrives, CKP rises from 0 to 1, CKN falls from 1 to 0, N1 / P1 is closed, S0 is floating, and the data is temporarily stored by the P2 / N2 gate capacitance of the first dynamic latch structure 110 and the parasitic capacitance at the S0 node; P3 / N3 is turned on, P6 / N6 is closed, and the data originally stored in the S0 node is directly transmitted to S1, and then transmitted to the output Q through P4 / N4.

[0055] State 3: When the pulse clock signal is at a high level, CKP=1, CKN=0. At this time, the S0 node holds data by parasitic capacitance.

[0056] State 4: When the falling edge of the pulse clock signal arrives, CKN rises from 0 to 1, CKP falls from 1 to 0, N1 / P1 is turned on, and data is directly transmitted to the S0 node through N1 / P1 after being input from D. Since P3 / N3 is closed, P6 / N6 is turned on, P5 / N5 / P6 / N6 / P7 / N7 forms a feedback loop to the S1 node, the data is locked at the node S1, and the output terminal Q is stable. After stabilization, it enters state 1.

[0057] The pulse clock circuit 120 has an input end connected to a clock source, and an output end connected to a clock end of each semi-dynamic register 111 at the same time.

[0058] In this embodiment, the pulse clock circuit 120 is used to adjust the source clock signal output by the clock source to a signal for controlling the semi-dynamic register 111. Figure 5 For example, the clock end of the semi-dynamic register 111 is an end connected to CKP and CKN, and CKP and CKN are used to input opposite clock signals. Therefore, the pulse clock circuit 120 can be connected to the CKP and CKN ports of the semi-dynamic register 111, adjust the source clock signal into two opposite signals and output them to both ends of CKP and CKN respectively to control the operation of the semi-dynamic register 111.

[0059] In the embodiment of the present application, multi-way parallel connection refers to the parallel connection of the clock terminals of the semi-dynamic register 111, such as Figure 1 and Figure 5 As shown, the clock end of each data storage structure 110 is connected to the same pulse clock circuit 120, specifically, the clock end of each semi-dynamic register 111 is connected to the same pulse clock circuit 120. Different circuits can be connected between the data input ends of each data storage structure 110, which is not limited here.

[0060] Compared with the method of using a clock circuit to control each half-dynamic register 111, in the embodiment of the present application, the clock ends of different semi-dynamic registers 111 are simultaneously connected to a pulse clock circuit 120, which can effectively reduce the power consumption and chip area occupied by the clock circuit. For example, if five semi-dynamic registers 111 are originally set in the chip, five clock circuits are required, and the five clock circuits work separately and occupy a certain chip area. However, through multi-way parallel connection, only one pulse clock circuit 120 is required, and the power consumption and chip area occupied are greatly reduced.

[0061] In addition, due to the reduction of clock circuits, the routing of each circuit is also reduced, and the routing length and power consumption caused by metal wires can be effectively reduced. Although this method reduces the occupied chip area and power consumption, different semi-dynamic registers 111 are set at different positions, and the distances from each semi-dynamic register 111 to the pulse clock circuit 120 are different, which may affect the delay of the pulse clock signal, so that each semi-dynamic register 111 cannot be accurately controlled. Therefore, in the embodiment of the present application, it is necessary to pre-plan the positions of the pulse clock circuit 120 and each data storage structure 110 on the chip.

[0062] In one embodiment, the wiring distance between each data storage structure 110 and the pulse clock circuit 120 can be made smaller than a preset distance.

[0063] In this embodiment, by limiting the wiring distance, the influence of the delay of the signal transmission path on the clock signal can be effectively reduced, so that the pulse clock signal output by the pulse clock circuit 120 can accurately control the storage and output data of each semi-dynamic register 111.

[0064] At present, some tools are usually used to layout the positions of each data storage structure 110. The positions placed by such tools are the optimal solutions for some critical paths, but will cause additional overhead for non-critical paths, and even make the delay of the pulse clock signal output to each semi-dynamic register 111 not meet the requirements due to uneven routing distances. Figure 6As shown in a, multiple data storage structures 110 are set on the same data path, and the tool may arrange the data storage structures 110 in the manner shown in a.

[0065] Therefore, in some embodiments of the present application, when setting a target area for each data storage structure 110 , the data storage structures 110 may be evenly arranged at different positions in the target area.

[0066] The data storage structure 110 can be regarded as a whole, and arranged regularly and neatly in the target area. If the data ends of multiple data storage structures 110 are connected in series, they can be arranged according to the flow of data. Figure 6 Taking b as an example, according to the data flow direction, the first four are arranged in one row, and the other three are arranged in another row, neatly and regularly arranged in the target area.

[0067] Compared with the layout made by the tool, by evenly arranging the data storage structures 110 in the target area, on the one hand, the planning of each structure can be more orderly, which is convenient for layout and routing. On the other hand, each data storage structure 110 can have a better path (not necessarily the best path) to the pulse clock circuit 120.

[0068] In the semi-dynamic register 111, the first dynamic latch structure may still be affected by leakage, and the longer the data stored in the first dynamic latch structure is affected by leakage, the greater the possibility of data loss and the amount of data lost. Therefore, in one embodiment of the present application, the pulse clock circuit 120 includes a pulse clock adjustment circuit, which is used to adjust the source clock signal output by the clock source to obtain a pulse clock signal; the pulse clock signal includes a first level and a second level; the first level is less than half of the signal period of the source clock signal and is greater than the minimum pulse width condition for storing data in the first dynamic latch structure. The pulse clock adjustment circuit is also connected to the clock end of the first dynamic latch structure and the clock end of the second static latch structure, respectively, to output the adjusted pulse clock signal to the first dynamic latch structure and the second static latch structure.

[0069] In this embodiment, the first level is used to make the electrode node of the first dynamic latch structure in a state of storing data; the second level is used to make the second static latch structure temporarily store data. For example, if the first dynamic latch structure stores data at a high level, the first level is a high level, and the second level is a low level. If the first dynamic latch structure stores data at a low level, the first level is a low level, and the second level is a high level. The level used by the semi-dynamic register 111 to store data can be changed according to the adjustment of the device in the circuit. The above is only an example and will not be repeated here.

[0070] In a conventional static register or a dynamic register, usually the high level and the low level each account for half, but in this embodiment, the first level is less than half of the signal period of the source clock signal, and is greater than the minimum pulse width condition for storing data in the first dynamic latch structure, that is, under the premise that the first dynamic latch structure stores data normally, the time of the high and low levels is not equal, and the time of controlling the first dynamic latch structure is short, for example, if the high level controls the first dynamic latch structure, the time of the high level is shorter than the time of the low level. Therefore, under the premise that the total time for storing data in the semi-dynamic register 111 remains unchanged, the time for storing data in the first dynamic latch structure is reduced, the influence of leakage on the stability of data storage is reduced, and the stability of data storage is further improved.

[0071] For the second static latch structure, since the low level time is prolonged, the time for saving data through the second static latch structure is prolonged, and the stability of data saving of the second static latch structure is higher, therefore, the time for saving data of the second static latch structure can be prolonged to improve the stability of data saving. The time for saving data between the first dynamic latch structure and the second static latch structure increases and decreases, which effectively improves the stability of data saving.

[0072] There are many ways to adjust the pulse clock signal. For example:

[0073] In one embodiment, the pulse clock adjustment circuit module may include a pulse width modulation circuit; the pulse width modulation circuit is used to modulate the duty cycle of the first level in the source clock signal to obtain a pulse clock signal.

[0074] PWM (Pulse width modulation) can adjust the duty cycle of the high level in the pulse signal. By adjusting the duty cycle, the time proportion of the high level in a single clock cycle can be achieved. Therefore, a pulse width modulation circuit can be configured in the pulse clock adjustment circuit module 200 to achieve the duty cycle adjustment of the first level and obtain the required pulse clock signal. The pulse width modulation circuit can refer to the prior art and will not be expanded here.

[0075] In another embodiment, the pulse clock adjustment circuit module 200 includes: an edge cutting circuit, which can also be called a signal jump circuit. The edge cutting circuit is used to generate an edge cutting signal, and perform logic processing on the source clock signal according to the edge cutting signal during the first level duration of the source clock signal, so as to generate a falling edge during the first level period of the source clock signal, and keep the low level unchanged until the next rising edge arrives, so as to obtain a pulse clock signal.

[0076] In this embodiment, the cutting edge circuit is mainly used to perform logic processing on the source clock signal to reduce the duration of the first level. For example, the cutting edge circuit generates a cutting edge signal by creating an additional delay path, and then the cutting edge signal and the source clock signal are logically processed. The logic processing can be 1 if the cutting edge signal and the source clock signal are both high levels, otherwise 0, thereby obtaining an adjusted pulse clock signal. For example, assuming that the source clock source signal is 11001100, it becomes 01100110 after delay, and the logic processing becomes 01000100, and the corresponding pulse signal is obtained in a similar manner.

[0077] The specific principles and implementation structures of the pulse width modulation circuit and the edge cutting circuit can refer to the prior art. The above is only an example and should not be a limitation to the present application.

[0078] The pulse clock signal adjusted by the pulse clock adjustment circuit is more complex and consumes more power than a conventional clock signal. By connecting the clock ends of multiple semi-dynamic registers 111 in parallel with the pulse clock circuit 120, the complexity of controlling multiple semi-dynamic registers 111 can be effectively reduced, and power consumption can be reduced.

[0079] Based on the same inventive concept, an embodiment of the present application further provides a chip, which may include the multi-channel parallel semi-dynamic register circuit provided by any of the above embodiments.

[0080] In the embodiments of the present application, the chip may be a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), a data processing core of AI (Artificial Intelligence), etc., or a processor chip applied to some large-scale data computing scenarios. The above is only an example and should not be a limitation to the present application.

[0081] In one embodiment of the present application, in the multi-way parallel semi-dynamic register circuit, the number of data storage structures 110 matches the data bit width of the processor chip.

[0082] The amount of data that can be stored in a semi-dynamic register 111 of a data storage structure 110 is 1 bit, and if the number of data storage structures 110 matches the data bit width of the processor chip, then the multi-way parallel semi-dynamic register circuit can completely store an instruction of the processor chip, thereby improving the accuracy of the output of the processor chip instructions. For example, if the data bit width of the processor chip is 32 bits, then the number of data storage structures 110 is 32.

[0083] Based on the same inventive concept, the present application may also provide an electronic device, which may include the chip provided in the above embodiment. The electronic device may be a computer, a server or other device with a processing core.

[0084] The technical features of the above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.

[0085] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0086] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such articles or devices. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the article or device including the element.

Claims

1. A multi-channel parallel semi-dynamic register circuit, characterized in that: include: A plurality of data storage structures, each data storage structure comprising at least one semi-dynamic register; the semi-dynamic register comprising a first dynamic latch structure and a second static latch structure; The first dynamic latch structure and the second static latch structure are data connected; the first dynamic latch structure stores charge based on the parasitic capacitance at the electrode node; The second static latch structure includes a data transmission path and a feedback loop; The pulse clock circuit has an input end connected to a clock source and an output end connected to a clock end of each of the semi-dynamic registers.

2. The multi-channel parallel semi-dynamic register circuit according to claim 1, characterized in that: The wiring distance between each of the data storage structures and the pulse clock circuit is less than a preset distance.

3. The multi-channel parallel semi-dynamic register circuit according to claim 2, characterized in that: The data storage structures are evenly arranged at different positions in a target area, and the target area is an area where the data storage structures are arranged.

4. The multi-channel parallel semi-dynamic register circuit according to claim 1, characterized in that: The pulse clock circuit comprises a pulse clock adjustment circuit, and the pulse clock adjustment circuit is used to adjust the source clock signal output by the clock source to obtain a pulse clock signal; The pulse clock signal includes a first level and a second level; the first level is less than half of the signal period of the source clock signal and greater than the minimum pulse width condition for storing data in the first dynamic latch structure; The first level is used to make the electrode node of the first dynamic latch structure in a state of storing data; The second level is used to make the second static latch structure temporarily store data; The pulse clock adjustment circuit is also connected to the clock end of the first dynamic latch structure and the clock end of the second static latch structure respectively, so as to output the pulse clock signal to the first dynamic latch structure and the second static latch structure.

5. The multi-channel parallel semi-dynamic register circuit according to claim 4, characterized in that: The pulse clock adjustment circuit includes a pulse width modulation circuit; The pulse width modulation circuit is used to modulate the duty cycle of the first level in the source clock signal to obtain the pulse clock signal.

6. The multi-channel parallel semi-dynamic register circuit according to claim 4, characterized in that: The pulse clock adjustment circuit comprises: an edge cutting circuit; The cutting edge circuit is used to generate a cutting edge signal, and perform logic processing on the source clock signal according to the cutting edge signal during the first level duration of the source clock signal to generate a falling edge during the first level period of the source clock signal to obtain the pulse clock signal.

7. The multi-channel parallel semi-dynamic register circuit according to any one of claims 1 to 6, characterized in that: The first dynamic latch structure includes a transmission gate; the transmission gate includes a first NMOS and a first PMOS; the gates of the first NMOS and the first PMOS are respectively connected to different clock ends, and the different clock ends are used to output opposite clock signals; the sources of the first NMOS and the first PMOS are connected to the port of input data, and the drains of the first NMOS and the first PMOS are used to output data.

8. The multi-channel parallel semi-dynamic register circuit according to any one of claims 1 to 6, characterized in that: The second static latch structure includes a data transmission path and a feedback loop, wherein the data transmission path includes a second PMOS, a third PMOS, a third NMOS, and a second NMOS; The source of the second PMOS is connected to a power supply, the drain of the second PMOS is connected to the source of the third PMOS, the drain of the third PMOS is connected to the drain of the third NMOS, the source of the third NMOS is connected to the drain of the second NMOS, and the source of the second NMOS is grounded; the gates of the second NMOS and the second NMOS are used to input data; The gates of the third PMOS and the third NMOS are respectively connected to different clock terminals, and the different clock terminals are used to output opposite clock signals; The feedback loop includes: a fifth PMOS, a sixth PMOS, a seventh PMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; The gates of the fifth NMOS and the fifth PMOS are connected to the drain of the third PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth PMOS is connected to a power supply; and the source of the fifth NMOS is grounded; The drain of each device in the sixth PMOS, the seventh PMOS, the seventh NMOS and the sixth NMOS is connected to the source of the next device; the source of the sixth PMOS is connected to the power supply; the source of the sixth NMOS is grounded; the drain of the seventh PMOS and the drain of the seventh NMOS are connected to the drain of the third PMOS; The sixth PMOS and the third NMOS are connected to the same clock terminal; the sixth NMOS and the third PMOS are connected to the same clock terminal.

9. A chip, characterized in that: include: A multi-channel parallel semi-dynamic register circuit as described in any one of claims 1 to 8.

10. The chip according to claim 9, characterized in that: In the multi-way parallel semi-dynamic register circuit, the number of the data storage structures matches the data bit width of the chip.

11. An electronic device, characterized in that: include: A chip as claimed in claim 9 or 10.

Images