Circuit and EEPROM

Abstract

The utility model relates to a circuit and an EEPROM. Disclosed herein is a circuit comprising a detector circuit comprising: a first detector configured to receive an input signal and generate a first detector output signal indicating that the input signal has reached a first activation threshold; and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicating that the input signal has reached a second activation threshold. The logic circuit is configured to perform a logical operation on the first detector output signal and the second detector output signal to generate an output indicating that the input signal has reached a voltage equal to the second activation threshold.

Description

Technical Field

[0001] The present disclosure relates to the field of threshold detector circuits, the effects of MOS transistor aging on those threshold detector circuits, and techniques for protecting threshold circuits from the effects of MOS transistor aging. Background Art

[0002] Metal oxide semiconductor field effect transistors (MOS transistors) are common components of integrated circuits (ICs) and are therefore widely used. While MOS transistors are widely used due to their versatility and practicality, they are not without problems, such as aging. Aging refers to the gradual degradation of the electrical properties of MOS transistors over time, resulting in a loss of performance and can cause circuits formed by MOS transistors to not function as expected.

[0003] The aging of MOS transistors is mainly caused by four mechanisms, namely, hot carrier injection (HCI), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB).

[0004] HCI occurs when high energy charge carriers (electrons or holes) are generated in the channel of a transistor due to a high electric field. These carriers can overcome the energy barrier and become injected into the gate oxide, resulting in the formation of interface traps and oxide charge capture. HCI is particularly problematic in short channel transistors where the electric field is more significant and when the gate voltage (VG) approaches half the drain voltage (VD / 2). The effects caused by HCI include threshold voltage shift, reduced transconductance, and increased leakage current.

[0005] NBTI is a degradation mechanism that primarily affects p-channel MOS transistors. It occurs when the transistor is subjected to negative gate-source voltage (Vgs) and elevated temperature. Under these conditions, hydrogen is released from the silicon dioxide (SiO2) layer, forming interface traps and oxide charge trapping. The effects of NBTI include threshold voltage shift (e.g., threshold voltage increase, resulting in reduced drain current), reduced transconductance, and increased leakage current (similar to HCI).

[0006] PBTI is a degradation mechanism that affects n-channel MOS transistors. It occurs when the transistor is subjected to very positive gate-source voltages (VGS) and elevated temperatures. Like NBTI, PBTI involves the release of hydrogen from the silicon dioxide (SiO2) layer, resulting in interface traps and oxide charge trapping. The effects of PBTI include threshold voltage shifts, reduced transconductance, and increased leakage current.

[0007] TDDB refers to the gradual degradation of the gate oxide in MOS transistors due to the presence of high electric fields and increased temperature. Over time, the gate oxide can weaken, leading to the formation of a conduction path and ultimately dielectric breakdown. The effects of TDDB include increased gate leakage current, threshold voltage shift, and reduced transconductance.

[0008] EEPROM (Electrically Erasable Programmable Read-Only Memory) devices are particularly susceptible to the negative effects of MOS transistor aging. These memory devices are typically specified to operate over a wide power supply (Vdd) range, typically between 1.6V and 5.5V. At the upper end of this range (5.5V), the MOS transistors may experience accelerated aging, while at the lower end of this range (1.6V), higher drifts in drain current levels may occur. These aging effects can cause chip drift and, in the worst case, cause the EEPROM device to not function properly.

[0009] Among the aging mechanisms, NBTI is identified as the most concerning issue for EEPROM devices, especially for p-channel MOS transistors. For example, after operating for 1000 hours at a gate-source voltage (VGS) of -6V, the threshold voltage (Vt) of a p-channel MOS transistor can increase from -0.8V to -1.0V, which significantly affects the performance and reliability of EEPROM memory.

[0010] Timer circuits are also susceptible to the negative effects of MOS transistor aging. Such timer circuits are generally based on the charging time of a capacitor. The capacitor is charged at a certain rate, and the detection of the end of charging determines the elapsed time. However, aging can affect the threshold for the detection of the end of charging, which can cause the timer operation to be inaccurate.

[0011] Referring now to Figure 1, there is shown a prior art detector 10 for detecting the end of charging of a capacitor in a timer circuit. The input IN to the detector 10 is the charge across the capacitor, and the output OUT of the detector is asserted once the input IN crosses the detection threshold of the detector 10. The "set point" of the timer circuit is a predetermined voltage threshold to which the capacitor is charged, at which the detector 10 is intended to assert its output, indicating the end of the charging process, and the time it takes for the capacitor to charge from its initial voltage to the set point determines the time interval that the timer circuit is intended to measure.

[0012] Before detrimental aging of one or more MOS transistors in detector 10 occurs, detector 10 operates as intended and switches near the set point (i.e., its activation threshold is close to the set point), which means that it accurately detects when the capacitor in the timer circuit reaches the predetermined voltage threshold. This can be seen in the diagram showing the operation of detector 10 before MOS transistor aging. Figure 2A-2BObserving in FIG. 1 , it can be seen that the detector activation threshold is close to or substantially at the set point. However, after one or more MOS transistors in the detector 10 have aged in this way, the detector 10 may now switch below the set point. This can be seen in FIG. 1 , which shows the operation of the detector 10 after MOS transistor aging. Figure 3A-3B , where it can be seen that the detector activation threshold is well below the set point. As a result, the output OUT is asserted before the input IN (the voltage across the capacitor) reaches the set point, which means that the measured time interval is now shorter than expected.

[0013] One way to mitigate the negative effects of aging of MOS transistors in a timer circuit is to limit the supply voltage of the timer circuit to a value where the effects of aging are reduced. This limitation can help minimize the aging of the MOS transistor(s) used to charge the capacitor in the timer. However, as described, while a lower supply voltage causes the MOS transistor to age more slowly, the effects of this aging (once aging occurs) are more pronounced at a lower supply voltage.

[0014] Another approach is to design the timer circuit to pair a capacitor charged at a constant current with a stable end-of-charge voltage detection mechanism to help maintain consistent timer operation. However, this has several disadvantages, including the fact that the constant current charging and stable voltage detection systems draw standby current, which can affect the overall power efficiency of the device, and can be complex and area-intensive to implement. Also, this approach does not guarantee that truly age-stable voltage detection is achieved. Aging-related fluctuations in the detection threshold may still occur, potentially affecting the performance and reliability of the timer over time.

[0015] In some applications, EEPROM is used to store data that is to be accessed, modified, or updated at specific intervals or under specific conditions. Timers can be used to control these processes by specifying that an appropriate amount of time has passed before initiating the next read, write, or erase operation. For example, a timer can be used to control the timing of an EEPROM write cycle, thereby providing a minimum amount of time required to elapse before attempting a write operation.

[0016] Since both EEPROM and timers are susceptible to MOS transistor aging, the performance and reliability of these components can be linked. Thus, aging-induced MOS transistor degradation may affect not only the direct operation of the EEPROM, but also the accurate operation of the timer responsible for controlling its access and modification.

[0017] Considering that the above-mentioned known solutions for addressing MOS transistor aging in timer circuits are insufficient for the reasons stated, further developments are needed with the aim of producing timer circuits that are not affected by MOS transistor aging. Utility Model Content

[0018] A circuit is disclosed herein, including a detector circuit, comprising: a first detector configured to receive an input signal and generate a first detector output signal indicating that the input signal has reached a first activation threshold; and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicating that the input signal has reached a second activation threshold. A logic circuit is configured to perform a logic operation on the first and second detector output signals to generate an output indicating that the input signal has reached a voltage equal to the second activation threshold.

[0019] Due to aging of at least one MOS transistor in the first detector, the second activation threshold may be greater than the first activation threshold.

[0020] The voltage equal to the second activation threshold may be a desired voltage level across the capacitor of the timer.

[0021] The logic circuit may be an AND gate configured to perform a logical AND operation on the first and second detector output signals to assert an output indicating that the input signal has reached a voltage equal to the second activation threshold.

[0022] An EEPROM is provided herein, comprising: a timer configured to charge and discharge a capacitor to time operation; and a detector circuit as described above, wherein the voltage across the capacitor is an input signal received by a first detector and a second detector of the detector circuit.

[0023] The timing circuit may be configured to charge the capacitor in response to assertion of the input signal. In this case, the detector circuit may further include an aging mitigation circuit, wherein the input of the first inverter is connected to receive the first detector output and provide the first inverter output. The aging mitigation circuit may include a second detector, wherein the second detector includes a first p-channel transistor and a first n-channel transistor, the first p-channel transistor having a source and a body connected to receive the first inverter output, a drain connected to the first tap node, and a gate connected to receive a voltage on the capacitor, the first n-channel transistor having a drain connected to the first tap node, a source connected to ground, and a gate connected to receive a reference voltage. The aging mitigation circuit may further include a second p-channel transistor and a second n-channel transistor, the second p-channel transistor having a source connected to a supply voltage, a drain connected to the second tap node, and a gate connected to receive the first inverter output, the second n-channel transistor having a drain connected to the second tap node, a source connected to ground, and a gate connected to receive a reference voltage. The logic circuit may perform a logic operation on the first and second detector outputs by receiving inputs from the first and second tap nodes and generating an output signal and discharging the capacitor based thereon.

[0024] The first detector may include a third p-channel transistor having a source connected to the supply voltage, a drain connected to the third tap node, and a gate connected to receive the voltage on the capacitor, and a third n-channel transistor having a drain connected to the third tap node, a source connected to ground, and a gate connected to receive the reference voltage.

[0025] The first inverter may have its input connected to the third tap node and its output connected to the gate of the second p-channel transistor.

[0026] The logic circuit may include an OR gate, a first NAND gate, and a second NAND gate, the OR gate having a first input terminal connected to the second tap node, a second input terminal connected to the first tap node, and an output terminal, the first NAND gate having a first input terminal connected to the output terminal of the OR gate, a second input terminal connected to the pre-output node, and an output terminal, the second NAND gate having a first input terminal connected to the output terminal of the first NAND gate, a second input terminal connected to receive an input signal, and an output terminal connected to the pre-output node.

[0027] The logic circuit may further include a third NAND gate having a first input terminal connected to receive the input signal, a second input terminal connected to the pre-output node, and an output terminal connected to the timing circuit.

[0028] The timing circuit may be configured to charge the capacitor in response to assertion of the input signal. In this case, the detector circuit may also include an aging mitigation circuit having an inverter circuit and a second detector, the inverter circuit having its input connected to receive the first detector output and providing the first inverter output. The second detector may include a first p-channel transistor and a first n-channel transistor, the first p-channel transistor having a source and a body connected to receive the first inverter output, a drain connected to the first tap node, and a gate connected to receive the voltage on the capacitor, the first n-channel transistor having a drain connected to the first tap node, a source connected to ground, and a gate connected to receive a reference voltage. The aging mitigation circuit may also include a second p-channel transistor having a source connected to a supply voltage, a drain connected to the first tap node, and a gate connected to receive the first inverter output. The logic circuit may perform a logic operation on the first and second detector outputs by receiving an input from the first tap node and generating an output signal and discharging the capacitor based thereon.

[0029] The first detector may include a third p-channel transistor having a source connected to the supply voltage, a drain connected to the second tap node, and a gate connected to receive the voltage on the capacitor, and a third n-channel transistor having a drain connected to the second tap node, a source connected to ground, and a gate connected to receive the reference voltage.

[0030] The inverter circuit may include a series of cascaded inverters connected between the second tap node and the gate of the second p-channel transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 is a block diagram of a known detector for detecting the end of charging of a capacitor in a timer circuit.

[0032] Figure 2A-2B is a graph of the input and output of the detector of FIG. 1 during operation, before one or more MOS transistors in the detector age.

[0033] Figure 3A-3B is a graph of the input and output of the detector of FIG. 1 during operation after aging of one or more MOS transistors in the detector.

[0034] Figure 4A is a block diagram of the EEPROM disclosed in this article.

[0035] Figure 4B yes Figure 4A Block diagram of the EEPROM timer detector circuit.

[0036] Figure 5A-Figure 5BBefore one or more MOS transistors in the first detector age Figure 4B Graph of the input and output of the first detector during operation.

[0037] Figure 5C Before one or more MOS transistors in the first detector age Figure 4B A graph of the stress level of the detector during operation.

[0038] Figure 5D Before one or more MOS transistors in the first detector age Figure 4B A graph of the activity of the detector during operation.

[0039] Figure 6A-6B After aging of one or more MOS transistors in the first detector Figure 4B Graph of the input and output of the first detector during operation.

[0040] Figure 6C After aging of one or more MOS transistors in the first detector Figure 4B A graph of the stress level of the detector during operation.

[0041] Fig.6D After aging of one or more MOS transistors in the first detector Figure 4B A graph of the activity of the detector during operation.

[0042] Figure 7 is a schematic diagram of the timer and associated detector circuits disclosed herein.

[0043] Figure 8 It is shown by Figure 7 A graph of the delay produced by a timer and detector circuit.

[0044] Fig. 9 is a schematic diagram of a timer and associated detector circuit disclosed herein for mitigating the effects of MOS transistor aging.

[0045] Fig.10 It is shown Fig. 9 A graph of the voltage of a node during operation.

[0046] Fig.11 is a schematic diagram of another timer and associated detector circuit disclosed herein for mitigating the effects of MOS transistor aging.

[0047] Fig.12 It is shown Fig.11 A graph of the voltage of a node during operation. DETAILED DESCRIPTION

[0048] The following disclosure enables those skilled in the art to make and use the subject matter described herein. Without departing from the spirit and scope of the present disclosure, the general principles outlined in the present disclosure may be applied to embodiments and applications other than those described in detail above. It is not intended to limit the present disclosure to the embodiments shown, but rather to give it the widest scope consistent with the principles and features disclosed or suggested herein.

[0049] Note that in the following description, unless otherwise specified, any resistor or resistance mentioned is a discrete device, not just an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between those two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise specified, any capacitor or capacitance mentioned is a discrete device, and, unless otherwise specified, is not a parasitic element. Furthermore, unless otherwise specified, any inductor or inductance mentioned is a discrete device, and, unless otherwise specified, is not a parasitic element.

[0050] The present disclosure focuses on mitigating the negative effects of MOS transistor aging, such as that caused by NBTI, on timers responsible for determining parameters in electronic systems, such as those involving EEPROMs. These parameters may include I2C filter time constants and write cycle times. By addressing drift caused by NBTI aging in the timer circuits, consistent and reliable operation of EEPROMs utilizing these timers may be provided.

[0051] Reference now Figure 4A Described is an EEPROM 18 that includes a timer 19 with a detector circuit 20 that mitigates the negative effects of MOS transistor aging such that when (or close to when) the input IN becomes equal to a desired voltage level across a capacitor C of the timer 19, the output OUT of the detector circuit 20 is asserted.

[0052] like Figure 4B As shown in , the detector circuit 20 includes a first detector 21 and a second detector 22. The first detector 21 receives an input signal IN representing a voltage across a capacitor C of a timer 19 in which the detector circuit 20 is incorporated, and generates a first detector output DET1OUT when the input signal IN reaches an activation threshold of the first detector 21. The second detector 22 also receives the input signal IN as an input, and when enabled (e.g., powered on), generates a second detector output DET2OUT when the input signal IN reaches an activation threshold of the second detector 22. A combinational logic circuit 40 (e.g., AND gate AND1) performs a logic operation (e.g., logical AND) on DET1OUT and DET2OUT to generate an output OUT.

[0053] In particular, it is observed that while the first detector 21 is set to be always enabled (e.g., powered) during operation, the second detector 22 is enabled by DET1OUT. Therefore, the second detector 22 is only enabled (e.g., powered) when DET1OUT is asserted (i.e., only enabled when the input IN reaches the activation threshold of the first detector 21).

[0054] like Figure 5A-Figure 5B As shown in , before one or more transistors in the first detector 21 age, both the first detector 21 and the second detector 22 switch near the set point of the timer 19 in which the detector circuit 20 is incorporated, so that the output OUT is asserted when the input IN reaches the desired voltage level across the capacitor C of the timer 19. Assuming that the stress experienced by the MOS transistors in the first detector 21 or the second detector 22 (which causes aging) increases with the difference between the input IN and the set point, it may follow an exponential curve, such as Figure 5C This means that the closer the input IN is to the set point, the lower the stress experienced by the first detector 21 and the second detector 22. However, as explained above, the second detector 22 is only enabled (e.g., powered on) when DET1OUT is asserted, which occurs when the input IN reaches the activation threshold of the first detector 21, such as Figure 5D . This allows the second detector 22 to remain disabled and unstressed until the input IN meets the set point. Therefore, the stress experienced by the second detector 22 is negligible compared to the stress experienced by the first detector 21 because it is enabled (e.g., powered on) for a shorter time and operates in the domain where the input IN is close to the set point.

[0055] The overall switching behavior of the output OUT of the detector circuit 20 is determined by the logical combination of the first detector 21 and the second detector 22. Since the output OUT is asserted only when both the first detector 21 and the second detector 22 are asserted, and since the enabling of the second detector 22 occurs only when DET1OUT is asserted to isolate the second detector 22 from the stresses (and consequent aging) experienced by the first detector 21, the detector 20 maintains accurate and consistent operation even as the MOS transistors within the first detector 21 age.

[0056] exist Figure 6A-6D This correct operation can be observed in FIG. 1 when one or more MOS transistors in the first detector 21 experience detrimental aging. For example, Fig. 6A In the figure, the activation threshold of the first detector 21 is lower than the set point during aging, while Figure 6BWhat is shown in FIG. 1 is that although DET1OUT is asserted before IN reaches the set point, OUT is not asserted until IN reaches the set point. As explained previously, and as Figure 6C This is due to the fact that the second detector 22 is only subject to low stress for a short period of time, since DETOUT2 is only enabled when the input IN reaches the activation threshold of the first detector 21.

[0057] To further summarize, this method can be applied to any threshold detector, thereby exceeding the scope of detection of charge in a capacitor to include voltage or current detection thresholds, as well as other applications (e.g., circuit reset or circuit enable operations that depend on voltage measurement and / or comparison operations). In such cases, the threshold detector emits a signal when the threshold is crossed. However, when the measured physical value is significantly lower than the threshold, the detector element may suffer from transistor aging. This aging therefore reduces the detection threshold of the detection element. In order to overcome this problem, a second detector similar to or identical to the first detector is added to the system. As long as the first detector does not detect the threshold, this second detector remains disabled, thereby preventing it from aging. Once the first detector detects the threshold, the second detector is enabled (e.g., powered on) but does not age because the measured physical value is close to the threshold. When both detectors detect the threshold, a signal is finally emitted, thereby ensuring accurate detection and extending service life.

[0058] The benefits of this detector circuit design are numerous. By mitigating the negative effects of MOS transistor aging on the detector circuit 20, the EEPROM parameters controlled by the timer incorporating the detector circuit 20, such as the I2C filter time constant and write cycle time, remain consistent and reliable throughout the life of the electronic device incorporating the EEPROM. This enhances the overall performance, reliability and useful life of the device, reducing the likelihood of failure, data corruption or other adverse effects.

[0059] Now consider Figure 7 The timer 19' and the detector circuit 20'.

[0060] The timer 19' includes a diode-coupled n-channel transistor N1 connected between the drain of a p-channel transistor P3 and ground, the source of P3 being connected to the supply voltage and the gate of P3 being connected to the node A1. The p-channel transistor P1 has its source connected to the supply voltage, its drain connected to the node A1 and its gate connected to the node A1. The resistor R is connected between the nodes A1 and A11. The n-channel transistor N4 has its drain connected to the node A11, its source connected to the ground and its gate connected to the node A10. The p-channel transistor P2 has its source connected to the supply voltage, its drain connected to the node A2 and its gate connected to the node A1. The n-channel transistor N2 has its drain connected to the drain of P2, its source connected to the ground and its gate connected to the node A9. The inverter IV1 has its input connected to the node A9 and its output connected to the node A10. The capacitor C is connected between the node A2 and ground.

[0061] The detector circuit 20' includes a p-channel transistor P4 having its source connected to a supply voltage, its drain connected to a node A3 and its gate connected to a node A2. An n-channel transistor N3 has its drain connected to the node A3, its source connected to ground and its gate connected to a reference voltage IREFN generated by a diode-coupled transistor N1. A NAND gate ND1 has its first input connected to the node A3, its second input connected to the node A8 and its output connected to the node A7. A NAND gate ND2 has its first input connected to the node A7, its second input connected to receive an input IN and its output connected to the node A8. An inverter IV2 has its input connected to the node A8 and its output generates an output signal OUT. A NAND gate ND3 has its first input connected to receive an input IN, its second input connected to the node A8 and its output connected to the node A9.

[0062] We will now discuss the Figure 7Operation of the timer 19' and detector circuit 20'. The timer 19' and detector circuit 20' form a delay circuit in which the output signal OUT transitions from a first logic state (e.g., 0) to a second logic state (e.g., 1) after a time delay T that is proportional to the product of the resistance of the resistor R and the capacitance of the capacitor C and is independent of the power supply voltage Vdd. When the input IN transitions from the first logic state (e.g., 0) to the second logic state (e.g., 1), the capacitor C is charged with a current approximately equal to (Vdd-VtP) / R, where Vdd is the supply voltage and VtP is the absolute value of the threshold voltage of the p-channel transistor P1 (remember that P1, P2 and P4 have the same threshold voltage). The time delay T is determined by the time it takes to charge the capacitor C from 0 to Vdd-VtP with this charging current, which is given by the following formula:

[0063] T=R×C

[0064] However, p-channel transistor P4 is subject to NBTI aging because its gate voltage follows the charge on capacitor C. Aging of p-channel transistor P4 results in an increase in its absolute threshold voltage from Vtp to VtPa. As transistor P4 ages, the delay time Ta is affected and becomes dependent on Vdd. The aging delay time Ta is given by the formula Ta=R×C×(Vdd-VtPa) / (Vdd-VtP), indicating that Ta is less than T. This reduction in delay time is due to aging of p-channel transistor P4.

[0065] For example, if Vdd = 1.6V, VtP = 0.8V and VtPa = 0.9V, then the aging delay time Ta is equal to

[0066] Ta=0.875×R×C

[0067] If VtPa reaches 1V, the aging delay time Ta becomes Ta = 0.75 × R × C, which further highlights the impact of aging on the delay time. Figure 8 , where the delay Ta is shown as nRC, where n is the constant described above (e.g., 0.875, 0.75).

[0068] To solve this problem caused by aging of the p-channel transistor P4, a Fig. 9 The timer 19" and the detector circuit 20". Here, Figure 7 The main difference between the timer 19' and the detector circuit 20' is that an aging protection circuit 30 is inserted between the node A3 and the first input terminal of the NAND gate ND1.

[0069] The timer 19″ includes a diode-coupled n-channel transistor N1 connected between the drain of a p-channel transistor P3 and ground, wherein the source of P3 is connected to a supply voltage and the gate of P3 is connected to a node A1. The p-channel transistor P1 has its source connected to the supply voltage, its drain connected to the node A1 and its gate connected to the node A1. A resistor R is connected between nodes A1 and A11. An n-channel transistor N4 has its drain connected to the node A11, its source connected to the ground and its gate connected to a node A10. A p-channel transistor P2 has its source connected to the supply voltage, its drain connected to the node A2 and its gate connected to the node A1. An n-channel transistor N2 has its drain connected to the node A2, its source connected to the ground and its gate connected to a node A9. An inverter IV1 has its input connected to the node A9 and its output connected to the node A10. A capacitor C is connected between the node A2 and ground.

[0070] The detector circuit 20″ includes a p-channel transistor P4 having its source connected to the supply voltage, its drain connected to the node A3 and its gate connected to the node A2. An n-channel transistor N3 has its drain connected to the node A3, its source connected to ground and its gate connected to the reference voltage IREFN generated by the diode-coupled transistor N1. The p-channel transistor P4 and the n-channel transistor N3 can be considered to form a first detector.

[0071] The aging protection circuit 30 is now described and includes an inverter IV3 having its input connected to the node A3 and its output connected to the node A4. A p-channel transistor P5 has its source connected to the node A4, its body connected to the node A4, its drain connected to the node A5 and its gate connected to the node A2. An n-channel transistor N5 has its drain connected to the node A5, its source connected to the ground and its gate connected to the reference voltage IREFN. A p-channel transistor P6 has its source connected to the power supply voltage, its drain connected to the node A6 and its gate connected to the node A4. An n-channel transistor N6 has its drain connected to the node A6, its source connected to the ground and its gate connected to the reference voltage IREFN.

[0072] P-channel transistor P5 may be a replica of p-channel transistor P4, and n-channel transistor N5 may be a replica of n-channel transistor N3. For example, p-channel transistors P5 and P4 may have the same width-to-length ratio, may have the same doping level, the same gate oxide thickness, etc. Similarly, n-channel transistors N5 and N3 may have the same width-to-length ratio, may have the same doping level, the same gate oxide thickness, etc.

[0073] The OR gate OR1 has its first input connected to the node A6, its second input connected to the node A5, and its output connected to the first input of the NAND gate ND1. The second input of the NAND gate ND1 is connected to the node A8, and the output of the NAND gate ND1 is connected to the node A7. The first input of the NAND gate ND2 is connected to the node A7, the second input is connected to receive the input IN, and the output is connected to the node A8. The NAND gate ND3 has its first input connected to receive the input IN, its second input is connected to the node A8, and its output is connected to the node A9. The NAND gates ND1-ND3 form a combinational logic circuit 40.

[0074] This detector circuit 20 ″ is not intended to avoid aging of the p-channel transistor P4, but to cascade a second detector (p-channel transistor P5, n-channel transistor N5) to effectively detect the charge of the capacitor C, and the second detector is powered on only when the first detector (p-channel transistor P4, n-channel transistor N3) detects the charge of the capacitor C.

[0075] Before the p-channel transistor P4 ages, both detectors switch when the voltage at node A2 becomes equal to Vdd-VtP, where Vdd is the supply voltage and VtP is the threshold voltage of P4.

[0076] However, when the p-channel transistor P4 ages, the first detector (p-channel transistor P4, n-channel transistor N3) switches when the voltage at node A2 becomes equal to Vdd-VtPa, where VtPa is the aging threshold of the p-channel transistor P4, and the second detector (p-channel transistor P5, n-channel transistor N5) switches when the voltage at node A2 becomes equal to Vdd-VtP because the p-channel transistor P5 has not aged because it avoids aging by turning on only when the p-channel transistor P4 turns on.

[0077] Therefore, in the aging device scenario, when the input IN enters the second logic state (e.g., logic 1), the capacitor C is gradually charged. The voltage at the node A3 is grounded after a period equal to the aging delay time Ta, which is greater than the delay time T before aging, as explained above, and is given by the following formula:

[0078] Ta=R×C×(Vdd-VtPa) / (Vdd-VtP)

[0079] At this point, the output of inverter IV3 raises the voltage at A4 and supplies current to the source of p-channel transistor P5, which turns on because its threshold voltage is VtP and its gate-source voltage |Vgs| is VtPa, which is greater than VtP. The gate-source voltage of p-channel transistor P5 is VtPa because its gate will be at the voltage at node A2 and its source will be at the voltage at node A2 minus the threshold voltage of p-channel transistor P4 (i.e., VtPa). Once p-channel transistor P5 turns on, the voltage at node A5 thus follows the voltage at node A4.

[0080] OR gate OR1 is connected between node A6 and a first input terminal of NAND gate ND1 to prevent a flip-flop (eg, NAND SR latch) formed by NAND gates ND1 and ND2 from switching when the voltage at A5 is ground before p-channel transistor P5 is turned on.

[0081] As long as the voltage at node A4 is ground, p-channel transistor P6 turns on and forces node A6 to the supply voltage Vdd. When the voltage at node A4 rises, p-channel transistor P6 turns off and n-channel transistor N6 pulls the voltage at A6 to ground. This arrangement exists because after the voltage at node A5 rises, the voltage at node A6 should be grounded to prevent the voltages at nodes A5 and A6 from being both grounded at the same time, which would immediately switch the flip-flop formed by NAND gates ND1 and ND2.

[0082] Therefore, in the aged device scenario, the first input terminal of the OR gate OR1 receives the same input at the same timing as in the non-aged device scenario. Therefore, the aging protection circuit can be said to compensate for the aging of the p-channel transistor P4 by providing the same input at the same timing to the first input terminal of the OR gate OR1 regardless of the aging of the p-channel transistor P4.

[0083] Additional references Fig.10 The timing diagram now describes Fig. 9 The operation of the timer 19" and the detector circuit 20".

[0084] In the initial state, the circuit is in a stable state, the voltage at node A8 is at Vdd and the voltage at node A7 is at ground, which is a valid state for the flip-flop formed by the NAND gates ND1 and ND2. When the input IN transitions to the second logic state (e.g., logic 1) at time T1, the input terminals of the NAND gate ND3 are all in the second logic state (e.g., logic 1), so that its output at node A9 drops. Since the input of the inverter IV1 at node A9 is in the first logic state (e.g., logic 0), the output of the inverter IV1 at node A10 eventually transitions to the second logic state (e.g., logic 1).

[0085] When the voltage at node A10 is subsequently in a second logic state (eg, logic 1), n-channel transistor N4 turns on, connecting node A11 to ground.

[0086] When node A11 is connected to ground, current flows out (sink) from node A1, which in turn turns on p-channel transistors P1 and P2. When p-channel transistor P2 is turned on, a current path is established between the supply voltage and node A2. Capacitor C is connected between node A2 and ground, so when current flows to node A2 through p-channel transistor P2, capacitor C begins to charge at time T2, causing the voltage at node A2 to rise. It is observed that at this time, the voltage at node A1 has dropped to Vdd-VtP, thereby turning on p-channel transistors P3 and P1, and the gate-source voltage Vgs is equal to VtP, mirroring the current through P1 to increase the voltage IREFN. Note that this current is also mirrored again into n-channel transistors N5 and N6.

[0087] As the voltage at node A2 increases (due to the current through p-channel transistor P1 being mirrored through p-channel transistor P2), it approaches the threshold voltage of p-channel transistor P4 (Vdd-Vtp when not aged, or Vdd-VtPa when aged). When the voltage at node A2 reaches the threshold voltage of p-channel transistor P4, the first detector (p-channel transistor P4, n-channel transistor N3) switches, and the voltage at node A3 changes from Vdd to ground for time T3.

[0088] The voltage transition at node A3 causes the output of inverter IV3 to rise, thereby raising the voltage at node A4. As the voltage at node A4 now rises, p-channel transistor P5 turns on because its gate-source voltage |Vgs| is greater than its threshold voltage VtP. This causes the voltage at node A5 to follow node A4 and rise at time T4.

[0089] As the voltage at node A5 rises, the OR gate OR1 asserts its output to the first input terminal of the NAND gate ND1, thereby preventing the flip-flop formed by the NAND gates ND1 and ND2 from switching. At the same time, when the voltage at node A4 rises from ground, the p-channel transistor P6 turns off, and the n-channel transistor N6 pulls the voltage at node A6 to ground.

[0090] Capacitor C continues to charge until the voltage at node A2 reaches Vdd-VtP at time T5. At this time, p-channel transistor P5 is turned off, causing the voltage at node A5 to drop to ground. Both node A5 and node A6 are at ground, causing the output of the OR gate to drop to a first logic state (e.g., logic 0), causing the flip-flop formed by the NAND gates ND1 and ND2 to switch, thereby triggering subsequent operations in the circuit, which are the same as those described above. Note that at time T6, due to the switching of the flip-flop formed by the NAND gates ND1 and ND2, the output of the inverter IV2 rises to a second logic state (e.g., logic 1), and the voltage at node A9 rises, thereby turning on the n-channel transistor N2 and thus discharging capacitor C to ground.

[0091] During this entire process, the second detector (p-channel transistor P5, n-channel transistor N5) is not aged. In particular, p-channel transistor P5 is not aged by NBTI because it does not experience a gate-to-source voltage Vgs that is negative enough to satisfy the NBTI aging condition. When the voltage at node A2 is low enough (less than Vdd-VtPa), the voltage at node A4 is 0V, and the gate-to-source voltage of p-channel transistor P5 is positive, indicating PBTI, which is not a problem in this case.

[0092] When the voltage at node A2 is equal to or greater than Vdd-VtPa, the voltage at node A4 is at Vdd, causing the gate-to-source voltage of p-channel transistor P5 to be greater than -VtPa, where VtPa is the threshold voltage of p-channel transistor P5. In a typical scenario, if the threshold voltage VtP is 0.8V and VtPa is at most 1V, the gate-to-source voltage of p-channel transistor P5 does not drop below -1V, thereby preventing NBTI aging conditions from occurring in p-channel transistor P5. Although p-channel transistor P6 may age, it operates in an on / off mode and receives its gate signal from inverter IV3. As a result, aging of p-channel transistor P6 does not affect the delay of delay circuit 19".

[0093] To further address the issues caused by aging of the p-channel transistor P4, an alternative embodiment is developed. Fig.11 The timer 19"' and the detector circuit 20"'. Here and Figure 7 The main difference between the timer 19' and the detector circuit 20' lies in the details of the aging protection circuit 30 connected between the node A3 and the first input terminal of the NAND gate ND1.

[0094] The timer 19'' includes a diode-coupled n-channel transistor N1 connected between the drain of a p-channel transistor P3 and ground, the source of P3 being connected to a supply voltage and the gate of P3 being connected to a node A1. The p-channel transistor P1 has its source connected to the supply voltage, its drain connected to the node A1 and its gate connected to the node A1. A resistor R is connected between nodes A1 and A11. An n-channel transistor N4 has its drain connected to the node A11, its source connected to the ground and its gate connected to a node A10. A p-channel transistor P2 has its source connected to the supply voltage, its drain connected to the node A2 and its gate connected to the node A1. An n-channel transistor N2 has its drain connected to the node A2, its source connected to the ground and its gate connected to a node A9. An inverter IV1 has its input connected to the node A9 and its output connected to the node A10. A capacitor C is connected between the node A2 and ground.

[0095] Detector circuit 20'" includes a p-channel transistor P4 having its source connected to a supply voltage, its drain connected to node A3 and its gate connected to node A2. An n-channel transistor N3 has its drain connected to node A3, its source connected to ground and its gate connected to a reference voltage IREFN generated by diode-coupled transistor N1. The p-channel transistor P4 and the n-channel transistor N3 may be considered to form a first detector.

[0096] The aging protection circuit 30 is now described, and includes three inverters IV3, IV4 and IV5 cascaded between nodes A3 and A4. The p-channel transistor P5 has its source and body connected to the node A4, its drain connected to the node A5 and its gate connected to the node A2. The n-channel transistor N5 has its drain connected to the node A5, its source connected to the ground and its gate connected to receive the reference voltage IREFN. The p-channel transistor P6 has its source connected to the supply voltage, its drain connected to the node A5 and its gate connected to the node A4.

[0097] P-channel transistor P5 may be a replica of p-channel transistor P4, and n-channel transistor N5 may be a replica of n-channel transistor N3.

[0098] The NAND gate ND1 has its first input terminal connected to the node A5, its second input terminal connected to the node A8, and its output terminal connected to the node A7. The NAND gate ND2 has its first input terminal connected to the node A7, its second input terminal connected to receive the input IN, and its output terminal connected to the node A8. The inverter IV2 has its input terminal connected to the node A8, and its output terminal generates the output signal OUT. The NAND gate ND3 has its first input terminal connected to receive the input IN, its second input terminal connected to the node A8, and its output terminal connected to the node A9.

[0099] With the detailed description of the previous embodiments given above, reference is now made to Fig.12 The operation of the timer 19'' and the detector circuit 20'' is described. In the aging device, as explained in the above embodiment, when the input IN transitions to the second logic state (e.g., logic 1) at time T1, the capacitor C is gradually charged from time T2. The node A3 has an initial voltage at Vdd, while the node A4 has an initial voltage at ground, and the node A5 has been precharged by the p-channel transistor P6.

[0100] As the device ages, the voltage at node A3 transitions to low after time Ta, as shown at time T3, causing inverters IV3, IV4, and IV5 to raise the voltage at node A4 and turn off p-channel transistor P6. The voltage at node A5 may decay due to the pull-down of n-channel transistor N5. However, when node A4 rises, the bulk and source of p-channel transistor P5 rise, causing p-channel transistor P5 to turn on and maintain node A5 at Vdd.

[0101] As capacitor C continues to charge, node A2 eventually reaches the supply voltage minus the threshold voltage of p-channel transistor P5, causing P5 to turn off and node A5 to fall to ground, as shown at time T4. This causes the flip-flop formed by transistors ND1 and ND2 to switch, and as shown in reference Fig. 9 Due to the switching of the flip-flop formed by the NAND gates ND1 and ND2, the output of the inverter IV2 rises to the second logic state (e.g., logic 1), and the voltage at the node A9 rises, thereby turning on the n-channel transistor N2, thereby discharging the capacitor C to the ground, as shown at time T5.

[0102] Finally, it will be apparent that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure. For example, another approach may be to isolate the input of the second detector from the input signal, but instead apply a signal based on the input signal at a safe level. Thus, in the disabled state, the detector circuit output ignores the detector circuit input, because this aging protection prevents the signal from propagating between the input and output. For example, in Fig. 9In FIG. 1 , instead of shutting off the power to p-channel transistor P5 through node A4, the source and body of p-channel transistor P5 are connected to Vdd, and the gate of p-channel transistor P5 is connected to Vdd as long as node A3 is high, and the gate of p-channel transistor P5 is connected to node A2 as long as node A3 goes low (while maintaining inverter IV3, node A4, p-channel transistor P6 and n-channel transistor N6 to avoid parasitic detection).

[0103] Method aspects are also disclosed herein. For example, a method may include receiving an input signal at a first detector, generating a first detector output signal when the input signal reaches a first activation threshold, enabling a second detector with the first detector output signal and generating a second detector output signal when the input signal reaches a second activation threshold, and performing a logic operation on the first and second detector outputs to generate an output indicating that the input signal has reached a voltage equal to the second activation threshold.

[0104] Due to aging of at least one MOS transistor in the first detector, the second activation threshold may be greater than the first activation threshold.

[0105] The voltage equal to the second activation threshold may correspond to a desired voltage level across the capacitor of the timer.

[0106] The logical operation performed on the first and second detector outputs may be a logical AND operation, and when both the first and second detector outputs are asserted, an output indicating that the input signal has reached a voltage equal to a second activation threshold may be asserted, the second activation threshold being greater than the first activation threshold due to aging of at least one MOS transistor in the first detector.

[0107] Although the present disclosure has been described using a limited number of embodiments, those skilled in the art having benefit of this disclosure may devise other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may devise embodiments that represent various combinations of the embodiments disclosed herein performed in various ways.

Claims

1. A circuit, characterized in that: include: A detector circuit comprising: a first detector configured to receive an input signal and generate a first detector output signal indicating that the input signal has reached a first activation threshold; a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicating that the input signal has reached a second activation threshold; and A logic circuit is configured to perform a logic operation on the first detector output signal and the second detector output signal to generate an output indicating that the input signal has reached a voltage equal to a second activation threshold.

2. The circuit according to claim 1, characterized in that Due to aging of at least one MOS transistor in the first detector, the second activation threshold is greater than the first activation threshold.

3. The circuit according to claim 1, characterized in that The voltage equal to the second activation threshold is the desired voltage level across the capacitor of the timer.

4. The circuit according to claim 1, characterized in that The logic circuit includes an AND gate configured to perform a logical AND operation on the first detector output signal and the second detector output signal to assert an output indicating that the input signal has reached a voltage equal to a second activation threshold.

5. The circuit according to claim 1, characterized in that Also included is a timing circuit configured to charge the capacitor in response to assertion of the input signal; The detector circuit further includes: Aging mitigation circuitry, including: a first inverter having an input connected to receive the first detector output and to provide a first inverter output; A second detector, the second detector comprising: a first p-channel transistor having a source and a body connected to receive the first inverter output, a drain connected to the first tap node, and a gate connected to receive the voltage on the capacitor; and a first n-channel transistor having a drain connected to the first tap node, a source connected to ground, and a gate connected to receive a reference voltage; a second p-channel transistor having a source connected to the supply voltage, a drain connected to the second tap node, and a gate connected to receive the output of the first inverter; and a second n-channel transistor having a drain connected to the second tap node, a source connected to ground and a gate connected to receive a reference voltage; The logic circuit performs a logic operation on the first detector output and the second detector output by receiving inputs from the first tap node and the second tap node and generating an output signal and discharging the capacitor based thereon.

6. The circuit as claimed in claim 5, It is characterized in that Wherein, the first detector comprises: a third p-channel transistor having a source connected to the supply voltage, a drain connected to the third tap node, and a gate connected to receive the voltage on the capacitor; and A third n-channel transistor has a drain connected to the third tap node, a source connected to ground, and a gate connected to receive a reference voltage.

7. The circuit according to claim 6, characterized in that The first inverter has its input connected to the third tap node and its output connected to the gate of the second p-channel transistor.

8. The circuit according to claim 5, characterized in that The logic circuit includes: An OR gate having a first input terminal connected to the second tap node, a second input terminal connected to the first tap node, and an output terminal; A first NAND gate having a first input terminal connected to the output terminal of the OR gate, a second input terminal connected to the pre-output node, and an output terminal; and The second NAND gate has a first input terminal connected to the output terminal of the first NAND gate, a second input terminal connected to receive an input signal, and an output terminal connected to the pre-output node.

9. The circuit according to claim 8, characterized in that The logic circuit also includes: The third NAND gate has a first input terminal connected to receive the input signal, a second input terminal connected to the pre-output node, and an output terminal connected to the timing circuit.

10. The circuit according to claim 1, characterized in that Also included is a timing circuit configured to charge the capacitor in response to assertion of the input signal; The detector circuit further includes: Aging mitigation circuitry, including: an inverter circuit having an input connected to receive the first detector output and to provide a first inverter output; A second detector, the second detector comprising: a first p-channel transistor having a source and a body connected to receive the first inverter output, a drain connected to the first tap node, and a gate connected to receive the voltage on the capacitor; and a first n-channel transistor having a drain connected to the first tap node, a source connected to ground, and a gate connected to receive a reference voltage; and a second p-channel transistor having a source connected to the supply voltage, a drain connected to the first tap node, and a gate connected to receive the output of the first inverter; The logic circuit performs a logic operation on the first detector output and the second detector output by receiving an input from the first tap node and generating an output signal and discharging the capacitor based thereon.

11. The circuit as claimed in claim 10, It is characterized in that Wherein, the first detector comprises: a third p-channel transistor having a source connected to the supply voltage, a drain connected to the second tap node, and a gate connected to receive the voltage on the capacitor; and A third n-channel transistor has a drain connected to the second tap node, a source connected to ground, and a gate connected to receive a reference voltage.

12. The circuit according to claim 10, characterized in that The inverter circuit includes a series of cascaded inverters connected between the second tap node and the gate of the second p-channel transistor.

13. An EEPROM, characterized in that: include: a timer configured to charge and discharge the capacitor to time the operation; as well as The detector circuit of claim 1, wherein the voltage across the capacitor is an input signal received by the first detector and the second detector of the detector circuit.

Images