SiC MOSFET capable of reducing holes in PP region

Abstract

The utility model discloses a SiC MOSFET capable of reducing holes in a PP region, and relates to the technical field of semiconductors. According to the utility model, the N + region of the cut-off region is formed at the lower part of the P-body region and the bottom of the PP region in the device, so that the N + region as the cut-off region cuts off the hole of the PP region in the follow current process of the PN junction body diode of the device, and the hole is prevented from entering the SiC Drift layer. Therefore, recombination of holes in the PP region and electrons in the SiC Drift layer is reduced, and the bipolar degradation risk of the device is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC MOSFET capable of reducing PP zone holes. Background Art

[0002] Voltage-controlled switching devices have always been dominated by Si MOSFET and Si IGBT devices. Si MOSFET devices have a unipolar structure, so they have high switching frequency and low switching loss, but they are not suitable for high-voltage and high-power fields, and cannot achieve a performance compromise of high voltage and low conduction loss. Si IGBT devices have a bipolar structure, so they can withstand high voltage, and the conductivity modulation effect of the device under high current will also reduce the device resistance, thereby achieving a combination of high voltage and low conduction loss performance, but they are not suitable for high switching frequency fields, and their switching frequency is low, usually below 40kHz. SiC MOSFET devices made of the third-generation semiconductor material SiC benefit from the unipolar characteristics of MOSFET to achieve high switching frequency, and benefit from the excellent physical properties of SiC materials to achieve a combination of high voltage and low conduction loss performance, and are very promising products in the future.

[0003] In SiC MOSFET, a PN junction diode is usually integrated inside the device. In addition to playing the role of a freewheeling diode, this PN junction diode can also improve the reverse withstand voltage capability of the device by making an ohmic contact, which is a very good structural design. However, with long-term use, researchers have found that the internally integrated PN junction diode will cause the performance of SiC MOSFET devices to deteriorate. This is because when the PN junction diode is used for a long time, the holes in its P region will enter the SiC Drift layer. Since the SiC Drift layer has relatively more defects, when the holes in the P region recombine with the electrons in the SiC Drift layer, it will cause the lattice defects in the material to spread, and the area where the defects spread will lose its function, which is very unfavorable for the long-term stable use of the device. Utility Model Content

[0004] In view of the above problems, the utility model proposes a SiC MOSFET with reduced PP region holes, which reduces the recombination of PP region holes and SiC Drift layer electrons, thereby reducing the risk of bipolar degradation of the device.

[0005] The technical solution of the utility model is:

[0006] A SiC MOSFET for reducing PP region holes includes a SiC Sub layer, a SiC Drift layer, an Ohmic contact alloy layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0007] The top surface of the SiC Drift layer is provided with a P-body region extending downward;

[0008] An N+ region extending downward is provided in the P-body region, and a gap is provided between the top surface of the N+ region and the top surface of the P-body region;

[0009] The top surface of the P-body region is provided with an NP region extending downward;

[0010] A PP region is provided in the middle of the top surface of the NP region, extending downward and connected to the N+ region; the depth of the PP region is less than the depth of the N+ region;

[0011] The top surface of the SiC Drift layer (2) is provided with a gate oxide layer connected to the P-body region and the NP region respectively;

[0012] A Poly layer is provided on the gate oxide layer;

[0013] An isolation dielectric layer is provided on the top surface of the Poly layer, and the isolation dielectric layer extends downward from the gate oxide layer and the side of the Poly layer and is connected to the NP region;

[0014] The bottom of the ohmic contact alloy layer is connected to the NP region and the PP region respectively, and the side is connected to the isolation dielectric layer.

[0015] Specifically, the front electrode metal layer is arranged on the isolation dielectric layer and the ohmic contact alloy layer.

[0016] Specifically, the SiC Sub layer is an N-type SiC Sub layer;

[0017] The SiC Drift layer is an N-type SiC Drift layer.

[0018] Specifically, the P-body region has a depth of 1um-1.2um.

[0019] Specifically, the top surface depth of the N+ region is 0.4um-0.6um.

[0020] Specifically, the NP region has a depth of 0.4 um.

[0021] Specifically, the PP region has a depth of 0.6 um, and the PP region is connected to the N+ region.

[0022] The utility model forms an N+ region of the cut-off region at the bottom of the P-body region and the bottom of the PP region in the SiC MOSFET device, so that during the freewheeling process of the device PN junction diode, the N+ region as the cut-off region cuts off the holes in the PP region to prevent them from entering the SiC Drift layer. This reduces the recombination of the holes in the PP region and the electrons in the SiC Drift layer, thereby reducing the risk of bipolar degradation of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of SiC MOSFET of the utility model;

[0024] Figure 2 It is a structural schematic diagram of step S100 of the utility model;

[0025] Figure 3 It is a structural schematic diagram of step S200 of the utility model;

[0026] Figure 4 It is a structural schematic diagram of step S300 of the utility model;

[0027] Figure 5 It is a structural schematic diagram of step S400 of the utility model;

[0028] Figure 6 It is a schematic diagram of the structure of step S500 of the utility model;

[0029] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0030] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0031] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0032] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0033] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0034] In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P-body region, 4 is N+ region, 5 is NP region, 6 is PP region, 7 is gate oxide layer, 8 is Poly layer, 9 is isolation dielectric layer, 10 is ohmic contact alloy layer, and 11 is front electrode metal layer. DETAILED DESCRIPTION

[0035] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0036] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] A method for preparing a SiC MOSFET with reduced PP region holes comprises the following steps:

[0039] S100, such as Figure 2 As shown, a SiC Drift layer 2 is epitaxially grown on the SiC Sub layer 1, the SiC Sub layer 1 plays a supporting role, and the SiC Drift layer 2 plays a protective role;

[0040] In step S100 , both the SiC Sub layer 1 and the SiC Drift layer 2 are of N-type conductivity.

[0041] S200, such as Figure 3 As shown, after mask layer deposition, pattern photolithography, and stripping and cleaning, a P-body region 3 is formed on the SiC Drift layer 2 by Al ion implantation;

[0042] The depth of the P-body region 3 in step S200 is 1 um-1.2 um.

[0043] S300, such as Figure 4 As shown, after mask layer deposition, pattern photolithography, and degumming and cleaning, N+ region 4 is formed by N ion implantation on the SiC Drift layer 2. The N+ region 4 serves as a hole cutoff region of the SiC MOSFET device.

[0044] In step S300, the top surface depth of the N+ region 4 is 0.4um-0.6um (the top surface depth refers to the distance between the top surface of the P-body region 3 and the top surface of the N+ region 4), and the bottom surface depth is 1um-1.2um (the distance between the bottom surface of the N+ region 4 and the top surface of the P-body region 3). The depth of the N+ region 4 is ≥ the depth of the P-body region 3 to form a good cutoff region.

[0045] S400, such as Figure 5 As shown, a spacer layer is formed on the SiC Drift layer 2 by mask layer deposition, mask layer etching, and degumming and cleaning, and then an NP region 5 is formed by N ion implantation. The function of the NP region 5 is to form a channel with the P-body region 4 after the gate is pressurized;

[0046] The depth of the NP region (5) in step S400 is 0.4 um.

[0047] S500, such as Figure 6 As shown, after mask layer deposition, pattern photolithography, and degumming and cleaning on the SiC Drift layer 2, Al ion implantation is performed to form a PP region 6. The PP region 6 is used to achieve the same potential with the NP region 5 and the P-body region 3 after ohmic contact is made, so as to improve the reverse withstand voltage capability of the SiC MOSFET device, and at the same time, it is used as a PN junction body diode of the device.

[0048] The depth of the PP region 6 in step S500 is 0.6 um, and the PP region 6 is connected to the N+ region 4 .

[0049] S600, after the SiC Drift layer 2 is coated with glue and carbonized with photoresist, the P-body region 3, the N+ region 4, the NP region 5, and the PP region 6 are activated and formed by high-temperature ion activation;

[0050] S700, such as Figure 7 As shown, a gate oxide layer 7 is formed on the SiC Drift layer 2 by dry oxygen oxidation, and NO annealing is introduced during the process to improve the quality of the gate oxide layer 7;

[0051] S800, such as Figure 8 As shown, after polysilicon Poly deposition, pattern photolithography, polysilicon Poly etching removal, and degumming and cleaning on the gate oxide layer 7, the required Poly layer 8 is formed as the gate electrode of the device;

[0052] S900, such as Fig. 9 As shown, an isolation dielectric layer 9 is formed on the NP region 5 and the Poly layer 8 by oxide deposition and densification, serving as a dielectric for isolating the gate electrode and the source electrode in the source region of the device to prevent the two from being short-circuited;

[0053] S1000, such as Fig.10 As shown, an ohmic contact alloy layer 10 is formed on the SiC Drift layer 2 by Ni metal sputtering and rapid thermal annealing;

[0054] The Ni metal sputtering thickness in step S1000 is 100 nm.

[0055] S1100, such as Fig.11 As shown, an electrode is formed at the top of the device by sputtering Ti / AlCu metal, and then a front electrode metal layer 11 is formed by pattern lithography, etching, and degumming and cleaning.

[0056] The sputtering thickness of Ti / AlCu metal in step S1100 is 100nm / 5000nm.

[0057] A SiC MOSFET for reducing PP region holes comprises a SiC Sub layer 1, a SiC Drift layer 2, an Ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top;

[0058] The top surface of the SiC Drift layer 2 is provided with a P-body region 3 extending downward;

[0059] An N+ region 4 extending downward is provided in the P-body region 3, a gap is provided between the top surface of the N+ region 4 and the top surface of the P-body region 3, and a bottom surface of the N+ region 4 and the bottom surface of the P-body region 3 are in the same plane;

[0060] The top surface of the P-body region 3 is provided with an NP region 5 extending downward; the N+ region 4 and the NP region 5 are respectively located in the middle of the P-body region 3;

[0061] A PP region 6 extending downward and connected to the N+ region 4 is provided in the middle of the top surface of the NP region 5; the PP region 6 is connected to the NP region 5; the depth of the PP region 6 is greater than the depth of the NP region 5;

[0062] The top surface of the SiC Drift layer 2 is provided with a gate oxide layer 7 connected to the P-body region 3 and the NP region 5 respectively;

[0063] A Poly layer 8 is disposed on the gate oxide layer 7; the thickness of the Poly layer 8 is greater than the thickness of the gate oxide layer 7;

[0064] An isolation dielectric layer 9 is provided on the top surface of the Poly layer 8, and the isolation dielectric layer 9 extends downward from the sides of the gate oxide layer 7 and the Poly layer 8 and is connected to the NP region 5;

[0065] The bottom of the ohmic contact alloy layer 10 is connected to the NP region 5 and the PP region 6 respectively, and the side is connected to the isolation dielectric layer 9;

[0066] The front electrode metal layer 11 is disposed on the isolation dielectric layer 9 and the ohmic contact alloy layer 10 .

[0067] Beneficial effects of the utility model:

[0068] SiC MOSFET devices generally integrate PN junction diodes internally. This PN junction diode not only improves the reverse withstand voltage capability of the device through ohmic contact, but also serves as a leakage path during the device's freewheeling process, thus protecting the device again. It is a very good design. However, the PN junction diode also has disadvantages. When the PN junction diode is turned on as a freewheeling tube, the holes in its P region will enter the SiC Drift layer, which can easily cause the holes in the P region to recombine with the electrons in the SiC Drift layer, thereby causing the lattice defects of the SiC Drift layer to spread, resulting in deterioration of the device's performance. In order to improve this problem, the utility model forms a cutoff region N+ region 4 at the bottom of the P-body region 3 and the bottom of the PP region 6 in the SiC MOSFET device, so that during the device's freewheeling process, the holes in the PP region of the PN junction diode will be cut off in the N+ region and will not enter the SiC Drift layer, thereby improving the bipolar degradation effect of the device.

Claims

1. A SiC MOSFET with reduced PP region holes, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), an Ohmic contact alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The top surface of the SiC Drift layer (2) is provided with a P-body region (3) extending downward; An N+ region (4) extending downward is provided in the P-body region (3), and a gap is provided between the top surface of the N+ region (4) and the top surface of the P-body region (3); The top surface of the P-body region (3) is provided with an NP region (5) extending downward; A PP region (6) extending downward and connected to the N+ region (4) is provided in the middle of the top surface of the NP region (5); the depth of the PP region (6) is less than the depth of the N+ region (4); The top surface of the SiC Drift layer (2) is provided with a gate oxide layer (7) connected to the P-body region (3) and the NP region (5) respectively; A Poly layer (8) is provided on the gate oxide layer (7); An isolation dielectric layer (9) is provided on the top surface of the Poly layer (8), and the isolation dielectric layer (9) extends downward from the side of the gate oxide layer (7) and the Poly layer (8) and is connected to the NP region (5); The bottom of the ohmic contact alloy layer (10) is connected to the NP region (5) and the PP region (6) respectively, and the side is connected to the isolation dielectric layer (9).

2. The SiC MOSFET with reduced PP region holes according to claim 1, characterized in that: The front electrode metal layer (11) is arranged on the isolation dielectric layer (9) and the ohmic contact alloy layer (10).

3. The SiC MOSFET with reduced PP region holes according to claim 1, characterized in that: The SiC Sub layer (1) is an N-type SiC Sub layer; The SiC Drift layer (2) is an N-type SiC Drift layer.

4. The SiC MOSFET with reduced PP region holes according to claim 1, characterized in that: The P-body region (3) has a depth of 1 um to 1.2 um.

5. The SiC MOSFET with reduced PP region holes according to claim 1, characterized in that: The top surface depth of the N+ region (4) is 0.4um-0.6um.

6. The SiC MOSFET with reduced PP region holes according to claim 1, characterized in that: The NP region (5) has a depth of 0.4 um.

7. The SiC MOSFET with reduced PP region holes according to claim 1, characterized in that: The PP region (6) has a depth of 0.6 um, and the PP region (6) is connected to the N+ region (4).

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