SiC MOSFET device capable of avoiding mistaken opening
By incorporating a dielectric resistor layer in the gate Gate Pad region of the SiC MOSFET device, the problem of the device being easily turned on incorrectly during the switching process is solved, and the effect of reducing gate oscillation and improving system stability is achieved.
Patent Information
- Application Number
- CN202421517837.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-30
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-06-30
AI Technical Summary
SiC MOSFET devices are prone to gate oscillation during switching, resulting in incorrect turn-on, affecting system use and may lead to breakdown failure.
In the gate Gate Pad region of the SiC MOSFET device, a dielectric resistor layer is built into the dielectric layer to increase the gate resistance inside the device and reduce the gate oscillation energy.
It effectively avoids the device error, improves the stability and efficiency of the overall system, and reduces switching losses.
Smart Images
Figure CN222827576U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC MOSFET device which can avoid being turned on by mistake. Background Art
[0002] In the field of power electronics technology, power devices have always been the main products in various markets, and their application scope covers various fields such as automobiles, photovoltaics, communications, industry, and consumer electronics. On the rectifier side of the application system, two solutions are generally adopted. One is to use a rectifier bridge composed of diodes for rectification, and the other is to use a synchronous rectifier bridge arm composed of switching devices such as MOSFET for rectification. In comparison, the diode rectifier bridge has high loss and low overall efficiency due to its own conduction voltage drop, but the advantage is low cost and stability. The MOSFET rectifier bridge arm has low conduction loss due to the switching characteristics of the MOSFET, which brings high overall efficiency, but the disadvantage is high cost and more complicated use.
[0003] Due to the inductance and capacitance of MOSFET devices, gate oscillation will occur during the switching process of the device by external driving voltage. The disadvantage is that the device is prone to false start, which affects the use of the entire system and may even cause the device to break down and fail. In order to reduce the gate oscillation phenomenon of MOSFET devices, the general method is to connect a gate resistor Rg in series outside the gate of the device to weaken the oscillation energy during the switching process of the device. However, the use of an additional resistor will undoubtedly increase the number of devices used and the device cost of the entire system. Therefore, if the gate resistor can be built into the MOSFET device, this problem will be avoided. Utility Model Content
[0004] The utility model deposits a dielectric layer in the gate pad region inside the SiC MOSFET device to connect a dielectric resistance layer in series inside, thereby increasing the gate resistance inside the device, reducing the gate oscillation energy during the switching process, and avoiding the device from being turned on by mistake.
[0005] The technical solution of the utility model is:
[0006] Avoiding SiC MOSFET devices that are turned on by mistake, including setting up SiC Sub layer and SiC Drift layer from bottom to top;
[0007] The SiC Drift layer in the source region and the Gate Pad region is provided with a P-body region extending downward;
[0008] The P-body region of the source region is provided with a NP region and a PP region extending downward; the NP region and the PP region are connected at the side;
[0009] A blocking dielectric layer extending to the Gate Bias region is provided on the top surface of the P-body region of the Gate Pad region;
[0010] A gate oxide layer connected to the blocking dielectric layer of the Gate Bias region is provided on the side thereof and extends toward the source region;
[0011] A Poly layer is provided on the blocking dielectric layer and the gate oxide layer;
[0012] The top surface of the Poly layer in the source region is provided with an isolation dielectric layer extending downward from the side of the Poly layer and connected to the NP region; the isolation dielectric layer extends to the Poly layer in the Gate Bias region and is respectively connected to the side of the Poly layer and the gate oxide layer;
[0013] The side of the isolation dielectric layer of the source region is provided with an ohmic contact alloy layer connected to the top surface of the NP region and the PP region respectively;
[0014] A dielectric resistance layer is provided on the top surface of the Poly layer in the Gate Pad region;
[0015] A gate metal layer is disposed on the dielectric resistance layer and extends downward from the side to be connected to the top surface of the Poly layer; the gate metal layer extends toward the Gate Bias region, and the bottom is respectively connected to the Poly layer and the isolation dielectric layer in the Gate Bias region;
[0016] The source region is provided with a source metal layer covering the top surfaces of the isolation dielectric layer and the ohmic contact alloy layer, and extending to the top surface of the isolation dielectric layer in the Gate Bias region.
[0017] Specifically, the blocking dielectric layer is a SiO2 blocking dielectric layer.
[0018] Specifically, the thickness of the blocking medium layer is 0.8um-1um.
[0019] Specifically, the dielectric resistance layer is a SiO2 dielectric resistance layer or a Si3N4 dielectric resistance layer, and has a thickness of 1um-2um.
[0020] Specifically, the thickness of the gate oxide layer is 45nm-50nm.
[0021] The utility model deposits a dielectric layer in the gate pad region inside the SiC MOSFET device to connect a dielectric resistance layer in series, thereby increasing the gate resistance inside the device. However, since the gate resistance will increase the switching loss of the device, an excessively large gate resistance will also affect the use of the device. The dielectric resistance layer of the utility model can change the resistance value by adjusting the thickness, so that the thickness can be changed according to the actual design requirements, thereby weakening the oscillation energy and preventing the device from being turned on by mistake. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 is a top view of the utility model (the gate metal layer is hidden in the figure);
[0023] Figure 2 yes Figure 1 Structural diagram of the AA section in the Y direction;
[0024] Figure 3 yes Figure 1 The structural diagram of the BB section in the X direction;
[0025] Figure 4 yes Figure 1 Structural diagram of CC section in Y direction;
[0026] Figure 5 It is a top view schematic diagram of the P-body area setting structure;
[0027] Figure 6 is a top view schematic diagram of the setting structure of the blocking medium layer;
[0028] Figure 7 Schematic diagram of the top view of the gate oxide layer and the Poly layer structure;
[0029] In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P-body region, 4 is NP region, 5 is PP region, 6 is blocking dielectric layer, 7 is gate oxide layer, 8 is Poly layer, 9 is isolation dielectric layer, 10 is dielectric resistance layer, 11 is ohmic contact alloy layer, 12 is gate metal layer, and 13 is source metal layer. DETAILED DESCRIPTION
[0030] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.
[0031] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.
[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0033] like Figure 1 As described above, the dashed rectangular frame Gate Pad on the left side of the figure is the gate welding area, and the long dashed rectangular frame Gate Bias on the right side is the gate wiring area.
[0034] To avoid false turn-on of SiC MOSFET devices, the following steps are included:
[0035] S100, epitaxially growing a SiC Drift layer 2 on the SiC Sub layer 1;
[0036] In step S100 , the conductivity types of the SiC Sub layer 1 and the SiC Drift layer 2 are both N-type.
[0037] S200, forming a lightly doped P-body region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;
[0038] The doping concentration of the P-body region 3 in step S200 is 1E17-3E18cm -2 .
[0039] S300, forming a heavily doped NP region 4 on the top surface of the P-body region 3 by N ion implantation;
[0040] The doping concentration of NP region 4 in step S300 is 1E18-1E19cm -2 .
[0041] S400, forming a heavily doped PP region 5 connected to the side of the NP region 4 on the top surface of the P-body region 3 by Al ion implantation;
[0042] The doping concentration of PP region 5 in step S400 is 1E18-1E19 cm -2 .
[0043] S500, forming a blocking dielectric layer 6 on the top surface of the SiC Drift layer 2 by oxide deposition, isolating the gate electrode at the gate bias and the SiC Drift layer to avoid use risks therein;
[0044] The material of the blocking dielectric layer 6 in step S500 is SiO2, and the thickness is 0.8um-1um.
[0045] S600, growing a gate oxide layer 7 on the top surface of the SiC Drift layer 2 and the side of the blocking dielectric layer 6 by introducing oxygen in a dry oxygen oxidation manner;
[0046] The thickness of the gate oxide layer 7 is 45 nm-50 nm.
[0047] S700, forming a Poly layer 8 covering the gate oxide layer 7 and the blocking dielectric layer 6 on the top surface of the gate oxide layer 7 by polysilicon deposition, as a gate electrode of the device;
[0048] S800, forming an isolation dielectric layer 9 on the top surface of the NP region 4 and the Poly layer 8 by oxide deposition, isolating the gate electrode and the source electrode at the source of the device to avoid short circuit between the two;
[0049] S900, forming a dielectric resistance layer 10 on the top surface of the Poly layer 8 in the gate pad region by oxide deposition, so as to increase the gate resistance of the device and reduce the gate switch oscillation;
[0050] The material of the dielectric resistance layer 10 in step S900 is SiO2 or Si3N4, and the thickness is 1um-2um.
[0051] S1000, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 4 and the PP region 5 by Ni metal sputtering and then by rapid thermal annealing;
[0052] The thickness of the Ni metal in step S1000 is 100 nm.
[0053] S1100, forming a gate metal layer 12 and a source metal layer 13 on the top of the device by AlCu metal sputtering, wherein the gate metal layer 12 serves as a gate electrode of the device, and the source metal layer 13 serves as a source electrode of the device.
[0054] The thickness of the AlCu metal in step S1100 is 5000 nm.
[0055] A SiC MOSFET device that avoids false start-up includes a SiC Sub layer 1 and a SiCDrift layer 2 that are sequentially arranged from bottom to top;
[0056] The SiC Drift layer 2 in the source region and the Gate Pad region is provided with a P-body region 3 extending downward, such as Figure 5 As shown;
[0057] The P-body region 3 of the source region is provided with a NP region 4 and a PP region 5 extending downward; the NP region 4 and the PP region 5 are connected at the sides, and the depth of the PP region 5 is greater than the depth of the NP region 4;
[0058] The top surface of the P-body region 3 in the Gate Pad region is provided with a blocking dielectric layer 6 extending to the Gate Bias region. Figure 6 As shown; the blocking dielectric layer 6 is located in the middle of the Gate Bias region;
[0059] The side of the blocking dielectric layer 6 in the Gate Bias region is provided with a gate oxide layer 7 connected thereto and extending toward the source region. Figure 7 As shown;
[0060] A Poly layer 8 is provided on the blocking dielectric layer 6 and the gate oxide layer 7; the thickness of the blocking dielectric layer 6 in the Gate Bias region is greater than the thickness of the gate oxide layer 7, and the Poly layer 8 in the Gate Bias region is provided with a boss located on the blocking dielectric layer 6;
[0061] The top surface of the Poly layer 8 in the source region is provided with an isolation dielectric layer 9 extending downward from the side of the Poly layer 8 and connected to the NP region 4; the isolation dielectric layer 9 extends to the Poly layer 8 in the Gate Bias region;
[0062] The isolation dielectric layer 9 of the source region is connected to the side of the Poly layer 8 and the gate oxide layer 7 respectively;
[0063] The side of the isolation dielectric layer 9 of the source region is provided with an ohmic contact alloy layer 11 connected to the top surfaces of the NP region 4 and the PP region 5 respectively;
[0064] A dielectric resistance layer 10 is provided on the top surface of the Poly layer 8 in the Gate Pad region;
[0065] A gate metal layer 12 is disposed on the dielectric resistance layer 10 and extends downward from the side to connect with the top surface of the Poly layer 8; the gate metal layer 12 extends toward the Gate Bias region, and the bottom is respectively connected with the Poly layer 8 and the isolation dielectric layer 9 in the Gate Bias region;
[0066] The source region is provided with a source metal layer 13 covering the top surfaces of the isolation dielectric layer 9 and the ohmic contact alloy layer 11 and extending to the top surface of the isolation dielectric layer 9 in the Gate Bias region.
[0067] The utility model reduces the gate oscillation of the device and avoids the device from being turned on by mistake:
[0068] In MOSFET devices, due to the presence of inductance and capacitance inside the device, gate oscillation occurs at the gate during the switching process of the device gate by the external driving voltage, which causes the device to be turned on by mistake, affecting the entire system, and in severe cases, causing the device to fail due to breakdown. This utility model patent deposits a dielectric layer in the gate pad region inside the SiC MOSFET device to connect a dielectric resistance layer in series inside, thereby increasing the gate resistance inside the device, and can change its resistance value by adjusting the thickness of the dielectric resistance layer, thereby reducing the gate oscillation effect of the device and preventing the device from being turned on by mistake.
Claims
1. A SiC MOSFET device for avoiding false start-up, characterized in that: The method includes sequentially arranging a SiC Sub layer (1) and a SiC Drift layer (2) from bottom to top; The SiC Drift layer (2) in the source region and the Gate Pad region is provided with a P-body region (3) extending downward; The P-body region (3) of the source region is provided with a NP region (4) and a PP region (5) extending downward; the NP region (4) and the PP region (5) are connected at the sides; The top surface of the P-body region (3) of the Gate Pad region is provided with a blocking dielectric layer (6) extending to the Gate Bias region; A gate oxide layer (7) connected to the blocking dielectric layer (6) in the Gate Bias region is provided on the side thereof and extends toward the source region; A Poly layer (8) is provided on the blocking dielectric layer (6) and the gate oxide layer (7); The top surface of the Poly layer (8) in the source region is provided with an isolation dielectric layer (9) extending downward from the side of the Poly layer (8) and connected to the NP region (4); the isolation dielectric layer (9) extends onto the Poly layer (8) in the Gate Bias region and is respectively connected to the side of the Poly layer (8) and the gate oxide layer (7); The side of the isolation dielectric layer (9) in the source region is provided with an ohmic contact alloy layer (11) respectively connected to the top surfaces of the NP region (4) and the PP region (5); A dielectric resistance layer (10) is provided on the top surface of the Poly layer (8) in the Gate Pad region; A gate metal layer (12) is provided on the dielectric resistance layer (10) and extends downward from the side to be connected to the top surface of the Poly layer (8); the gate metal layer (12) extends toward the Gate Bias region, and the bottom is respectively connected to the Poly layer (8) and the isolation dielectric layer (9) in the Gate Bias region; The source region is provided with a source metal layer (13) covering the top surfaces of the isolation dielectric layer (9) and the ohmic contact alloy layer (11), and extending to the top surface of the isolation dielectric layer (9) in the Gate Bias region.
2. The SiC MOSFET device for preventing mis-startup according to claim 1, characterized in that: The blocking dielectric layer (6) is a SiO2 blocking dielectric layer.
3. The SiC MOSFET device for preventing mis-startup according to claim 2, characterized in that: The thickness of the blocking medium layer (6) is 0.8 um-1 um.
4. The SiC MOSFET device for preventing mis-startup according to claim 1, characterized in that: The dielectric resistance layer (10) is a SiO2 dielectric resistance layer or a Si3N4 dielectric resistance layer, and has a thickness of 1 um to 2 um.
5. The SiC MOSFET device for preventing mis-startup according to claim 1, characterized in that: The thickness of the gate oxide layer (7) is 45nm-50nm.