SiC MOSFET with higher through-current capability

Abstract

The utility model discloses a SiC MOSFET with higher through-current capability, and relates to the technical field of semiconductors. According to the utility model, the size of a P-body region without a P + region is reduced, so that a conventional strip-shaped channel region is changed into a step-shaped channel region, and the length of the channel region serving as a through-flow path in the unit area inside the device is increased to about 1.6 microns, thereby improving the through-flow capability of the unit area of the device and improving the power density.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC MOSFET with higher current carrying capacity. Background Art

[0002] As a voltage-controlled switching device, MOSFET is used in various fields of power electronic systems. However, due to the physical performance limits of the material itself, traditional Si-based MOSFET devices cannot achieve a compromise between high voltage and low conduction loss performance. Therefore, current Si MOSFET devices are usually below 600V. In high-power applications, Si IGBT devices are widely used due to their high withstand voltage and low conduction loss performance advantages under high voltage. However, Si IGBT devices do not have the high switching frequency advantage of MOSFET devices, resulting in most of them being used in the industrial control field. However, with the continuous progress of society, especially the development of new energy vehicles, photovoltaics and other industries towards high voltage and high power fields, Si MOSFET and Si IGBT devices can no longer fully meet these more stringent application requirements.

[0003] The third generation semiconductor material SiC has very significant physical properties, so the prepared SiCMOSFET device not only has the advantages of high voltage resistance and low conduction loss, but also has the advantages of high switching frequency. It is considered to be the core device of the future, especially in the field of new energy vehicles, and can significantly improve the driving range and charging speed of new energy vehicles. However, due to the high difficulty of preparing SiC materials themselves, the cost is high, and its large-scale commercial use has been hindered due to cost issues. Therefore, the development path for its large-scale commercialization is to increase the current capacity per unit area of ​​SiC devices as much as possible and increase the power density. Utility Model Content

[0004] In view of the above problems, the utility model provides a SiC MOSFET with higher current carrying capacity, which improves the channel region length per unit area, the current carrying capacity per unit area and the power density.

[0005] The technical solution of the utility model is:

[0006] A SiC MOSFET with higher current capability includes a SiC substrate layer, a SiC drift layer, an ohmic contact alloy layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0007] A CSL region extending downward is provided on the top surface of the SiC drift layer;

[0008] The top surface of the CSL region is provided with a plurality of P-body regions extending downward at intervals; the width of the P-body region in the first region is greater than the width of the P-body region in the second region;

[0009] The top surface of the P-body region is provided with an N+ region extending downward, and a side portion of the N+ region is spaced from a side portion of the P-body region;

[0010] The N+ region of the first region is provided with a P+ region connected thereto;

[0011] The top surface of the CSL region is provided with a gate oxide layer and a Poly layer in sequence from bottom to top; the bottom surface of the gate oxide layer is connected to the CSL region, the P-body region and the N+ region respectively;

[0012] The ohmic contact alloy layer is located on the side of the gate oxide layer, and the bottom surface is connected to the top surfaces of the N+ region and the P+ region respectively; the side of the ohmic contact alloy layer is provided with an isolation dielectric layer wrapping the gate oxide layer and the Poly layer, and the bottom of the isolation dielectric layer is connected to the N+ region.

[0013] Specifically, the width of the P+ region (5) is 1.6 um.

[0014] Specifically, the depth of the CSL region (6) is greater than that of the P-body region (3) by 0.2 um.

[0015] Specifically, the deposition thickness of the Poly layer (8) is 500 nm.

[0016] The utility model adopts a unique design layout in the planar gate SiC MOSFET device, and compared with the conventional strip layout, the size of the P-body region without the P+ region is reduced, so that the conventional strip channel region is changed into a step channel region, resulting in the channel region length as the current path per unit area inside the device being increased by about 1.6um, thereby improving the current flow capacity per unit area of ​​the device and improving the power density. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a top view of the planar gate SiC MOSFET of the utility model (the CSL region 6, gate oxide layer 7, Poly layer 8, isolation dielectric layer 9, and ohmic contact alloy layer 10 are hidden in the figure);

[0018] Figure 2 yes Figure 1 Structural diagram of the AA section in the Y direction;

[0019] Figure 3 This is a top view of a planar gate SiC MOSFET with a conventional strip-shaped channel region;

[0020] Figure 4yes Figure 3 Structural diagram of the BB section in the Y direction;

[0021] In the figure, 1 is the SiC substrate layer, 2 is the SiC drift layer, 3 is the P-body region, 4 is the N+ region, 5 is the P+ region, 6 is the CSL region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the ohmic contact alloy layer, and 11 is the front electrode metal layer. DETAILED DESCRIPTION

[0022] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0023] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] A SiC MOSFET with higher current capability includes the following steps:

[0026] S100, epitaxially growing a SiC drift layer 2 on the SiC substrate layer 1, wherein the SiC substrate layer serves as a support, and the SiC drift layer serves as a reverse withstand voltage of the device and a protection;

[0027] The doping concentration of the SiC substrate layer 1 in step S100 is 1E19 cm -2 , the doping concentration of SiC drift layer 2 is 5E16-1.2E16cm -2 .

[0028] S200, after RCA cleaning, mask layer deposition, pattern lithography, and debonding cleaning, a P-body region 3 is formed on the SiC drift layer 2 by Al ion implantation in a medium beam implanter;

[0029] The doping concentration of the P-body region 3 in step S200 is 1E17-3E18cm -2 .

[0030] S300, forming a spacer layer on the SiC drift layer 2 by mask layer deposition, mask layer etching, and debonding and cleaning, and then forming an N+ region 4 by N ion implantation on a large beam implanter;

[0031] The doping concentration of N+ region 4 in step S300 is 1E18-1E19cm -2 .

[0032] S400, after RCA cleaning, mask layer deposition, pattern lithography, and debonding cleaning, a P+ region 5 is formed on the SiC drift layer 2 by Al ion implantation in a large beam implanter;

[0033] The doping concentration of the P+ region 5 in step S400 is 1E18-1E19 cm -2 , width is 1.6um.

[0034] S500 , after RCA cleaning, mask layer deposition, pattern lithography, and debonding cleaning are performed on the SiC drift layer 2 , a CSL region 6 is formed by N ion implantation in a medium beam implanter to reduce device resistance.

[0035] The doping concentration of the CSL region 6 in step S500 is 5E16-7E16cm -2 , the depth of the CSL region 6 is greater than 0.2um of the P-body region 3.

[0036] S600, after RCA cleaning, glue coating, and photoresist carbonization on the SiC drift layer 2, high-temperature ion activation is performed in an ion activation furnace to completely form all ion implantation areas;

[0037] The high temperature ion activation conditions in step S600 are a temperature of 1700° C. and a time of 15 minutes.

[0038] S700, after RCA cleaning on the SiC drift layer 2, dry oxygen oxidation is performed in a gate oxide annealing furnace to form a gate oxide layer 7, and NO annealing is introduced during the process to improve the quality of the gate oxide layer;

[0039] S800, depositing polysilicon Poly on the SiC drift layer 2 and the gate oxide layer 7 by LPCVD, and then forming the required Poly layer 8 as the gate electrode of the device by pattern lithography, etching and removing excess polysilicon Poly, and degumming and cleaning;

[0040] The thickness of the deposited Poly layer 8 in step S800 is 500 nm.

[0041] S900, after RCA cleaning on the N+ region 4 and the Poly layer 8, an oxide is deposited by PECVD method and then densified to form an isolation dielectric layer 9, which serves as a dielectric for isolating the gate electrode and the source electrode at the source of the device to avoid short circuit between the two;

[0042] S1000, forming an ohmic contact alloy layer 10 on the SiC drift layer 2 by sputtering Ni metal and then performing rapid thermal annealing;

[0043] The Ni metal sputtering thickness in step S1000 is 100 nm, and the thermal annealing conditions are a temperature of 1000° C. and a time of 5 minutes.

[0044] S1100, an electrode is formed on the top of the device by sputtering Ti / AlCu metal, and then a front electrode metal layer 11 is formed by patterning, etching, degumming and cleaning.

[0045] The sputtering thickness of Ti / AlCu metal in step S1100 is 100nm / 5000nm.

[0046] A SiC MOSFET with higher current carrying capacity comprises a SiC substrate layer 1, a SiC drift layer 2, an ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top;

[0047] The top surface of the SiC drift layer 2 is provided with a CSL region 6 extending downward;

[0048] The top surface of the CSL region 6 is provided with a plurality of P-body regions 3 extending downward at intervals, and a gap is provided between the bottom surface of the P-body region 3 and the bottom surface of the N+ region 4; the width of the P-body region 3 in the first region is greater than the width of the P-body region 3 in the second region;

[0049] The top surface of the P-body region 3 is provided with an N+ region 4 extending downward, and a gap is provided between the side of the N+ region 4 and the side of the P-body region 3; the space between the N+ region 4 and the P-body region 3 is a channel region;

[0050] A P+ region 5 connected to the N+ region 4 is provided in the middle of the first region, and the depth of the P+ region 5 is greater than the depth of the N+ region 4;

[0051] The top surface of the CSL region 6 is provided with a gate oxide layer 7 and a Poly layer 8 in sequence from bottom to top; the bottom surface of the gate oxide layer 7 is connected to the CSL region 6, the P-body region 3 and the N+ region 4 respectively;

[0052] The ohmic contact alloy layer 10 is located on the side of the gate oxide layer 7, and the bottom surface is connected to the top surface of the N+ region 4 and the P+ region 5 respectively; the side of the ohmic contact alloy layer 10 is provided with an isolation dielectric layer 9 that wraps the gate oxide layer 7 and the Poly layer 8, and the bottom of the isolation dielectric layer 9 is connected to the N+ region 4.

[0053] The utility model has the beneficial effects of increasing the current channel area of ​​the device and improving the current carrying capacity of the device.

[0054] In a planar gate SiC MOSFET device, since the P+ regions in the P-body region are usually arranged at intervals, the present invention reduces the size of the P-body region 3 without the P+ region, and changes the SiC MOSFET originally having a strip-shaped channel region into a step-shaped channel region ( Figure 1 The elliptical dotted area in the middle increases the channel length per unit area of ​​the SiC MOSFET by about 1.6um, which significantly improves the current carrying capacity and power density of the device. Figure 2 The downward arrow in the middle trench region indicates the movement direction of the holes in the P region of the device during the follow-up process.

Claims

1. SiC MOSFET with higher current capability, characterized by: It comprises a SiC substrate layer (1), a SiC drift layer (2), an ohmic contact alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The top surface of the SiC drift layer (2) is provided with a CSL region (6) extending downward; The top surface of the CSL region (6) is provided with a plurality of P-body regions (3) extending downward at intervals; the width of the P-body region (3) in the first region is greater than the width of the P-body region (3) in the second region; The top surface of the P-body region (3) is provided with an N+ region (4) extending downward, and a gap is provided between the side of the N+ region (4) and the side of the P-body region (3); A P+ region (5) connected to the N+ region (4) of the first region is provided in the N+ region (4) thereof; The top surface of the CSL region (6) is provided with a gate oxide layer (7) and a Poly layer (8) in sequence from bottom to top; the bottom surface of the gate oxide layer (7) is connected to the CSL region (6), the P-body region (3) and the N+ region (4) respectively; The ohmic contact alloy layer (10) is located on the side of the gate oxide layer (7), and the bottom surface is connected to the top surfaces of the N+ region (4) and the P+ region (5) respectively; the side of the ohmic contact alloy layer (10) is provided with an isolation dielectric layer (9) that wraps the gate oxide layer (7) and the Poly layer (8), and the bottom of the isolation dielectric layer (9) is connected to the N+ region (4).

2. The SiC MOSFET with higher current carrying capacity according to claim 1, characterized in that: The width of the P+ region (5) is 1.6 um.

3. The SiC MOSFET with higher current carrying capacity according to claim 1, characterized in that: The depth of the CSL region (6) is 0.2 um greater than that of the P-body region (3).

4. The SiC MOSFET with higher current carrying capacity according to claim 1, characterized in that: The deposition thickness of the Poly layer (8) is 500 nm.

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