Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a substrate structure; the source electrode structure is positioned on one side of the substrate structure; the drain electrode structure and the source electrode structure are arranged in a stacked mode; the grid electrode structure is located between the source electrode structure and the drain electrode structure, and the grid electrode structure comprises a plurality of grid electrode parts; the isolation structures are located between the adjacent gate parts; the channel layer is located in the gate structure, one end of the channel layer is in contact with the source electrode structure, and the other end of the channel layer is in contact with the drain electrode structure; and the bonding layer is positioned between the gate structure and the isolation structure and conformally covers the side wall of the gate structure. The problem of poor interface adhesion between a gate structure and an isolation structure in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular, to a semiconductor device. Background Art

[0002] In semiconductor devices, the interface adhesion between the gate structure and the isolation structure is poor, which leads to device failure. Therefore, there is an urgent need for a semiconductor device with good interface adhesion between the gate structure and the isolation structure. Utility Model Content

[0003] The main purpose of the present application is to provide a semiconductor device to solve the problem of poor interface adhesion between a gate structure and an isolation structure in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, including: a substrate structure; a source structure, located on one side of the substrate structure; a drain structure, stacked with the source structure; a gate structure, located between the source structure and the drain structure, the gate structure including a plurality of gate parts; an isolation structure, located between adjacent gate parts; a channel layer, located in the gate structure, wherein one end of the channel layer is in contact with the source structure, and the other end of the channel layer is in contact with the drain structure; an adhesive layer, located between the gate structure and the isolation structure, conformally covering the sidewalls of the gate structure.

[0005] Furthermore, the isolation structure between two adjacent gate portions is in contact with the source structure.

[0006] Furthermore, the adhesive layer directly contacts the upper surface of the source structure.

[0007] Furthermore, there is a gap between the adhesive layer and the source structure, and the isolation structure is located on the gap.

[0008] Furthermore, the adhesive layer directly contacts the lower surface of the isolation structure.

[0009] By applying the technical solution of the present application, an adhesive layer is provided between the gate structure and the isolation structure, and the gate structure and the isolation structure are bonded together by the adhesive layer, thereby solving the problem of poor interface adhesion between the gate structure and the isolation structure in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0011] Figure 1A cross-sectional schematic diagram of a semiconductor device provided according to an embodiment of the present application is shown;

[0012] Figure 2 A cross-sectional schematic diagram of another semiconductor device provided according to an embodiment of the present application is shown;

[0013] Figure 3 A cross-sectional schematic diagram of another semiconductor device provided according to an embodiment of the present application is shown;

[0014] Figures 4 to 20 A cross-sectional schematic diagram of corresponding steps of a semiconductor device preparation process provided according to an embodiment of the present application is shown.

[0015] The above drawings include the following reference numerals:

[0016] 10. Base structure; 101. First metal layer; 102. First isolation layer; 103. Metal part; 104. First metal protection layer; 20. Source structure; 201. Second metal protection layer; 202. Source metal layer; 203. Third metal protection layer; 204. Semiconductor material layer; 30. Isolation structure; 40. Gate part; 401. Fourth metal protection layer; 402. Gate metal layer; 501. First sacrificial layer; 502. Second sacrificial layer; 503. Barrier layer; 60. Adhesive layer; 701. Third oxide layer; 702. Second oxide layer; 703. First oxide layer; 801. Channel layer; 90. Drain part; 901. Fifth metal protection layer; 902. Drain metal layer. DETAILED DESCRIPTION

[0017] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0018] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0019] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0020] As introduced in the background art, the interface adhesion between the existing gate structure and the isolation structure is poor. In order to solve the above technical problems, the present application proposes a semiconductor device.

[0021] Figure 1 Schematic cross-sectional view of the semiconductor device provided in this embodiment. Figure 1 As shown, this embodiment provides a semiconductor device, including:

[0022] Base structure 10;

[0023] Specifically, the base structure 10 includes a first metal layer 101 and a first isolation layer 102 stacked in sequence, wherein the first isolation layer 102 is provided with a metal part 103 and a first metal protection layer 104, the first metal layer 101 can be used as the substrate of the semiconductor device, one end of the metal part 103 is connected to the first metal layer 101, and the other end is connected to the source structure 20, so it can be used as an electrical connector, such as a terminal, and the material of the metal part 103 can be a metal material with conductive properties. The first metal protection layer 104 is used to protect the metal part 103, and can be made of at least one of a nitride material and an oxide material, such as ruthenium dioxide, rhenium trioxide, cadmium oxide, iridium dioxide, chromium dioxide, tin dioxide, indium oxide, germanium oxide, zinc oxide, titanium nitride, tantalum nitride, tungsten nitride, and titanium silicon nitride. The first isolation layer 102 is used to isolate the first metal layer 101 from the source structure 20. The first isolation layer 102 may be a single-layer structure or a multi-layer structure. The material of the first isolation layer 102 may be at least one of an oxide material and a nitride material.

[0024] The source structure 20 is located on one side of the substrate structure 10;

[0025] Specifically, the source structure 20 includes a second metal protection layer 201, a source metal layer 202, a third metal protection layer 203 and a semiconductor material layer 204 stacked in sequence from bottom to top. The second metal protection layer 201 and the third metal protection layer 203 are located on both sides of the source metal layer 202, and protect the source metal layer 202 from two directions respectively. The materials of the second metal protection layer 201 and the third metal protection layer 203 can be at least one of nitride materials and oxide materials, and the materials of the second metal protection layer 201 and the third metal protection layer 203 can be the same as or different from the materials of the first metal protection layer 104. The material of the source metal layer 202 can be a source metal material, such as ruthenium, rhodium, iridium, palladium, platinum, cobalt, palladium, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, nickel, lead, etc. The material of the semiconductor material layer 204 can be at least one of silicon, silicon carbide, silicon germanium compound, oxide semiconductor material, nitride semiconductor material and oxynitride semiconductor material.

[0026] A drain structure, stacked with the source structure 20;

[0027] Specifically, the drain structure may have a plurality of drain portions 90, which are arranged at intervals on a side of the source structure 20 away from the substrate structure 10. The drain portion 90 includes a fifth metal protection layer 901 and a drain metal layer 902 stacked in sequence from bottom to top. The fifth metal protection layer 901 is used to protect the drain metal layer 902. The material of the fifth metal protection layer 901 may be at least one of a nitride material and an oxide material. The material of the fifth metal protection layer 901 may be the same as or different from the first metal protection layer 104, the second metal protection layer 201, and the third metal protection layer 203. The material of the drain metal layer 902 may be a drain metal material, such as ruthenium, rhodium, iridium, palladium, platinum, cobalt, palladium, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, nickel, lead, etc. The material of the drain metal layer 902 may be the same as or different from the material of the source metal layer 202.

[0028] A gate structure, located between the source structure 20 and the drain structure, the gate structure comprising a plurality of gate portions 40;

[0029] Specifically, the number of the gate portions 40 may be the same as the number of the drain portions 90, and the positions are arranged one by one. The gate portion 40 includes a fourth metal protection layer 401 and a gate metal layer 402 stacked from bottom to top, wherein the material of the fourth metal protection layer 401 may be at least one of a nitride material and an oxide material, and the material of the fourth metal protection layer 401 may be the same as or different from the first metal protection layer 104, the second metal protection layer 201, the third metal protection layer 203 and the fifth metal protection layer 901. The material of the gate metal layer 402 may be a gate metal material, for example: ruthenium, rhodium, iridium, palladium, platinum, cobalt, palladium, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, nickel, lead, etc. The material of the gate metal layer 402 may be the same as or different from the material of the source metal layer 202 and the drain metal layer 902.

[0030] An isolation structure 30 located between adjacent gate portions 40;

[0031] Specifically, the isolation structure 30 may include a plurality of parts, a part between the gate portion 40 and the source structure 20 is used to isolate the gate structure from the source structure 20, and a part between the gate portion 40 and the drain structure is used to isolate the gate structure from the drain structure. The material of the isolation structure 30 may include at least one of a low-k dielectric material, a high-k dielectric material, an oxide material, a nitride material, an oxynitride material, and a carbon oxynitride silicon material, wherein the low-k dielectric material may include one or more of a flowable oxide, thohn silicon nitride, undoped silica glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, plasma-enhanced tetraethyl orthosilicate, fluorosilicic acid, salt glass, high-density plasma oxide, plasma-enhanced oxide, or a flowable CVD oxide; the high-k dielectric material may include one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, and carbon oxynitride silicon.

[0032] A channel layer 801 is located in the gate structure, wherein one end of the channel layer 801 contacts the source structure 20, and the other end of the channel layer 801 contacts the drain structure;

[0033] Specifically, the channel layer 801 is located between adjacent gate portions 40, presenting a "U"-shaped structure, with the first end in contact with the source structure 20, and the second and third ends in contact with the same drain portion 90. The material of the channel layer 801 may be one or more of polysilicon material, metal silicide material, ferroelectric material, high-k dielectric material and indium gallium zinc oxide, wherein the polysilicon has doped ions, and the doped ions may include one or more of fluorine, boron, phosphorus, arsenic, germanium, indium, aluminum, titanium, cobalt and nickel, and the metal silicide material may be cobalt silicide, titanium silicide, tungsten silicide, and nickel silicide. The ferroelectric material may include at least one of an oxide ferroelectric material, a polymer ferroelectric material, a fluoride ferroelectric material and a ferroelectric semiconductor. A first oxide layer 703 and a barrier layer 503 are stacked in sequence from bottom to top between the channel layer 801 and the drain electrode 90, wherein the bottom surface of the first oxide layer 703 contacts the channel layer 801, and the top surface of the barrier layer 503 contacts the drain electrode 90. The material of the first oxide layer 703 can be at least one of an oxide material, an oxynitride material, and a oxycarbon silicon material, and can be the same material as the isolation structure. The material of the barrier layer 503 can be at least one of a semiconductor material, a metal material, and a metal silicide material.

[0034] The adhesive layer 60 is located between the gate structure and the isolation structure 30 , and conformally covers the sidewall of the gate structure.

[0035] Specifically, the adhesive layer 60 covering the sidewall of the gate structure is used to bond the gate structure and the isolation structure 30. In addition, the adhesive layer 60 is also located on the sidewall of the drain portion 90. The material of the adhesive layer 60 can be nitride, such as titanium nitride, tungsten nitride and silicon nitride. A third oxide layer 701 is also included between the isolation structure 30 and the adhesive layer 60. The material of the third oxide layer 701 can be at least one of an oxide material, an oxynitride material and an oxycarbon silicon nitride material.

[0036] In an embodiment of the present application, a semiconductor device includes: a substrate structure; a source structure, located on one side of the substrate structure; a drain structure, stacked with the source structure; a gate structure, located between the source structure and the drain structure, the gate structure including a plurality of gate parts; an isolation structure, located between adjacent gate parts; a channel layer, located in the gate structure, wherein one end of the channel layer contacts the source structure, and the other end of the channel layer contacts the drain structure; an adhesive layer, located between the gate structure and the isolation structure, conformally covering the sidewall of the gate structure. By arranging an adhesive layer between the gate structure and the isolation structure, and bonding the gate structure and the isolation structure through the adhesive layer, the problem of poor interface adhesion between the gate structure and the isolation structure in the prior art is solved.

[0037] In another embodiment, Figure 1 As shown, the isolation structure 30 between two adjacent gate portions 40 is in contact with the source structure 20 .

[0038] In fact, the isolation structure between two adjacent gate portions is in direct contact with the semiconductor material layer in the source structure.

[0039] In another embodiment, Figure 1 As shown, the adhesive layer 60 directly contacts the upper surface of the source structure 20 .

[0040] Specifically, the adhesive layer is in direct contact with the semiconductor material layer in the source structure.

[0041] In another embodiment, Figure 2 As shown, there is a gap between the adhesive layer 60 and the source structure 20, and the isolation structure 30 is located on the gap. The above structural arrangement can further improve the isolation effect between the source structure and the gate structure without affecting the adhesive effect of the adhesive layer.

[0042] Specifically, the isolation structure is used to isolate the bonding layer and the semiconductor material layer in the source structure.

[0043] In another embodiment, Figure 3 As shown, the adhesive layer 60 directly contacts the lower surface of the isolation structure 30. The above structural arrangement further increases the contact surface area of ​​the adhesive layer, thereby further improving the bonding effect of the adhesive layer.

[0044] Specifically, the isolation structure includes two parts, one part is located at the upper part of the adhesive layer, and the other part is located at the lower part of the adhesive layer. The adhesive layer forms a "U"-shaped structure, and the groove part at the top of the "U"-shaped structure is in direct contact with the lower surface of the isolation structure located at the upper part of the adhesive layer, and the bottom of the "U"-shaped structure is not in direct contact with the source structure, but is in contact with the upper surface of the isolation structure located at the lower part of the adhesive layer.

[0045] Figures 4 to 20 The cross-sectional schematic diagram of the corresponding steps of the preparation process of the semiconductor device provided in this embodiment is shown below in combination with Figures 4 to 20 The preparation process of the semiconductor device provided in this embodiment is described in detail.

[0046] Step S1: Provide a base structure 10, and sequentially form a source structure 20, an isolation structure 30, a fourth metal protection layer 401, a gate metal layer 402, and a first sacrificial layer 501 on one side of the base structure 10, wherein the base structure comprises a first metal layer 101 and a first isolation layer 102 stacked in sequence, wherein the first isolation layer 102 is provided with a metal portion 103 and a first metal protection layer 104, the first metal layer 101 can be used as a substrate of the semiconductor device, one end of the metal portion 103 is connected to the first metal layer 101, and the other end is connected to the source structure 20. The source structure 20 comprises a second metal protection layer 201, a source metal layer 202, a third metal protection layer 203, and a semiconductor material layer 204 stacked in sequence from bottom to top, and the source structure 20 is obtained as follows. Figure 4 The structure shown.

[0047] Specifically, the metal part can be used as an electrical connector, such as a terminal, and the material of the metal part can be a metal material with conductive properties. The first metal protective layer is used to protect the metal part, and can use at least one of a nitride material and an oxide material, such as ruthenium dioxide, rhenium trioxide, cadmium oxide, iridium dioxide, chromium dioxide, tin dioxide, indium oxide, germanium oxide, zinc oxide, titanium nitride, tantalum nitride, tungsten nitride, and titanium silicon nitride. The first isolation layer is used to isolate the first metal layer and the source structure, and the first isolation layer can be a single-layer structure or a multi-layer structure. The material of the first isolation layer can be at least one of an oxide material and a nitride material. The second metal protective layer and the third metal protective layer are located on both sides of the source metal layer, respectively protecting the source metal layer from two directions, and the materials of the second metal protective layer and the third metal protective layer can be at least one of a nitride material and an oxide material, and the materials of the second metal protective layer and the third metal protective layer can be the same as or different from the materials of the first metal protective layer. The material of the source metal layer may be a source metal material, such as ruthenium, rhodium, iridium, palladium, platinum, cobalt, palladium, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, nickel, lead, etc. The material of the semiconductor material layer may be at least one of silicon, silicon carbide, silicon germanium compound, oxide semiconductor material, nitride semiconductor material and oxynitride semiconductor material. The material of the isolation structure may include at least one of low-k dielectric material, high-k dielectric material, oxide material, nitride material, oxynitride material and oxynitride carbon silicon material. The material of the fourth metal protection layer may be at least one of nitride material and oxide material, and the material of the gate metal layer may be a gate metal material, such as ruthenium, rhodium, iridium, palladium, platinum, cobalt, palladium, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, nickel, lead, etc. The material of the first sacrificial layer may be any mask material in the prior art.

[0048] Step S2: removing the first sacrificial layer 501, the gate metal layer 402, the fourth metal protection layer 401 and the isolation structure 30, so that a portion of the surface of the source structure 20 is exposed, and the remaining gate metal layer 402 and the remaining fourth metal protection layer 401 form a plurality of gate portions 40 with intervals, so as to obtain Figure 5 The structure shown.

[0049] Specifically, the first sacrificial layer, the gate metal layer, the fourth metal protection layer and the isolation structure can be removed in sequence by etching. During the etching process, the isolation structure between two adjacent gate portions can be retained or completely etched away to expose the surface of the source structure.

[0050] Step S3: forming an adhesive layer 60 on the exposed surface of the structure formed in step S2, so as to obtain Figure 6 The structure shown.

[0051] Specifically, the material of the adhesive layer may be nitride, such as titanium nitride, tungsten nitride and silicon nitride. In addition, the adhesive layer 60 may be further etched to expose a portion of the surface of the source structure 20, such as Figure 7 shown.

[0052] Step S4: forming a third oxide layer 701 on the exposed surface of the structure obtained in step S3, wherein the third oxide layer 701 completely fills the gap between two adjacent gate portions 40 in the structure obtained in step S3, so as to obtain Figure 8 The structure shown.

[0053] Specifically, the material of the third oxide layer may be at least one of an oxide material, an oxynitride material, and an oxycarbon silicon nitride material.

[0054] Step S5: forming an isolation structure 30 on the exposed surface of the structure obtained in step S4, so as to obtain Fig. 9 The structure shown.

[0055] Specifically, the material of the isolation structure may include at least one of a low-k dielectric material, a high-k dielectric material, an oxide material, a nitride material, an oxynitride material, and a silicon oxynitride material.

[0056] Step S6: removing the first sacrificial layer 501 and a portion of the isolation structure 30, a portion of the third oxide layer 701 and a portion of the adhesive layer 60 to expose the surface of the gate metal layer 402, thereby obtaining Fig.10 The structure shown.

[0057] Specifically, the surfaces of the remaining isolation structure, the remaining third oxide layer and the remaining adhesion layer away from the substrate structure are located on the same horizontal plane as the exposed surface of the gate metal layer.

[0058] Step S7: sequentially remove a portion of the isolation structure 30, the gate metal layer 402 and the fourth metal protection layer 401 to expose a portion of the surface of the isolation structure 30 to form a groove, thereby obtaining Fig.11 The structure shown.

[0059] Specifically, the isolation structure, the gate metal layer and the fourth metal protection layer may be removed by etching.

[0060] Step S8: forming a second oxide layer 702 on the exposed surface of the structure obtained in step S7, and obtaining Fig.12 The structure shown.

[0061] Specifically, the material of the second oxide layer may be at least one of an oxide material, an oxynitride material, and an oxycarbon silicon nitride material.

[0062] Step S9: forming a channel layer 801 on the exposed surface of the structure obtained in step S8, and obtaining Fig.13 The structure shown.

[0063] Specifically, the material of the channel layer may be one or more of polysilicon material, metal silicide material, ferroelectric material, high-k dielectric material and indium gallium zinc oxide, wherein the polysilicon has doped ions, and the doped ions may include one or more of fluorine, boron, phosphorus, arsenic, germanium, indium, aluminum, titanium, cobalt and nickel, and the metal silicide material may be cobalt silicide, titanium silicide, tungsten silicide, nickel silicide. The ferroelectric material may include at least one of oxide ferroelectric material, polymer ferroelectric material, fluoride ferroelectric material and ferroelectric semiconductor.

[0064] Step S10: removing the channel layer 801 on the side of the second oxide layer 702 away from the isolation structure 30 to expose the surface of the isolation structure, and removing the channel layer 801, the third oxide layer 701 and the isolation structure 30 in the groove to expose part of the surface of the semiconductor material layer, thereby obtaining Fig.14 The structure shown.

[0065] Step S11: forming a channel layer 801 on the exposed surface of the structure obtained in step S10, and obtaining Fig.15 The structure shown.

[0066] Step S12: forming a first oxide layer 703 in the groove between two adjacent gate portions 40, so as to obtain Fig.16 The structure shown.

[0067] Specifically, the material of the first oxide layer may be at least one of an oxide material, an oxynitride material, and an oxycarbon silicon nitride material.

[0068] Step S13: forming a barrier layer 503 on the surface of the first oxide layer 703 away from the substrate structure 10, so as to obtain Fig.17 The structure shown.

[0069] Specifically, the material of the barrier layer may be at least one of a semiconductor material, a metal material and a metal silicide material.

[0070] Step S14: forming a fifth metal protection layer 901, a drain metal layer 902 and a second sacrificial layer 502 in sequence on the exposed surface of the structure formed in step S13, so as to obtain Fig.18 The structure shown.

[0071] Specifically, the material of the second sacrificial layer can be a mask material in the prior art. The material of the fifth metal protection layer can be at least one of a nitride material and an oxide material, and the material of the drain metal layer can be a gate metal material, such as ruthenium, rhodium, iridium, palladium, platinum, cobalt, palladium, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, nickel, lead, etc.

[0072] Step S15: sequentially remove a portion of the second sacrificial layer 502, a portion of the drain metal layer 902, and a portion of the fifth metal protection layer 901 to expose a portion of the surface of the isolation structure 30, thereby obtaining Fig.19 The structure shown.

[0073] Step S16: forming an adhesive layer 60 on the sidewalls of the remaining fifth metal protection layer 901, the drain metal layer 902 and the second sacrificial layer 502, so as to obtain Fig. 20 The structure shown.

[0074] Step S17: removing the second sacrificial layer 502 to expose the surface of the drain metal layer 902, thereby obtaining Figure 1 The structure shown.

[0075] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0076] The semiconductor device of the present application includes: a substrate structure; a source structure, located on one side of the substrate structure; a drain structure, stacked with the source structure; a gate structure, located between the source structure and the drain structure, the gate structure including a plurality of gate parts; an isolation structure, located between adjacent gate parts; a channel layer, located in the gate structure, wherein one end of the channel layer contacts the source structure, and the other end of the channel layer contacts the drain structure; an adhesive layer, located between the gate structure and the isolation structure, conformally covering the sidewall of the gate structure. By arranging an adhesive layer between the gate structure and the isolation structure, and bonding the gate structure and the isolation structure through the adhesive layer, the problem of poor interface adhesion between the gate structure and the isolation structure in the prior art is solved.

[0077] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: Base structure; A source structure, located on one side of the base structure; A drain structure, stacked with the source structure; A gate structure, located between the source structure and the drain structure, the gate structure comprising a plurality of gate portions; An isolation structure, located between adjacent gate portions; A channel layer is located in the gate structure, wherein one end of the channel layer contacts the source structure, and the other end of the channel layer contacts the drain structure; The adhesive layer is located between the gate structure and the isolation structure and conformally covers the sidewall of the gate structure.

2. The semiconductor device according to claim 1, wherein: The isolation structure between two adjacent gate portions is in contact with the source structure.

3. The semiconductor device according to claim 2, characterized in that The adhesive layer directly contacts an upper surface of the source structure.

4. The semiconductor device according to claim 2, characterized in that There is a gap between the adhesive layer and the source structure, and the isolation structure is located on the gap.

5. The semiconductor device according to claim 4, characterized in that The adhesive layer directly contacts the lower surface of the isolation structure.

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