Semiconductor device

Abstract

Some embodiments of the present disclosure provide a semiconductor device. A semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed over the semiconductor substrate. A trench is formed in the semiconductor substrate and adjacent to the gate structure. The semiconductor substrate is formed with a trench bottom surface below the trench. The trench bottom surface includes a plurality of spaced apart protrusions separated by a plurality of grooves, each of the protrusions having an uppermost surface. An uppermost surface of the protrusion closer to the gate structure is located at a depth deeper than an uppermost surface of the protrusion at a center of the trench. The dielectric material is located in the trench.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements on the material layers.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Utility Model Content

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed above a semiconductor substrate. The trench is formed in the semiconductor substrate and is adjacent to the gate structure. The semiconductor substrate has a trench bottom surface formed below the trench. The trench bottom surface includes a plurality of spaced-apart protrusions, the protrusions being separated by a plurality of grooves, each of the protrusions having an uppermost surface. The uppermost surface of the protrusion closer to the gate structure is located at a deeper depth than the uppermost surface of the protrusion at the center of the trench. The dielectric material is located in the trench.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed above a semiconductor substrate. The trench is formed in the semiconductor substrate and is adjacent to the gate structure. The semiconductor substrate has a trench bottom surface formed below the trench. The trench bottom surface includes a plurality of spaced-apart protrusions, the protrusions being separated by a plurality of grooves, each of the protrusions having an uppermost surface. The uppermost surface of the protrusion closer to the gate structure is located at a deeper depth than the uppermost surface of the protrusion at the center of the trench. The trench is arched and the uppermost surface of the protrusion defines a crown-shaped profile. The dielectric material is located in the trench.

[0006] According to some embodiments of the present disclosure, a semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed above a semiconductor substrate. The trench is formed in the semiconductor substrate and is adjacent to the gate structure. The semiconductor substrate has a trench bottom surface formed below the trench. The trench bottom surface includes a plurality of spaced-apart protrusions, the protrusions being separated by a plurality of grooves, each of the protrusions having an uppermost surface. The uppermost surface of the protrusion closer to the gate structure is located at a deeper depth than the uppermost surface of the protrusion at the center of the trench. The vertical depth of the uppermost surface of one of the protrusions closer to the gate structure measured from the top surface of the gate structure is more than twice the vertical depth of the uppermost surface of one of the protrusions at the center of the trench measured from the top surface of the gate structure. The dielectric material is located in the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of some embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a plan view of a layout of a multi-gate device according to some embodiments;

[0009] Figures 2 to 13 is a diagram of a multi-gate device during successive manufacturing stages according to some embodiments, wherein according to some embodiments, Figure 2 , Figure 5 , Figure 8 and Fig.11 is a perspective diagram of the successive stages, where Figure 3 , Figure 6 , Fig. 9 and Fig.12 is a cross-sectional view taken along the X-axis of the multi-gate device of the aforementioned perspective view, and Figure 4 , Figure 7 , Fig.10 and Fig.13 A Y-axis cut-away cross-sectional view of the multi-gate device of the aforementioned perspective view;

[0010] Fig.14 According to some embodiments, Fig.13 , but with a Y-axis cut cross-sectional view of a multi-gate device having larger trenches and a greater number of fins and isolation regions;

[0011] Fig.15 According to some embodiments Fig.14 A Y-axis cut cross-sectional view of a multi-gate device after an etching process;

[0012] Fig.16 According to some embodiments Fig.15A Y-axis cut cross-sectional view of a multi-gate device after a deposition process;

[0013] Fig.17 is a TEM view cut along the Y-axis of a multi-gate device according to some embodiments, which illustrates the etching depth of the etching process;

[0014] Fig.18 According to some embodiments Fig.15 TEM image of a cross-sectional view of a multi-gate device cut along the X-axis;

[0015] Fig.19 A flow chart illustrating a method according to some embodiments.

[0016]

Explanation of symbols

[0017] 3, 4: Line

[0018] 10:Substrate

[0019] 11: Lattice unit

[0020] 20: Active Zone

[0021] 30: Gate line

[0022] 40: Isolation

[0023] 100: Installation

[0024] 101, 102: Installation area

[0025] 205, 500: fins

[0026] 206: Virtual fin

[0027] 208: Isolation and insulation area

[0028] 210: Source / drain epitaxial region

[0029] 215: Sidewall spacer

[0030] 220:Metal gate

[0031] 221: Gate dielectric layer

[0032] 222: Work function metal layer

[0033] 223:Metal gate electrode layer

[0034] 225: Gate electrode layer

[0035] 230: Interlayer dielectric (ILD) layer

[0036] 235, 240: Hard mask

[0037] 301: Bottom

[0038] 302: Middle layer

[0039] 303: Photoresist layer

[0040] 305: Opening

[0041] 400: Groove

[0042] 401, 402: side wall

[0043] 410: Bottom groove surface

[0044] 491: First end wall

[0045] 492: Second end wall

[0046] 501, 502: fins

[0047] 511: District 1

[0048] 512: District 2

[0049] 513: Central Area

[0050] 600: Isolation Zone

[0051] 601, 602: terminal isolation layer section

[0052] 611, 612: middle isolation layer section

[0053] 700: Arrow

[0054] 810: protrusion

[0055] 811: Surface

[0056] 815: Outline

[0057] 820: Groove

[0058] 821: lowest surface

[0059] 850: Isolation Structure

[0060] 900, 910, 920: plane

[0061] 1000:Method

[0062] 1~9、10'~1': protrusion

[0063] 1~10, 10'~1': Groove

[0064] a: Gate height

[0065] b, c: Depth

[0066] d, e: critical size

[0067] f: maximum width

[0068] g: distance (height)

[0069] DP, DR: Depth

[0070] S11, S12, S13, S14, S15, S16, S17: Steps

[0071] X, Y: direction DETAILED DESCRIPTION

[0072] The following disclosure provides many different embodiments or examples for realizing the different features of the subject matter. The specific examples of components and configurations described below are to simplify some embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly in contact. In addition, some embodiments of the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0073] Additionally, for ease of description, spatially relative terms such as "above," "overlying," "above," "upper," "top," "below," "underlying," "under," "below," "bottom," "side," and the like may be used in some embodiments of the present disclosure to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure may likewise be interpreted accordingly.

[0074] In some embodiments of the present disclosure, a "material structure" is a structure that includes at least 50% by weight of an identified material (e.g., at least 60% by weight of an identified material, at least 75% by weight of an identified material, at least 90% by weight of an identified material, at least 95% by weight of an identified material, or at least 99% by weight of an identified material); and is a structure formed of a "material" that includes at least 50% by weight of an identified material (e.g., at least 60% by weight of an identified material, at least 75% by weight of an identified material, at least 90% by weight of an identified material, at least 95% by weight of an identified material, or at least 99% by weight of an identified material). For example, in certain embodiments, each of a tungsten structure and a structure formed of tungsten is a structure that is at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of tungsten.

[0075] For the sake of brevity, typical techniques related to the manufacture of semiconductor devices may not be described in detail in some embodiments of the present disclosure. In addition, the various tasks and processes described in some embodiments of the present disclosure may be incorporated into a more comprehensive program or process with additional functionality that is not described in detail in some embodiments of the present disclosure. In particular, the various processes for manufacturing semiconductor devices are well known, and therefore, for the sake of brevity, many typical processes will only be briefly mentioned in some embodiments of the present disclosure or will be completely omitted without providing familiar process details. As will be readily apparent to those familiar with the art after a complete reading of some embodiments of the present disclosure, the structures disclosed in some embodiments of the present disclosure can be adopted together with various technologies and can be incorporated into various semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes different numbers of components, and a single component shown in the description can represent multiple components.

[0076] Some embodiments of the present disclosure present embodiments of semiconductor devices and embodiments of methods for manufacturing such devices. The methods described in some embodiments of the present disclosure can be easily integrated into current process flows. In addition, the methods described in some embodiments of the present disclosure are related to forming an insulating structure that insulates adjacent devices from each other, such as a Continuous Poly On Diffusion Edge (CPODE) structure. In some embodiments, a portion of one or more selected fins is removed and replaced with an insulating material.

[0077] In some embodiments, a continuous poly on diffusion edge (CPODE) process is used to provide an isolation structure between adjacent devices. For the purposes of some embodiments of the present disclosure, a "diffusion edge" may be equivalently referred to as an active edge, where, for example, the active edge is adjacent to an adjacent active region. In addition, the active region includes a region where a transistor structure (e.g., including a source, a drain, and a gate / channel structure) is formed. In some instances, the active region may be disposed between insulating regions. The CPODE process may provide an isolation structure between adjacent active regions by performing a plasma etching process along the active edge (e.g., at the boundary of adjacent active regions) to form a cut region and by filling the cut region with a dielectric such as silicon nitride (SiN), and thereby providing adjacent transistors.

[0078] In some embodiments of the present disclosure, the CPODE final treatment method (i.e., after metal gate formation) achieves high overlay tolerance through self-aligned structures. In addition, the CPODE final treatment method provides lower epitaxial layer stress, especially when compared to the CPODE first treatment that is subjected to epitaxial stress relief during the etching process.

[0079] Some embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, but not all advantages must be discussed in some embodiments of the present disclosure, and not all embodiments require a particular advantage.

[0080] For the purpose of the following discussion, Figure 1 A simplified top-down layout diagram of a semiconductor device 100, such as a multi-gate device 100, is provided. In various embodiments, the multi-gate device 100 may include a FinFET device, a GAA transistor, or other types of multi-gate devices. The multi-gate device 100 is formed over a substrate 10. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate.

[0081] Figure 1 A lattice cell 11 is illustrated, i.e., a portion of a semiconductor substrate 10. As shown, parallel active regions 20 are spaced apart from each other and extend in the X direction. Additionally, parallel gate lines 30 are spaced apart from each other and extend in the Y direction, which is perpendicular to the X direction. In some embodiments, exemplary gate lines 30 are formed of a conductive material such as a metal and form a gate structure of the multi-gate device 100.

[0082] like Figure 1 As further shown in FIG. 4 , a cut region or trench is formed in one gate line 30 and filled with an isolation 40. As described below, this isolation 40 can isolate adjacent devices from each other.

[0083] refer to Fig.19, which describes a method 1000 for fabricating a semiconductor device 100 (e.g., a multi-gate device, hereinafter interchangeably referred to as multi-gate device 100) using a CPODE process according to various embodiments. The method 1000 is discussed below with reference to a FinFET device. However, it should be understood that various aspects of the method 1000 (including the disclosed CPODE process) can be equally applied to other types of multi-gate devices without departing from the scope of some embodiments of the present disclosure. In some embodiments, the method 1000 can be used to fabricate the multi-gate devices described above with reference to FIG. Figure 1 The multi-gate device 100 described above. Therefore, one or more aspects discussed above with reference to the multi-gate device 100 may also be applied to the method 1000. It should be understood that the method 1000 includes steps that are characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow, and therefore is only briefly described in some embodiments of the present disclosure. In addition, additional steps may be performed before, after, and / or during the method 1000.

[0084] Reference below Figures 2 to 15 Describes Fig.19 Method 1000, Figures 2 to 15 The semiconductor device 100 is illustrated at various stages of fabrication according to the method 1000 .

[0085] Figure 2 A perspective view illustrating a portion of an intermediate structure in forming a device 100 such as a FinFET semiconductor device, according to some embodiments. Figure 3 For along Figure 2 The cross-sectional view is taken along line 3 in FIG. 3 , that is, an X-axis cut, wherein the vertical direction is defined by the Z-axis and the lateral direction is defined by the X-axis. Figure 4 For along Figure 2 4, i.e., a Y-axis cut, wherein the vertical direction is defined by the Z-axis and the lateral direction is defined by the Y-axis. It should be understood that method 1000 includes steps characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus is only briefly described in some embodiments of the present disclosure. In addition, additional steps may be performed before, after, and / or during method 1000.

[0086] Reference Fig.19 and Figures 2 to 4 The method 1000 for manufacturing the semiconductor device 100 comprises, in step S11, providing Figures 2 to 41000. For example, method 1000 includes providing a substrate 10 for processing. In an embodiment, substrate 10 is a semiconductor substrate, which may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, a III-V material substrate (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and / or GaInAsP; or a combination thereof), or a substrate formed of other semiconductor materials having, for example, high band-to-band tunneling (BTBT). Substrate 10 may be doped or undoped. In some embodiments, substrate 10 may be a bulk semiconductor substrate, such as a bulk silicon substrate as a wafer, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like.

[0087] Method 1000 includes forming fins 205 above substrate 10, such as forming fins 205 with substrate 10. Fins 205 are patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines lithography and self-alignment processes, thereby allowing the formation of patterns having, for example, a smaller pitch than that which can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate, and the sacrificial layer is patterned using a lithography process. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0088] In some embodiments, the entire fin 205 is formed of crystalline Si. In other embodiments, at least the channel region of the fin 205 includes SiGe, wherein the Ge content is in the range of about 20 atomic % to 50 atomic %. When a SiGe channel is used, a SiGe epitaxial layer is formed over the substrate 10 and a patterning operation is performed. In some embodiments, one or more buffer semiconductor layers having a lower Ge concentration than the channel region are formed over the substrate 10.

[0089] As shown, the fins 205 extend in the X direction and are spaced apart from each other in the Y direction. In some embodiments, one or more dummy fins 206 are formed adjacent to the fins 205 of the active FinFET.

[0090] After forming the fin 205, an insulating layer of the isolation region 208 is disposed above the fin 205 and the substrate 10. In some embodiments, the isolation insulating region 208 is a "shallow-trench-isolation (STI)" layer filled with an insulating material. The insulating material of the isolation insulating region 208 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or low-k dielectric material or other suitable materials.

[0091] In some embodiments, the isolation insulating region 208 comprises one or more layers of insulating material, such as silicon dioxide, silicon oxynitride, and / or silicon nitride formed by low pressure chemical vapor deposition (LPCVD), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material is deposited instead of silicon oxide. Flowable dielectric materials, as the name implies, can "flow" during deposition to fill gaps or spaces with high aspect ratios. Typically, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicates, siloxanes, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silylamines, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multi-operation process. After the flowable film is deposited, it is cured and then annealed to remove undesirable elements, thereby forming silicon oxide. When the undesirable elements are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and / or phosphorus. In some embodiments, the isolation insulating region 208 is formed of one or more layers of SOG, SiO, SiON, SiOCN, or fluorine-doped silicate glass (FSG).

[0092] After the isolation insulating region 208 is formed above the fin 205, a planarization operation is performed to remove a portion of the isolation insulating region 208. The planarization operation may include chemical mechanical polishing (CMP) and / or an etch-back process. Subsequently, the portion of the isolation insulating region 208 extending above the top surface of the fin 205 is removed using, for example, an etching process, chemical mechanical polishing (CMP), or the like. In addition, the isolation insulating region 208 is recessed to expose the upper portion of the fin 205. In some embodiments, a single etching process or multiple etching processes are used to recess the isolation insulating region 208. In some embodiments where the isolation insulating region 208 is made of silicon oxide, the etching process is a dry etching, chemical etching, or a wet cleaning process. In some embodiments, the partial removal of the isolation insulating region 208 is performed using a wet etching process, such as by immersing the substrate in hydrofluoric acid (HF). In another embodiment, the partial removal of the isolation insulating region 208 is performed using a dry etching process. For example, a dry etching process using CHF 3 or BF 3 as an etching gas may be used.

[0093] After forming the isolation insulating region 208, a thermal process (e.g., an annealing process) may be performed to improve the quality of the isolation insulating region 208. In some embodiments, the thermal process is performed by rapid thermal annealing (RTA) at a temperature ranging from about 900° C. to about 1050° C. in an inert gas environment such as an N2, Ar, or He environment for about 1.5 seconds to about 10 seconds.

[0094] like Figures 2 to 4 As shown in FIG. , in some embodiments, the fins 205 extend in the X direction and are arranged and spaced apart at equal intervals in the Y direction.

[0095] After forming the fins 205 and the isolation insulating regions 208, a sacrificial gate structure (not shown) including a sacrificial gate dielectric layer and a sacrificial gate electrode layer is formed over the exposed fins 205, which is then used as a channel layer for the gate region. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are then used to define and form source / drain regions. In some embodiments, the sacrificial gate dielectric layer and the sacrificial gate electrode layer are formed by first depositing a sacrificial gate dielectric layer formed over the exposed fins 205 and patterning the sacrificial gate dielectric layer, and then depositing a dummy electrode layer over the sacrificial gate dielectric layer and patterning the dummy electrode layer. The sacrificial gate dielectric layer may be formed by thermal oxidation, CVD, sputtering, or any other method known and used in the art for forming a sacrificial gate dielectric layer. In some embodiments, the sacrificial gate dielectric layer is made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, SiCN, SiON, and SiN; low-k dielectrics such as carbon-doped oxides; very low-k dielectrics such as porous carbon-doped silicon dioxide; polymers such as polyimide; the like, or combinations thereof. In some embodiments, SiO2 is used.

[0096] Subsequently, a sacrificial gate electrode layer is formed over the sacrificial gate dielectric layer. In some embodiments, the sacrificial gate electrode layer is a conductive material and is selected from the group consisting of amorphous silicon, polycrystalline silicon, amorphous germanium, polycrystalline germanium, amorphous silicon germanium, polycrystalline silicon germanium, metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate electrode layer may be deposited by PVD, CVD, sputtering deposition, or other techniques known and used in the art for depositing conductive materials. Other conductive and non-conductive materials may be used. In one embodiment, polycrystalline silicon is used.

[0097] A mask pattern may be formed over the sacrificial gate electrode layer to assist in patterning. The mask pattern includes a first mask layer and a second mask layer disposed on the first mask layer. The mask pattern includes one or more layers of SiO2, SiCN, SiON, aluminum oxide, silicon nitride, or other suitable materials. In some embodiments, the first mask layer includes silicon nitride or SiON, and the second mask layer includes silicon oxide. The dummy electrode layer is patterned into a sacrificial gate electrode layer by using the mask pattern as an etching mask. In some embodiments, the dielectric layer is also patterned to define a sacrificial gate dielectric layer. The fin 205 extends in the X direction, and the sacrificial gate structure extends in the Y direction substantially perpendicular to the X direction.

[0098] In addition, sidewall spacers 215 are formed on opposite sidewalls of the sacrificial gate structure. The sidewall spacers 215 include one or more dielectric layers. In one embodiment, the sidewall spacers 215 are made of one or more of silicon oxide, silicon nitride, SiOCN, SiCN, aluminum oxide, AlCO or AlCN or any other suitable dielectric material. The blanket layer of the sidewall insulating material may be formed by CVD, PVD, ALD or other suitable techniques. Next, the sidewall insulating material is anisotropically etched to form a pair of sidewall insulating layers (sidewall spacers 215) on the two main sides of the sacrificial gate structure.

[0099] Subsequently, in some embodiments, the area of ​​the fin 205 for forming the source / drain region is recessed downward below the upper surface of the isolation insulating region 208. Next, a source / drain region 210 is formed above the recess in the fin 205. As used in some embodiments of the present disclosure, "source / drain region" may refer to a source region or a drain region, either alone or together, depending on the context. In some embodiments, each source / drain epitaxial region 210 is a merged epitaxial layer. In other embodiments, each source / drain epitaxial region 210 is formed separately above the recess in the fin 205 without merging with adjacent source / drain epitaxial regions 210.

[0100] For n-type and p-type FinFETs, the materials used for the source / drain epitaxial regions 210 may be different, such that one type of material is used for n-type FinFETs to apply tensile stress in the channel region, while another type of material is used for p-type FinFETs to apply compressive stress. For example, SiP or SiC may be used to form n-type FinFETs, while SiGe or Ge may be used to form p-type FinFETs. In some embodiments, boron (B) is doped in the source / drain epitaxial layers of the p-type FinFETs. Other materials may be used. In some embodiments, the source / drain epitaxial regions 210 include two or more epitaxial layers having different compositions and / or different dopant concentrations. The source / drain epitaxial regions 210 may be formed by CVD, ALD, molecular beam epitaxy (MBE), or any other suitable method.

[0101] After forming the source / drain epitaxial regions 210, an interlayer dielectric (ILD) layer 230 is formed. In some embodiments, before forming the ILD layer 230, an etch stop layer (ESL) is formed over the source / drain epitaxial regions 210 and the sidewall spacers 215. In some embodiments, the ESL is made of silicon nitride or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). Materials used for the ILD layer 230 include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. In some embodiments, an organic material such as a polymer is used for the ILD layer 230.

[0102] After forming the ILD layer 230 , a planarization process such as an etch-back process and / or a chemical mechanical polishing (CMP) process is performed to expose the upper surface of the sacrificial gate electrode layer.

[0103] Next, the sacrificial gate electrode layer is removed to form a gate space (not shown). A hard mask 235 may be formed over the interlayer dielectric layer 230. In some embodiments, when the sacrificial gate electrode layer is polysilicon and the ILD layer 230 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution is used to selectively remove the sacrificial gate electrode layer. In some embodiments, a suitable etching operation is then used to remove the sacrificial gate dielectric layer. In some embodiments, a portion of the fin 205 below the gate space between the source / drain regions of the fin 205 is selected and trimmed.

[0104] Then, a metal gate 220 is formed in the gate space, such as Figures 2 to 4 The metal gate 220 may include a gate dielectric layer 221 formed above the channel region of the fin 205. The metal gate 220 may further include a plurality of work function metal layers 222 formed above the gate dielectric layer 221 in the gate space. In addition, the metal gate 220 may include a metal gate electrode layer 223 formed above the work function metal layer 222.

[0105] In some embodiments, the gate dielectric layer 221 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, La2O3, HfO2-La2O3, Y2O3 or other suitable high-k dielectric materials and / or combinations thereof. High-k dielectric materials are materials having a dielectric constant (k) greater than about 3.9 (i.e., greater than silicon dioxide). The gate dielectric layer 221 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 221 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed around each channel layer.

[0106] In some embodiments, the work function metal layer 222 is made of a conductive material such as a single layer of TaN, TiN, WN, TiC, WCN, MoN, Co, TaSiN, TiAl, TiAlC, TaAl, TiAlN, and TaAlC, or a multilayer of two or more of these materials. The work function metal layer 222 can be formed by ALD, CVD, PVD, or any suitable method. In some embodiments, for n-channel FETs, aluminum-containing layers such as TiAl, TiAlC, TaAl, TiAlN, and / or TaAlC are used as n-type work function metal layers, and for p-channel FETs, one or more of TaN, TiN, WN, TiC, TaSiN, and / or Co are used as p-type work function metal layers.

[0107] In some embodiments, the gate stack structure includes two types of work function metal (WFM) layers 222: a first type WFM for forming a p-type conductivity structure and a second type WFM for forming an n-type conductivity structure.

[0108] The semiconductor device may include a p-type structure (i.e., pFET) or an n-type structure (i.e., nFET). In some embodiments, the semiconductor device includes both a pFET structure and an nFET structure on the same substrate. In some embodiments, the pFET structure includes one or more first type work function metal (p-type WFM) layers disposed over a gate dielectric layer and one or more second type work function metal (n-type WFM) layers disposed over the p-type WFM layer. In some embodiments, the nFET structure includes one or more n-type WFM layers disposed over a gate dielectric layer and one or more p-type WFM layers disposed over the n-type WFM layer. The number of WFM layers may be selected to tune the threshold voltage Vt. For example, an ultra low voltage threshold (uLVT) device may have only one p-type WFM layer, while a low voltage threshold (LVT) device has two p-type WFM layers, and a standard voltage threshold (SVT) device may have three p-type WFM layers or thicker p-type WFM layers.

[0109] The metal gate electrode layer 223 is formed above the work function metal layer 222 and fills the remaining open volume of the gate space. In some embodiments, the metal gate electrode layer 223 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof.

[0110] As shown, the method 1000 may further form a gate electrode layer 225 over the metal gate 220. The gate electrode layer 225 may include a semiconductor material such as polysilicon, amorphous silicon, or the like.

[0111] As shown, the method 1000 may include etching through the gate electrode layer 225 and the metal gate 220 to electrically separate the device region 101 from the device region 102. Specifically, such etching may land on the dummy fin 206 located between the device regions (or active FinFET regions) 101. As shown, a hard mask 240 is then deposited over the gate electrode layer 225 and extends to the dummy fin 206. In some embodiments, the hard mask 240 is silicon nitride.

[0112] Reference Fig.19 and Figures 5 to 7, method 1000 may begin a CPODE process. Specifically, in step S12, method 1000 includes forming a patterned layer over the partially fabricated device 100. As shown, a bottom layer 301, an intermediate layer 302, and a photoresist layer 303 are deposited over the partially fabricated device 100. Next, the photoresist layer 303 is processed, i.e., exposed and / or developed, to form an opening 305 over the material to be removed during the CPODE process, i.e., the selected fin 205.

[0113] exist Fig.19 and Figures 8 to 10 In step S13 , the method 1000 includes etching through the hard mask 240 and the gate electrode layer 225 ; and landing on the metal gate electrode layer 223 of the metal gate 220 .

[0114] exist Fig.19 and Figures 11 to 13 In step S14, method 1000 includes etching through metal gate electrode layer 223, work function metal layer 222 and gate dielectric layer 221 of metal gate 220 through hard mask 240. Therefore, fin 205 and isolation insulating region (e.g., STI) 208 are not covered and bottom trench surface 410 of trench 400 is formed.

[0115] Fig.14 Cut the view along the Y axis, similar to Fig.13 , but a larger trench 400 having a greater number of fins (now labeled 500) and isolation regions (now labeled 600) is illustrated, and for descriptive purposes, an underlying substrate 10 is illustrated. Fig.14 4 , the trench 400 is bounded by sidewalls 401 and 402. As shown, the trench sidewalls 401 and 402 are formed by the dummy fins 206 and the hard mask 240.

[0116] exist Fig.14 , a field of twenty fins 500 is illustrated in the trench 400; however, any suitable number of fins 500 may be disposed in the trench 400. In some embodiments, at least three fins 500 or at least four fins 500 are located in the trench 400 between the sidewall 401 and the sidewall 402.

[0117] The isolation region 600 may be considered to include an end isolation region 601 and an end isolation region 602 immediately adjacent to the trench sidewalls 401 and 402 .

[0118] Fin 500 may be considered to include end fins 501 and 502 immediately adjacent to trench sidewalls 401 and 402 , ie, separated from trench sidewalls 401 and 402 only by end isolation regions 601 and 602 .

[0119] In addition, the fin 500 and the isolation region 600 may be classified into a first region 511 adjacent to the trench sidewall 401 , a second region 512 adjacent to the trench sidewall 402 , and a central region 513 , wherein the central region 513 is located between the first region 511 and the second region 512 .

[0120] As shown, the first region 511 includes a terminal isolation layer segment 601 and a middle isolation layer segment 611 between the terminal isolation layer segment 601 and the central region 513 ; the second region 512 is formed with a terminal isolation layer segment 602 and a middle isolation layer segment 612 between the terminal isolation layer segment 602 and the central region 513 .

[0121] Therefore, method 1000 includes providing a semiconductor structure in steps S11 to S14, wherein the semiconductor structure has a first sidewall 401 away from the second sidewall 402, a fin 500 located between the first sidewall 401 and the second sidewall 402, and an isolation region 600 located between the first sidewall 401 and the second sidewall 402, wherein adjacent fins 500 are separated by respective isolation regions 600.

[0122] Cross Reference Fig.19 and Fig.15 , the method 1000 further includes performing an etching process to etch the fin 500 and the isolation region 600 in step S15. In some embodiments, the etching process is a plasma etching process that chemically etches the fin 500 and physically etches the isolation region 600. In some embodiments, the etching process etches the isolation region 600 and the substrate 10 located below the isolation region 600 to a surface 811 defining a crown-shaped depth profile. In some embodiments, the etching process etches the isolation layer 600 in the first region 511 and the second region 512 to a first depth and etches the isolation layer 600 in the central region 513 to a second depth, wherein the first depth is deeper than the second depth.

[0123] like Fig.15As shown in FIG. 7 , during a plasma etching process, plasma ions are directed toward the bottom trench surface 410 in a vertical direction of arrow 700. Plasma ions are positively charged. At the beginning of the etching process, negative charges accumulate on the trench sidewalls 401 and 402. Therefore, the plasma ions are attracted out of the vertical direction and toward the trench sidewalls 401 and 402. The plasma ions directed toward the center region 513 may be pulled toward the first region 511 or the second region 512. The plasma ions directed toward the first region 511 may be directed into the sidewall 401. The plasma ions directed toward the second region 512 may be directed into the sidewall 402. The plasma ions that strike the trench sidewalls 401 and 402 may be reflected toward the bottom trench surface 410 while retaining most of their energy. Therefore, the ion bombardment adjacent to the trench sidewalls 401 and 402 is greater than the ion bombardment at locations farther away from the trench sidewalls 401 and 402. In other words, the ion bombardment in the first region 511 and the second region 512 is greater than the ion bombardment in the central region 513.

[0124] Plasma bombardment is particularly relevant to physical etching of materials. In some embodiments, the etchant and conditions of the plasma etching process are selected such that the etching of the isolation region 600 is dominated by physical etching, while the etching of the fin 500 is dominated by chemical etching.

[0125] Therefore, the fin 500 and the substrate 10 located below the fin 500 are etched to substantially the same depth, that is, the charged sidewalls 401 and 402 and the non-vertical flow of positive ions do not significantly affect the chemical etching of the fin 500 in different regions (the first region 511, the second region 512, and the central region 513).

[0126] However, because physical etching dominates the etching of the isolation region 600, the isolation region 600 and the substrate 10 below the isolation region 600 are etched more near the trench sidewalls 401 and 402, i.e., etched to a deeper depth, and are etched less away from the trench sidewalls 401 and 402 due to ion attraction toward the sidewalls 401 and 402, i.e., etched to a shallower depth. In other words, the isolation region 600 and the substrate 10 below the isolation region 600 are etched more deeply in the first region 511 and the second region 512, and are etched more shallowly in the central region 513, i.e., etched to a shallower depth. In addition, the variation in etching depth can form a smooth gradient and define a crown profile 815.

[0127] In some embodiments, the chemical etching of the fin 500 achieves a deeper depth than the physical etching of the isolation region 600, that is, the minimum depth of etching under the fin 500 is greater than the maximum depth of etching under the isolation region 600. Therefore, the etched surface is formed with a protrusion 810, the protrusion 810 is formed under the isolation region 600 or includes the isolation region 600, and the protrusion 810 is separated by the groove 820 formed under the fin 500. In addition, due to the differential physical etching, the protrusion 810 is formed with an uppermost surface 811 defining a crown-shaped depth profile 815. The groove 820 is formed with a lowermost surface 821.

[0128] In some embodiments, performing a plasma etching process to etch the fins 500 and the isolation regions 600 may include completely removing the fins 500 and the isolation regions 600 and etching into the semiconductor substrate 10 below each fin 500 and each isolation region 600. In other embodiments, portions of the isolation regions 600 or portions of some of the isolation regions 600 may remain after the etching process is completed, such as Fig.15 as shown in .

[0129] In some embodiments, the fin 500 is a silicon fin, the isolation region is a silicon oxide isolation region, and the plasma etching process is performed using hydrogen bromide (HBr) as an etchant, such as in a HBrO 2 etching process.

[0130] Cross Reference Fig.19 and Fig.16 The method 1000 may continue to fill the trench 400 with a dielectric in step S16 to form the isolation structure 850. The method 1000 may continue to further process in step S17 to complete the manufacturing.

[0131] Reference Fig.17 , provides a transmission electron microscope (TEM) image of a portion of the semiconductor device 100. Fig.16 In the embodiment of the present invention, the etching process forms nineteen protrusions 810 labeled as protrusions 1, 2, 3, 4, 5, 6, 7, 8, 9, 10', 9', 8', 7', 6', 5', 4', 3', 2' and 1' in the groove 400 and twenty grooves 820 labeled as grooves 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10', 9', 8', 7', 6', 5', 4', 3', 2' and 1'.

[0132] As shown, the trench 400 is located between two metal gates 220. A plane 900 is defined by the top surfaces of the metal gates 220.

[0133] The uppermost surface 811 of each protrusion 810 is located at a vertical depth or distance DP below plane 900. The lowermost surface 821 of each recess is located at a vertical depth or distance DR below plane 900.

[0134] Table 1 provides the average, maximum and minimum values ​​of the depth DP of each protrusion.

[0135]

[0136]

[0137] As shown, the depth DP of the protrusions 810 varies greatly. For example, the total maximum depth DP (185 nm) is more than twice the total minimum depth DP (86 nm). In addition, the end protrusions 1 and 1' are even more significantly etched than the immediately adjacent protrusions 2 and 2'. In addition, the depth DP is much smaller in the central region 513 than in the first region 511 and the second region 512.

[0138] Table 2 provides the average, maximum and minimum values ​​of the depth DR of each groove.

[0139]

[0140] As shown in Table 2, the depths DR of the grooves are substantially the same. For example, the total minimum depth DR (172 nm) is within 10% of the total maximum depth (191 nm). In addition, there is no systematic difference in the depth DR between the first region 511, the second region 512, and the central region 513.

[0141] Fig.18 FIG. 4 is a transmission electron microscope (TEM) image of a portion of the semiconductor device 100 cut along the X-axis. As shown, in the X-direction, a trench 400 is formed between adjacent metal gates 220 .

[0142] exist Fig.18 , a plane 900 is defined at the top of the metal gate 220. In addition, a gate height a is defined from the plane 900 to a plane 910 defined by the uppermost surface of the gate. Furthermore, a depth b is defined from the plane 900 to the bottom of the trench 400. Each trench 400 is formed in an arcuate shape having a maximum width f at a depth c from the plane 900.

[0143] In addition, a horizontal width or critical dimension (CD) d between adjacent surfaces of the hard mask 240 is defined at the plane 910. Furthermore, a horizontal width or critical dimension (CD) e between adjacent fins 205 is defined at the plane 900.

[0144] exist Fig.18 In FIG. 9 , plane 920 is defined by the uppermost surface of hard mask 240. In addition, a vertical distance or height g of hard mask 240 from plane 910 to plane 920 is defined.

[0145] Table 3 presents the average size, maximum size, and minimum size of measurements a to g, according to some embodiments.

[0146]

[0147] Cross Reference Figures 11 to 13 and Fig.18 , the trench 400 is formed with a first end wall 491 away from the second end wall 492 in the X direction. As shown, the first end wall 491 is located between the gate structure and the second end wall 492, and the second end wall 492 is located between the second gate structure and the first end wall 491. After the plasma etching process, the maximum critical dimension in the X direction from the first end wall to the second end wall at the height of the first gate structure and the second gate structure (i.e., the fin critical dimension e) is 25 nanometers (nanometer, nm), such as 24.5nm, 24nm or 23.7nm. After the plasma etching process, the maximum critical dimension in the X direction from the first end wall 491 to the second end wall 492 at the bending depth c (i.e., the bending critical dimension f) is 30 nanometers (nanometer, nm), such as 29.5nm, 29nm, 28.5nm or 28.3nm.

[0148] As described above, the methods of some embodiments of the present disclosure provide, such as during a CPODE process, the formation of multiple trenches having a deeper depth closest to the trench sidewalls. Thus, the isolation structure formed within the trench provides improved protection against current leakage at the line edge. Additionally, the methods described in some embodiments of the present disclosure can be used for high aspect ratio etching and provide a unique depth profile. The method provides selective etching to remove small etch amounts, thereby providing a low risk of damage to the epitaxial source / drain region.

[0149] A method for manufacturing a semiconductor device is provided, and the method includes the following steps. A semiconductor structure is provided, the semiconductor structure having a first sidewall and a second sidewall away from the first sidewall, a plurality of fins located between the first sidewall and the second sidewall, and a plurality of isolation regions located between the first sidewall and the second sidewall, wherein adjacent fins are separated by respective isolation regions. A plasma etching process is performed to etch the fins and the isolation regions, wherein the plasma etching process chemically etches the fins, and wherein the plasma etching process physically etches the isolation regions to a plurality of surfaces defining a crown-shaped depth profile.

[0150] In some embodiments of the method, performing the plasma etching process includes chemically etching the fins to substantially the same depth.

[0151] In some embodiments of the method, the fins and the isolation regions are located above the semiconductor material, and wherein performing the plasma etching process to etch the fins and the isolation regions includes etching into the semiconductor material below each of the fins and below each of the isolation regions.

[0152] In some embodiments of the method, the fins and the isolation regions are located above the semiconductor material, wherein performing a plasma etching process to etch the fins and the isolation regions includes etching into the semiconductor material below each of the fins and below each of the isolation regions, and wherein a minimum depth of etching below the fins is greater than a maximum depth of etching below the isolation regions.

[0153] In some embodiments of the method, the fin is a silicon fin, wherein the isolation region is a silicon oxide isolation region, and wherein the plasma etching process is performed using hydrogen bromide (HBr) as an etchant.

[0154] In some embodiments of the method, at least three of the fins are located between the first sidewall and the second sidewall.

[0155] In some embodiments of the method, the first sidewall is away from the second sidewall in the Y direction; providing the semiconductor structure includes providing a semiconductor structure having a first end wall away from the second end wall in the X direction perpendicular to the Y direction, wherein the first end wall is located between the first gate structure and the second end wall, and wherein the second end wall is located between the second gate structure and the first end wall; after performing a plasma etching process, a maximum critical dimension in the X direction from the first end wall to the second end wall at the height of the first gate structure and the second gate structure is 25 nanometers.

[0156] In some embodiments of the method, the first sidewall is away from the second sidewall in the Y direction; providing the semiconductor structure includes providing a semiconductor structure having a first end wall away from the second end wall in an X direction perpendicular to the Y direction, wherein the first end wall is located between the first gate structure and the second end wall, and wherein the second end wall is located between the second gate structure and the first end wall; after performing a plasma etching process, a maximum critical dimension in the X direction from the first end wall to the second end wall at a height below the first gate structure and the second gate structure is 30 nanometers.

[0157] In another embodiment, a method of manufacturing a semiconductor device is provided, and the method includes the following steps: forming a field of fins extending upward from a first region, a second region, and an isolation layer in a central region between the first region and the second region; performing an etching process to etch the isolation layer, wherein the etching process etches the isolation layer in the first region and the second region to a first depth and etches the isolation layer in the central region to a second depth, wherein the first depth is deeper than the second depth.

[0158] In some embodiments of the method, performing the etching process includes etching the fin to a third depth, wherein the third depth is deeper than the first depth.

[0159] In some embodiments of the method, performing the etching process includes chemically etching the fin and physically etching the isolation layer.

[0160] In some embodiments of the method, the first region is formed with an end isolation layer segment and an intermediate isolation layer segment located between the end isolation layer segment and the central region; the second region is formed with an end isolation layer segment and an intermediate isolation layer segment located between the end isolation layer segment and the central region; and the etching process includes etching the end isolation layer segment to a maximum first depth and etching the intermediate isolation layer segment to a shallower first depth.

[0161] In some embodiments of the method, the fin and the isolation layer are formed to cover the semiconductor substrate, and wherein performing the etching process includes removing the isolation layer, removing the fin, and recessing the semiconductor substrate to form a trench.

[0162] In some embodiments, the method further includes depositing a dielectric material in the trench to define an edge of the semiconductor device.

[0163] In some embodiments of the method, the field of the fin extending upward from the isolation layer is formed adjacent to the metal gate structure having the uppermost surface; the first depth is greater than 130 nanometers; and the second depth is less than 130 nanometers.

[0164] In some embodiments of the method, performing the etching process includes etching the fin to a third depth; and the third depth is greater than 160 nanometers.

[0165] In another embodiment, a semiconductor device is provided, and the semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed above a semiconductor substrate. The trench is formed in the semiconductor substrate and is adjacent to the gate structure. The semiconductor substrate is formed with a trench bottom surface below the trench. The trench bottom surface includes a plurality of spaced-apart protrusions, the protrusions being separated by a plurality of grooves, each of the protrusions having an uppermost surface. The uppermost surface of the protrusion closer to the gate structure is located at a deeper depth than the uppermost surface of the protrusion at the center of the trench. The dielectric material is located in the trench.

[0166] In some embodiments of the device, each of the recesses has a vertical depth greater than 170 nanometers measured from a top surface of the gate structure; and each of the uppermost surfaces has a vertical depth less than 170 nanometers measured from a top surface of the gate structure.

[0167] In some embodiments of the device, each of the grooves has a lowest surface, and wherein the lowest surfaces are located at depths within ten percent of each other.

[0168] In some embodiments of the device, the uppermost surface of the protrusion defines a crown-shaped profile.

[0169] In another embodiment, a semiconductor device is provided, and the semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed above a semiconductor substrate. The trench is formed in the semiconductor substrate and adjacent to the gate structure. The semiconductor substrate has a trench bottom surface formed below the trench. The trench bottom surface includes a plurality of spaced-apart protrusions separated by a plurality of grooves, each of the protrusions having an uppermost surface. The uppermost surface of the protrusion closer to the gate structure is located at a deeper depth than the uppermost surface of the protrusion at the center of the trench. The trench is arched and the uppermost surface of the protrusion defines a crown profile. The dielectric material is located in the trench. In some embodiments of the device, each of the grooves has a vertical depth greater than 170 nanometers measured from the top surface of the gate structure, and each of the uppermost surfaces has a vertical depth less than 170 nanometers measured from the top surface of the gate structure. In some embodiments of the device, each of the grooves has a vertical depth measured from the top surface of the gate structure in the range of 172 nanometers to 191 nanometers. In some embodiments of the device, each of the uppermost surfaces has a vertical depth in a range of 86 nanometers to 185 nanometers measured from the top surface of the gate structure. In some embodiments of the device, each of the recesses has a lowermost surface, and the lowermost surfaces are located at multiple depths within ten percent of each other.

[0170] In another embodiment, a semiconductor device is provided, and the semiconductor device includes a gate structure, a trench, and a dielectric material. The gate structure is formed above a semiconductor substrate. The trench is formed in the semiconductor substrate and is adjacent to the gate structure. The semiconductor substrate is formed with a trench bottom surface below the trench. The trench bottom surface includes a plurality of spaced-apart protrusions, the protrusions being separated by a plurality of grooves, each of the protrusions having an uppermost surface. The uppermost surface of the protrusion closer to the gate structure is located at a deeper depth than the uppermost surface of the protrusion at the center of the trench. The vertical depth of the uppermost surface of one of the protrusions closer to the gate structure measured from the top surface of the gate structure is more than twice the vertical depth of the uppermost surface of one of the protrusions at the center of the trench measured from the top surface of the gate structure. The dielectric material is located in the trench.

[0171] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they can easily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and various changes, substitutions and modifications can be made in some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A gate structure is formed on a semiconductor substrate; a trench formed in the semiconductor substrate and adjacent to the gate structure, wherein: The semiconductor substrate forms a trench bottom surface below the trench; The groove bottom surface includes a plurality of spaced-apart protrusions separated by a plurality of grooves, each of the plurality of protrusions having an uppermost surface; and The plurality of protrusions are located closer to the plurality of uppermost surfaces of the gate structure at a depth deeper than the plurality of uppermost surfaces of the plurality of protrusions at a center of the trench; and A dielectric material is located in the trench.

2. The semiconductor device according to claim 1, wherein in: Each of the plurality of recesses has a vertical depth measured from a top surface of the gate structure greater than 170 nanometers; and Each of the plurality of uppermost surfaces has a vertical depth measured from the top surface of the gate structure that is less than 170 nanometers.

3. The semiconductor device according to claim 1, wherein: Wherein each of the plurality of grooves has a lowest surface, and wherein the plurality of lowest surfaces are located at depths that are within ten percent of each other.

4. The semiconductor device according to claim 1, wherein: Wherein the plurality of uppermost surfaces of the plurality of protrusions define a crown-shaped profile.

5. A semiconductor device, characterized in that: Include: A gate structure is formed on a semiconductor substrate; a trench formed in the semiconductor substrate and adjacent to the gate structure, wherein: The semiconductor substrate forms a trench bottom surface below the trench; The groove bottom surface includes a plurality of spaced-apart protrusions separated by a plurality of grooves, each of the plurality of protrusions having an uppermost surface; The plurality of protrusions are located closer to the plurality of uppermost surfaces of the gate structure at a depth deeper than the plurality of uppermost surfaces of the plurality of protrusions at a center of the trench; and The groove is arcuate and the uppermost surfaces of the projections define a crown-shaped profile; and A dielectric material is located in the trench.

6. The semiconductor device according to claim 5, wherein: in: Each of the plurality of recesses has a vertical depth measured from a top surface of the gate structure greater than 170 nanometers; and Each of the plurality of uppermost surfaces has a vertical depth measured from the top surface of the gate structure that is less than 170 nanometers.

7. The semiconductor device according to claim 6, wherein: The vertical depth of each of the plurality of recesses measured from the top surface of the gate structure is in a range of 172 nanometers to 191 nanometers.

8. The semiconductor device according to claim 5, wherein: Each of the plurality of uppermost surfaces has a vertical depth measured from a top surface of the gate structure in a range of 86 nanometers to 185 nanometers.

9. The semiconductor device according to claim 5, wherein: Wherein each of the plurality of grooves has a lowest surface, and wherein the plurality of lowest surfaces are located at depths within ten percent of each other.

10. A semiconductor device, characterized in that: Include: A gate structure is formed on a semiconductor substrate; a trench formed in the semiconductor substrate and adjacent to the gate structure, wherein: The semiconductor substrate forms a trench bottom surface below the trench; The groove bottom surface includes a plurality of spaced-apart protrusions separated by a plurality of grooves, each of the plurality of protrusions having an uppermost surface; The plurality of protrusions are located closer to the plurality of uppermost surfaces of the gate structure at a depth deeper than the plurality of uppermost surfaces of the plurality of protrusions at a center of the trench; and A vertical depth of the uppermost surface of one of the plurality of protrusions closer to the gate structure measured from a top surface of the gate structure is more than twice a vertical depth of the uppermost surface of one of the plurality of protrusions at the center of the trench measured from the top surface of the gate structure; and A dielectric material is located in the trench.

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