Semiconductor device

Abstract

Various embodiments of the utility model relate to a semiconductor device, which can comprise an electrostatic discharge (ESD) protection circuit and a high-voltage ESD trigger circuit, and the high-voltage ESD trigger circuit is configured to trigger ESD protection for a high-voltage circuit of the semiconductor device. The high voltage ESD trigger circuit may be implemented by one or more of the exemplary embodiments of the high voltage ESD trigger circuit described herein. Exemplary embodiments of the high voltage ESD trigger circuits described herein are capable of handling high voltages of high voltage circuits included in a semiconductor device. This reduces the likelihood of premature triggering of ESD protection during normal operation of the high voltage circuits and / or prevents premature triggering of ESD protection, and enables high voltage circuits to be protected from high voltage ESD events.

Description

Technical Field

[0001] The embodiment of the utility model relates to a semiconductor device. Background Art

[0002] Electrostatic discharge (ESD) is a concern for semiconductor integrated circuits (ICs). If not handled properly, an ESD event may generate high voltages that damage device circuits of a semiconductor device. To prevent ESD-related damage, a semiconductor device may include an ESD protection circuit. The ESD protection circuit is operable to divert current away from the device circuit of the semiconductor device during an ESD event, thereby protecting the device circuit from damage by the ESD event. Utility Model Content

[0003] One aspect of the utility model provides a semiconductor device. The semiconductor device includes: a device circuit, an electrostatic discharge (ESD) circuit, and an ESD trigger circuit. The ESD circuit is coupled to the device circuit. The ESD trigger circuit is coupled to the ESD circuit and the device circuit, and includes: a substrate, a PNP ESD trigger device, and a plurality of n-type doped barrier regions. The PNP ESD trigger device is in the substrate, and includes: an n-type doped base, a p-type doped collector, and a p-type doped emitter, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector, and wherein a second portion of the substrate is located between the p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter. A plurality of n-type doped barrier regions are in the substrate, and include: a first n-type doped barrier region located under the first n-type doped well of the n-type doped base and a second n-type doped barrier region located under the second n-type doped well of the p-type doped emitter, wherein a third portion of the substrate is located between the first n-type doped barrier region and the second n-type doped barrier region.

[0004] Another aspect of the utility model provides a method for forming a semiconductor device. The method includes: forming a plurality of shallow trench isolation (STI) regions in a substrate of the semiconductor device. The method also includes: forming: an n-type doped base, a p-type doped collector, and a p-type doped emitter for a PNP electrostatic discharge (ESD) trigger device of the semiconductor device. The n-type doped base is located in the substrate and between a first STI region and a second STI region among a plurality of STI regions. The p-type doped collector is located in the substrate and between a second STI region and a third STI region among a plurality of STI regions, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector. The p-type doped emitter is located in the substrate and between a third STI region and a fourth STI region among a plurality of STI regions, wherein a second portion of the substrate is located between a p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter. The method also includes: forming a first field plate structure on the second STI region. The method also includes: forming a second field plate structure on the third STI region.

[0005] Another aspect of the present invention provides a semiconductor device. The semiconductor device includes: a device circuit, an electrostatic discharge (ESD) circuit, and an ESD trigger circuit. The ESD circuit is coupled to the device circuit. The ESD trigger circuit is coupled to the ESD circuit and the device circuit, and includes: a substrate; and a PNP ESD trigger device. The PNP ESD trigger device is in the substrate, and includes: an n-type doped base, a p-type doped collector, and a p-type doped emitter. The n-type doped base includes a plurality of first fin-shaped structures. The p-type doped collector includes a plurality of second fin-shaped structures, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector. The p-type doped emitter includes a plurality of third fin-shaped structures, wherein a second portion of the substrate is located between a p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented.

[0008] FIG. 2A to FIG. 2C is a diagram of an exemplary semiconductor device described herein.

[0009] FIG. 3A to FIG. 3C is a diagram of an exemplary implementation of an electrostatic discharge (ESD) triggering circuit described herein.

[0010] FIG. 4A to FIG. 4Jis a diagram of an exemplary embodiment of an ESD trigger circuit formed in a semiconductor device described herein.

[0011] FIG. 5A to FIG. 5C is a diagram of an exemplary implementation of an ESD trigger circuit described herein.

[0012] FIG. 6A to FIG. 6C is a diagram of an exemplary implementation of an ESD trigger circuit described herein.

[0013] FIG. 7A to FIG. 7C is a diagram of an exemplary embodiment of an ESD trigger circuit formed in a semiconductor device described herein.

[0014] FIG. 8A to FIG. 8C is a diagram of an exemplary implementation of an ESD trigger circuit described herein.

[0015] 9A to 9C is a diagram of an exemplary implementation of an ESD trigger circuit described herein.

[0016] FIG. 10A to FIG. 10F is a diagram of an exemplary implementation of an ESD trigger circuit described herein.

[0017] FIG. 11A to FIG. 11K is a diagram of an exemplary implementation of an ESD trigger circuit described herein.

[0018] Fig.12 is a diagram of exemplary components of an apparatus described herein.

[0019] Fig.13 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein.

[0020] Fig.14 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein.

[0021] Fig.15 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein. DETAILED DESCRIPTION

[0022] The present invention provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed by itself.

[0023] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] Some semiconductor devices include high voltage circuits configured to operate at high voltages (e.g., greater than 40 volts). Conventional electrostatic discharge (ESD) protection circuits may be triggered by ESD trigger circuits, which are unable to handle the high voltages of these high voltage circuits and may prematurely trigger the ESD protection during normal operation of these high voltage circuits, thereby rendering the high voltage circuits inoperable.

[0025] In some embodiments described herein, a semiconductor device may include an ESD protection circuit and a high-voltage ESD trigger circuit, wherein the high-voltage ESD trigger circuit is configured to trigger ESD protection for a high-voltage circuit of the semiconductor device. The high-voltage ESD trigger circuit may be implemented by one or more of the exemplary embodiments of the high-voltage ESD trigger circuit described herein. The exemplary embodiments of the high-voltage ESD trigger circuit described herein are capable of handling the high voltage of the high-voltage circuit included in the semiconductor device. This reduces the possibility of prematurely triggering ESD protection during normal operation of these high-voltage circuits and / or prevents prematurely triggering ESD protection during normal operation of these high-voltage circuits, and enables the high-voltage circuit to be protected from the effects of high-voltage ESD events.

[0026] Figure 11 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, environment 100 may include a plurality of semiconductor processing tools 102-114 and a wafer / die transport tool 116. Multiple semiconductor processing tools 102-114 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor processing tool. Among other examples, the tools included in exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility.

[0027] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0028] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme UV (EUV) source, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from the mask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0029] The developing tool 106 is a semiconductor processing tool capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portion of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed portion or the unexposed portion of the photoresist layer using a chemical developer.

[0030] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0031] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free-abrasive polishing) to polish or planarize the surface of the semiconductor device. The planarization tool 110 may utilize abrasives and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate at different rotational axes to remove material and smooth any irregular topography of the semiconductor device, so that the semiconductor device becomes flat or planar.

[0032] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0033] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate so that the ions are implanted below the surface of the substrate.

[0034] Among other examples, the wafer / die transporter 116 may be included in a cluster tool, or in another type of tool that includes multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between multiple processing chambers, between a processing chamber and a buffer, between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)). In some embodiments, the wafer / die transporter 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning chamber (e.g., for cleaning or removing oxides, oxidation and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition chambers (e.g., chambers for depositing different types of materials, chambers for performing different types of deposition operations).

[0035] In some implementations, one or more of the semiconductor processing tools 102 - 114 and / or the wafer / die transport tool 116 may perform one or more semiconductor processing operations described herein. For example, among other examples, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may form multiple shallow trench isolation (STI) regions in a substrate of a semiconductor device; for a PNP ESD trigger device of the semiconductor device, an n-type doped base may be formed in the substrate and between a first STI region and a second STI region of the multiple STI regions, a p-type doped collector may be formed in the substrate and between a second STI region and a third STI region of the multiple STI regions, a first portion of the substrate may be located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector, a p-type doped emitter may be formed in the substrate and between a third STI region and a fourth STI region of the multiple STI regions, and a second portion of the substrate may be located between the p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter; a first field plate structure may be formed on the second STI region; and / or a second field plate structure may be formed on the third STI region.

[0036] As another example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may form an n-type doped base of a PNP ESD trigger device in a substrate of the semiconductor device; a p-type doped collector of the PNP ESD trigger device, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector; and a p-type doped emitter of the PNP ESD trigger device, wherein a second portion of the substrate is located between the p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter; and a plurality of n-type doped barrier regions in the substrate, including a first n-type doped barrier region below the first n-type doped well of the n-type doped base and a second n-type doped barrier region below the second n-type doped well of the p-type doped collector, wherein a third portion of the substrate is located between the first n-type doped barrier region and the second n-type doped barrier region.

[0037] As another example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 can form an n-type doped base of a PNP ESD trigger device in a substrate of the semiconductor device, the n-type doped base including a plurality of first fin-shaped structures; a p-type doped emitter of the PNP ESD trigger device, the p-type doped emitter including a plurality of second fin-shaped structures, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped emitter; and a p-type doped collector of the PNP ESD trigger device, the p-type doped collector including a plurality of third fin-shaped structures, wherein a second portion of the substrate is located between a p-type doped well of the p-type doped emitter and a second n-type doped well of the p-type doped collector.

[0038] One or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may perform other semiconductor processing operations described herein, such as FIG. 4A to FIG. 4J , FIG. 7A to FIG. 7C and / or Fig.13 Related examples and other examples.

[0039] Figure 1 The number and arrangement of devices shown are provided as one or more examples. Figure 1 There may be additional devices, fewer devices, different devices, or differently arranged devices than those shown. Figure 1 Two or more of the devices shown may be implemented in a single device, or Figure 1 The single device shown may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of the exemplary environment 100 may perform one or more functions described as being performed by another set of devices of the exemplary environment 100.

[0040] FIG. 2A to FIG. 2C 2 is a diagram of an exemplary semiconductor device described herein. The semiconductor device 200 may include a logic device (e.g., a processor, a central processing unit (CPU), a graphics processing unit (GPU)), a memory device (e.g., a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device), a display panel device (e.g., a display panel driver including a driver integrated circuit (IC), a line driver IC, a level shifter IC), and / or another type of semiconductor device 200 including a high voltage semiconductor device.

[0041] like Figure 2AAs shown, the exemplary semiconductor device 200 may include a device circuit 202, an ESD protection circuit 204, and an ESD trigger circuit 206, as well as other types of circuits. Among other examples, the device circuit 202, the ESD protection circuit 204, and / or the ESD trigger circuit 206 may be coupled to a drain input 208, a source input 210, and / or a control input 212.

[0042] The device circuit 202 may include one or more transistors 214. One or more transistors may be configured to perform logic operations, memory operations, power supply operations, analog-to-digital conversion operations, and / or other types of semiconductor device operations. In some embodiments, the transistor 214 may be configured as a complementary metal oxide semiconductor (CMOS) logic circuit or another type of circuit. In some embodiments, the device circuit 202 includes a high voltage device circuit, and the transistor 214 includes a high voltage transistor. The high voltage transistor may include a high voltage planar transistor, a high voltage fin field effect transistor (finFET), a high voltage nanostructure (e.g., a full surround gate (GAA) transistor, a nanowire transistor, a nanosheet transistor, a multi-bridge channel transistor, a nanobelt transistor) and / or another type of high voltage transistor configured to operate at a high voltage (e.g., greater than 40 volts).

[0043] The ESD protection circuit 204 may include one or more ESD protection devices 216 configured to provide ESD protection for the device circuit 202 against high voltage spikes, high voltage surges, and / or other types of high voltage events. For example, the ESD protection circuit 204 may include one or more diodes and / or one or more other types of ESD protection devices configured to provide ESD protection for the device circuit 202 against high voltage spikes, high voltage surges, and / or other types of high voltage events. Figure 2A As shown, in the exemplary semiconductor device 200 , the ESD protection devices 216 may be connected in series with each other, and the ESD protection devices 216 may be connected to the drain input 208 , the source input 210 , and the control input 212 .

[0044] The ESD trigger circuit 206 may include one or more PNP ESD trigger devices 218. The PNP ESD trigger device 218 may be configured to redirect current from the device circuit 202 to the ESD protection circuit 204 based on or in response to a high voltage event, so that the ESD protection circuit 204 can release current, thereby protecting the device circuit 202. The PNP ESD trigger device 218 may include a bipolar junction transistor (BJT) configured to trigger activation of the ESD protection circuit 204 based on a voltage of the device circuit 202 satisfying a threshold voltage. The threshold voltage may be greater relative to the operating voltage of the device circuit 202. For example, if the device circuit 202 operates at approximately 40 volts, the threshold voltage may be included in the range of approximately 50 volts to approximately 65 volts. However, other ranges of values ​​are also within the scope of the present disclosure. The PNP ESD trigger device 218 may include an n-type doped base 220, a p-type doped emitter 222, and a p-type doped collector 224, thereby forming a PNP structure of the PNP ESD trigger device 218.

[0045] Figure 2B Another exemplary semiconductor device 226 is shown. Figure 2B As shown, semiconductor device 226 may include a circuit configuration similar to semiconductor device 200. For example, semiconductor device 226 may include device circuit 202, ESD protection circuit 204, and ESD trigger circuit 206. Device circuit 202 may include one or more transistors 214, ESD protection circuit 204 may include multiple ESD protection devices 216, and ESD trigger circuit 206 may include one or more PNP ESD trigger devices 218. Figure 2B As further shown, the ESD protection circuit 204 may include multiple pairs of ESD protection devices 216 connected in parallel in the ESD protection circuit 204. The ESD protection devices 216 may be connected in series with each other, and the ESD protection devices 216 may be connected to the drain input 208, the source input 210, and the control input 212.

[0046] Figure 2C Another exemplary semiconductor device 228 is shown. Figure 2C As shown, semiconductor device 228 may include a circuit configuration similar to semiconductor device 200 and semiconductor device 226. For example, semiconductor device 228 may include device circuit 202, ESD protection circuit 204, and ESD trigger circuit 206. Device circuit 202 may include one or more transistors 214, ESD protection circuit 204 may include multiple ESD protection devices 216, and ESD trigger circuit 206 may include one or more PNP ESD trigger devices 218.

[0047] like Figure 2CAs further shown, the ESD protection circuit 204 may include multiple pairs of ESD protection devices 216 connected in parallel in the ESD protection circuit 204. The ESD protection devices 216 may be connected in series with each other, and the ESD protection devices 216 may be connected to the drain input 208, the source input 210, and the control input 212. Figure 2C As further shown, the ESD protection circuit 204 may include a resistor 230 that cross-couples the pair of ESD protection devices 216 .

[0048] As noted above, providing FIG. 2A to FIG. 2C As an example. Other examples can be found in FIG. 2A to FIG. 2C Different than described.

[0049] FIG. 3A to FIG. 3C is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. FIG. 3A to FIG. 3C The described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0050] Figure 3A and Figure 3B FIG. 3 is an exemplary embodiment 300 of the ESD trigger circuit 206. Figure 3A As shown, the ESD trigger circuit 206 can be formed and / or included in a substrate 302 of a semiconductor device. The substrate 302 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The substrate 302 may include various layers, including a conductive layer or an insulating layer formed on a semiconductor substrate. The substrate 302 may include a compound semiconductor and / or an alloy semiconductor. The substrate 302 may include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., n-well, p-well) may be formed in regions designed for different device types (e.g., p-type metal-oxide semiconductor (PMOS) nanostructure transistors, n-type metal-oxide semiconductor (NMOS) nanostructure transistors) on the substrate 302. Suitable doping may include ion implantation and / or diffusion processes of dopants. Additionally, substrate 302 may include an epitaxial layer (epi layer), may be strained for performance enhancement, and / or may have other suitable enhancement features.Substrate 302 may include a portion of a semiconductor wafer on which other semiconductor devices are formed.

[0051] The ESD trigger circuit 206 may include a plurality of doped regions included in the substrate 302. For example, the ESD trigger circuit 206 may include a plurality of p-type doped wells 304 included in the substrate 302. The p-type doped wells 304 may be regions of the substrate 302 doped with one or more p-type dopants, such as boron (B), gallium (Ga), and / or indium (In). As another example, the ESD trigger circuit 206 may include a plurality of n-type doped wells 306 included in the substrate 302. The n-type doped wells 306 may be regions of the substrate 302 doped with one or more n-type dopants, such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb). In some embodiments, one or more of the p-type doped wells 304 are omitted from the ESD trigger circuit 206 to reduce manufacturing costs and / or manufacturing complexity for forming the ESD trigger circuit 206. However, including the p-type doped wells 304 may reduce the on-resistance (R on In some embodiments, one or more n-type doped wells 306 are omitted from the ESD trigger circuit 206 to reduce manufacturing costs and / or manufacturing complexity for forming the ESD trigger circuit 206. However, including the n-type doped well 306 can reduce the on-resistance (R on ).

[0052] As another example, the ESD trigger circuit 206 may include a plurality of p+ regions 308 included in the substrate 302. The p+ region 308 may be a region of the substrate 302 doped with one or more p-type dopants, such as boron (B), gallium (Ga), and / or indium (In). As another example, the ESD trigger circuit 206 may include a plurality of n+ regions 310 included in the substrate 302. The n+ region 310 may be a region of the substrate 302 doped with one or more n-type dopants, such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb).

[0053] As another example, the ESD trigger circuit 206 may include a plurality of p+ regions 312 included in the substrate 302. The p+ region 312 may be a region of the substrate 302 doped with one or more p-type dopants, such as boron (B), gallium (Ga), and / or indium (In). As another example, the ESD trigger circuit 206 may include a plurality of n+ regions 314 included in the substrate 302. The n+ region 314 may be a region of the substrate 302 doped with one or more n-type dopants, such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb).

[0054] The p-type doped well 304, the p+ region 308, and the p+ region 312 may have different dopant concentrations. For example, the dopant concentration in the p+ region 312 may be greater than the dopant concentration in the p+ region 308, and the dopant concentration in the p+ region 308 may be greater than the dopant concentration in the p-type doped well 304.

[0055] The n-type doped well 306, the n+ region 310, and the n+ region 314 may have different dopant concentrations. For example, the dopant concentration in the n+ region 314 may be greater than the dopant concentration in the n+ region 310, and the dopant concentration in the n+ region 310 may be greater than the dopant concentration in the n-type doped well 306.

[0056] like Figure 3A As further shown, the ESD trigger circuit 206 may include one or more PNP ESD trigger devices 218. The PNP ESD trigger device 218 may include an n-type doped base 220, a p-type doped emitter 222, and a p-type doped collector 224. In some embodiments, the ESD trigger circuit 206 may include 2 to 50 "fingers" of the PNP ESD trigger device 218. For example, 2 fingers refer to 2 n-type doped bases 220, 2 p-type doped collectors 224, and 1 p-type doped emitter 222. As another example, 4 fingers refer to 2 n-type doped bases 220, 3 p-type doped collectors 224, and 2 p-type doped emitters 222.

[0057] The n-type doped base 220 may include an n-type doped well 306, an n+ region 310 in the n-type doped well 306, and an n+ region 314 in the n+ region 310. The p-type doped emitter 222 may include the n-type doped well 306, an n+ region 310 in the n-type doped well 306, and a p+ region 312 in the n+ region 310. The p-type doped collector 224 may include the p-type doped well 304, a p+ region 308 in the p-type doped well 304, and a p+ region 312 in the p+ region 308.

[0058] like Figure 3A As further shown, the ESD trigger circuit 206 may include a plurality of STI regions 316 in the substrate 302. For example, the STI region 316 may be included between the n-type doped base 220 and the p-type doped collector 224 of the PNP ESD trigger device 218. The STI region 316 may be included on opposite sides of the n-type doped base 220. The STI region 316 may include a dielectric material, such as silicon oxide (SiO2). i O x ), silicon nitride (Si x N y), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low dielectric constant (low-k) dielectric material, and / or another suitable insulating material. The STI region 316 may include a multi-layer structure, for example, having one or more liner layers.

[0059] like Figure 3A As further shown, the ESD trigger circuit 206 may include one or more resist protection oxide (RPO) structures 318 on and / or above the substrate 302. For example, the RPO structure 318 may be included on and / or above the substrate 302 between the p-type doped collector 224 and the p-type doped emitter 222 of the PNP ESD trigger device 218. The RPO structure 318 may include an oxide material, such as silicon oxide (SiO x , such as SiO 2 ) and / or another dielectric oxide material. The RPO structure 318 may be included to control the flow of charge carriers in the PNP ESD trigger device 218. In some embodiments, the RPO structure 318 may partially overlap the p-type doped well 304 of the p-type doped collector 224, the p+ region 308 of the p-type doped collector 224, the n-type doped well 306 of the p-type doped emitter 222, and / or the n+ region 310 of the p-type doped emitter 222.

[0060] like Figure 3A As further shown, the ESD trigger circuit 206 may include one or more n-type doped barrier regions 320 in the substrate 302. The n-type doped barrier region 320 may be included below the n-type doped base 220 of the PNP ESD trigger device 218 and below the p-type doped emitter 222 of the PNP ESD trigger device 218. The n-type doped barrier region 320 may be included below the n-type doped base 220 of the PNP ESD trigger device 218 and below the p-type doped emitter 222 of the PNP ESD trigger device 218 to reduce or prevent charge carrier migration from the n-type doped well 306 into the substrate 302. Reduced or eliminated charge carrier migration into the substrate 302 may increase the operating efficiency of the ESD trigger circuit 206. The n-type doped barrier region 320 may be a region of the substrate 302 doped with one or more n-type dopants, such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb), etc.

[0061] The n-type doped barrier region 320 may be omitted (not included) below the p-type doped collector 224 of the PNP ESD trigger device 218. Omitting the n-type doped barrier region 320 below the p-type doped collector 224 of the PNP ESD trigger device 218 results in a gap or portion 322 of the substrate 302 being located between the n-type doped barrier regions 320. The PNP ESD trigger device 218 may trigger the operation of the ESD protection circuit 204 based on a voltage applied to the PNP ESD trigger device 218 that satisfies a breakdown voltage of the PNP ESD trigger device 218. If a breakdown occurs between the n-type doped barrier region 320 and the p-type doped well 304 of the p-type doped collector 224, the breakdown voltage of the PNP ESD trigger device 218 may be too low to accommodate the high operating voltage of the associated device circuit 202 in the semiconductor device, thereby causing the device circuit 202 to not function properly.

[0062] Omission of the n-type doped barrier region 320 below the p-type doped collector 224 of the PNP ESD trigger device 218 results in a lack of a PN interface below the p-type doped collector 224, which prevents the PNP ESD trigger device 218 from breaking down between the n-type doped barrier region 320 and the p-type doped well 304 of the p-type doped collector 224. Instead, the breakdown of the PNP ESD trigger device 218 occurs between the p+ region 308 of the p-type doped collector 224 and the n+ region 310 of the p-type doped emitter 222.

[0063] The portion 322 of the substrate 302 may be an undoped portion or p-type doped, or a portion of the substrate 302 having a very low n-type dopant concentration relative to the n-type doped barrier region 320. The portion 322 may be doped with n-type dopants as a byproduct of semiconductor processing of the ESD trigger circuit 206 because n-type dopants may migrate from the n-type doped barrier region 320 (and / or other n-type doped regions) into the portion 322 during thermal operations or other types of operations that result in dopant migration. Even if n-type dopants inadvertently migrate into the portion 322 of the substrate 302, omitting the n-type doped barrier region 320 below the p-type doped collector 224 of the PNP ESD trigger device 218 may result in a lower overall effective dopant concentration in the portion 322. For example, the n-type dopant concentration in the portion 322 of the substrate 302 may include about 1×10 13 n-type ions to about 1x10 per cubic centimeter 15 n-type ions, and the n-type dopant concentration in the n-type doping barrier region 320 may be within a range of about 1×10 17 n-type ions to about 1x10 per cubic centimeter 21 However, other value ranges are also within the scope of the present disclosure.

[0064] like Figure 3A As further shown, the ESD trigger circuit 206 may include a portion 324 of the substrate 302 between the n-type doped base 220 and the p-type doped collector 224 and between the p-type doped collector 224 and the p-type doped emitter 222. The portion 324 of the substrate 302 may be located below the RPO structure 318 of the ESD trigger circuit 206. The portion 324 provides a gap or spacing between the n-type doped well 306 of the n-type doped base 220 and the p-type doped well 304 of the p-type doped collector 224 and between the p-type doped well 304 of the p-type doped collector 224 and the n-type doped well 306 of the p-type doped emitter 222. The portion 324 increases the distance or spacing between the p+ region 308 of the p-type doped collector 224 and the n+ region 310 of the p-type doped emitter 222 (e.g., adjacent relative to the p-type doped well 304 and the n-type doped well 306), and the increased distance or spacing increases the breakdown of the PNP ESD trigger device 218. In addition, the size or width of the portion 324 can be adjusted during the manufacturing process of the ESD trigger circuit 206 to achieve a threshold breakdown voltage of the ESD trigger circuit 206.

[0065] Portion 324 of substrate 302 may be an undoped portion or p-type doped, or a portion of substrate 302 having a very low n-type dopant concentration relative to p-type doped well 304 and n-type doped well 306. Portion 324 may be doped with n-type dopants and / or p-type dopants as a byproduct of semiconductor processing of ESD trigger circuit 206 because n-type dopants may migrate from adjacent n-type doped well 306 (and / or other n-type doped regions) into portion 324 and / or p-type dopants may migrate from adjacent p-type doped well 304 (and / or other p-type doped regions) into portion 324 during thermal operations or other types of operations that cause dopant migration. The n-type dopant concentration in portion 324 of substrate 302 may include about 1×10 13 n-type ions to about 1x10 per cubic centimeter 15 n-type ions, and / or the p-type dopant concentration in the portion 324 of the substrate 302 may include about 1×10 13 p-type ions to about 1x10 per cubic centimeter 15 However, other value ranges are also within the scope of the present disclosure.

[0066] like Figure 3AAs further shown, the ESD trigger circuit 206 may also include a terminal 326. The terminal 326 may enable a voltage to be applied to the substrate 302 to electrically bias the substrate 302. The terminal 326 may include a p-type doped well 304, a p+ region 308 in the p-type doped well 304, and a p+ region 312 in the p+ region 308. The STI region 316 may be included on opposite sides of the terminal 326. In some embodiments, a portion 324 of the substrate 302 may be included between the terminal 326 and the n-type doped base 220 of the adjacent, PNP ESD trigger device 218. In some embodiments, the n-type doped barrier region 320 may be omitted from below the p-type doped well 304 of the terminal 326.

[0067] Figure 3B FIG. 2 shows several exemplary dimensions of an exemplary embodiment 300 of the ESD trigger circuit 206. In some embodiments, one or more other exemplary embodiments of the ESD protection circuit 206 described herein may include a combination of Figure 3B One or more of the dimensions shown and described.

[0068] like Figure 3B As shown, the exemplary dimension D1 may include a spacing or distance between the p-type doped well 304 of the p-type doped collector 224 and the n-type doped well 306 of the p-type doped emitter 222 of the PNP ESD trigger device 218 of the ESD trigger circuit 206. The exemplary dimension D1 may correspond to a width of the portion 324 of the substrate 302 between the p-type doped well 304 and the n-type doped well 306. In some embodiments, the exemplary dimension D1 may be included in a range of about 0.5 microns to about 5 microns. If the exemplary dimension D1 is less than about 0.5 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). If the exemplary dimension D1 is greater than about 5 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too high to trigger activation of the associated ESD protection circuit 204, thereby increasing the likelihood of damage to the device circuit 202. However, other ranges of values ​​are also within the scope of the present disclosure.

[0069] Another exemplary dimension D2 may include a spacing or distance between the p-type doped well 304 of the p-type doped collector 224 and the n-type doped well 306 of the n-type doped base 220 of the PNP ESD trigger device 218 of the ESD trigger circuit 206. The exemplary dimension D2 may correspond to a width of the portion 324 of the substrate 302 between the p-type doped well 304 and the n-type doped well 306. In some embodiments, the exemplary dimension D2 may be included in a range of about 0.5 microns to about 5 microns. If the exemplary dimension D2 is less than about 0.5 microns, the breakdown of the PNP ESD trigger device 218 occurs between the n-type doped base 220 and the p-type doped collector 224 instead of between the p-type doped collector 224 and the p-type doped emitter 222 of the PNP ESD trigger device 218, thereby causing improper operation of the PNP ESD trigger device 218. If the exemplary dimension D2 is greater than about 5 microns, the lateral size of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0070] Another exemplary dimension D3 may include a spacing or distance between the P-type doped well 304 of the terminal 326 of the PNP ESD trigger device 218 of the ESD trigger circuit 206 and the n-type doped well 306 of the n-type doped base 220. The exemplary dimension D3 may correspond to a width of a portion 324 of the substrate 302 between the P-type doped well 304 and the n-type doped well 306. In some embodiments, the exemplary dimension D3 may be included in a range of about 0.5 microns to about 5 microns. If the exemplary dimension D3 is less than about 0.5 microns, the breakdown of the PNP ESD trigger device 218 occurs between the terminal 326 and the n-type doped base 220, rather than between the P-type doped collector 224 and the P-type doped emitter 222 of the PNP ESD trigger device 218, thereby causing improper operation of the PNP ESD trigger device 218. If the exemplary dimension D3 is greater than about 5 microns, the lateral size of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0071] Another exemplary dimension D4 may include a spacing or distance between an outer edge of the n-type doped well 306 and an outer edge of the n+ region 310 included in the n-type doped well 306. The n-type doped well 306 and the n+ region 310 may be included in the n-type doped base 220 or the p-type doped emitter 222 of the PNP ESD trigger device 218 of the ESD trigger circuit 206. In some embodiments, the exemplary dimension D4 may be included in a range of about 0.2 microns to about 5 microns. If the exemplary dimension D4 is less than about 0.2 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too high to trigger activation of the associated ESD protection circuit 204, thereby increasing the likelihood of damage to the device circuit 202. If the exemplary dimension D4 is greater than about 5 microns, the lateral size of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0072] Another exemplary dimension D5 may include a spacing or distance between an outer edge of the n+ region 310 and an outer edge of an n+ region 314 included in the n+ region 310. The n+ region 310 and the n+ region 314 may be included in the n-type doped base 220 of the PNP ESD trigger device 218 of the ESD trigger circuit 206. In some embodiments, the exemplary dimension D5 may be included in a range of about 0.2 microns to about 5 microns. If the exemplary dimension D5 is less than about 0.2 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too high to trigger activation of the associated ESD protection circuit 204, thereby increasing the likelihood of damage to the device circuit 202. If the exemplary dimension D5 is greater than about 5 microns, the lateral dimensions of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0073] Another exemplary dimension D6 may include a spacing or distance between an outer edge of the P-type doped well 304 and an outer edge of a p+ region 308 included in the P-type doped well 304. The P-type doped well 304 and the p+ region 308 may be included in a terminal 326 or a P-type doped collector 224 of a PNP ESD trigger device 218 of the ESD trigger circuit 206. In some embodiments, the exemplary dimension D6 may be included in a range of about 0.2 microns to about 5 microns. If the exemplary dimension D6 is less than about 0.2 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too high to trigger activation of the associated ESD protection circuit 204, thereby increasing the likelihood of damage to the device circuit 202. If the exemplary dimension D6 is greater than about 5 microns, the lateral dimensions of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0074] Another exemplary dimension D7 may include a spacing or distance between an outer edge of the p+ region 308 and an outer edge of a p+ region 312 included in the p+ region 308. The p+ region 308 and the p+ region 312 may be included in the terminal 326 or the P-type doped collector 224 of the PNP ESD trigger device 218 of the ESD trigger circuit 206. In some embodiments, the exemplary dimension D7 may be included in a range of about 0.2 microns to about 5 microns. If the exemplary dimension D7 is less than about 0.2 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too high to trigger the activation of the associated ESD protection circuit 204, thereby increasing the possibility of damage to the device circuit 202. If the exemplary dimension D7 is greater than about 5 microns, the lateral size of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0075] Another exemplary dimension D8 may include a spacing or distance between an outer edge of the n+ region 310 and an outer edge of a p+ region 312 included in the n+ region 310. The n+ region 310 and the p+ region 312 may be included in a P-type doped emitter 222 of a PNP ESD trigger device 218 of the ESD trigger circuit 206. In some embodiments, the exemplary dimension D8 may be included in a range of about 0.2 microns to about 5 microns. If the exemplary dimension D8 is less than about 0.2 microns, the breakdown voltage of the PNP ESD trigger device 218 may be too high to trigger activation of the associated ESD protection circuit 204, thereby increasing the likelihood of damage to the device circuit 202. If the exemplary dimension D8 is greater than about 5 microns, the lateral dimensions of the ESD trigger circuit 206 may increase, thereby reducing the device density in the semiconductor device. However, other ranges of values ​​are also within the scope of the present disclosure.

[0076] Another exemplary dimension D9 may include the width of the RPO structure 318 included in the PNP ESD trigger device 218 of the ESD trigger circuit 206. In some embodiments, the exemplary dimension D9 may be included in a range of about 0.5 microns to about 3 microns. If the exemplary dimension D9 is less than about 0.5 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to allow the associated device circuit 202 to achieve high voltage operation (e.g., lower than the operating voltage of the associated device circuit 202). If the exemplary dimension D9 is greater than about 3 microns, the on-resistance (R on ) may be relatively high and result in reduced operating efficiency of the ESD trigger circuit 206. However, other ranges of values ​​are also within the scope of the present disclosure.

[0077] Another exemplary dimension D10 includes the thickness of the STI region 316 included in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D10 may be included in a range of about 0.1 microns to about 50 microns. If the exemplary dimension D10 is less than about 0.1 microns, the STI region 316 may not provide sufficient electric field suppression in the ESD trigger circuit 206, resulting in reduced electrical isolation in the ESD trigger circuit 206. If the exemplary dimension D10 is greater than about 50 microns, the on-resistance (R on ) may be relatively high and result in reduced operating efficiency of the ESD trigger circuit 206. However, other ranges of values ​​are also within the scope of the present disclosure.

[0078] Another exemplary dimension D11 includes the width of the n-type doped barrier region 320 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D11 may be included in a range of about 1 micron to about 10 microns. If the exemplary dimension D11 is less than about 1 micron, the n-type doped barrier region 320 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D11 is greater than about 10 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0079] Another exemplary dimension D12 includes the thickness of the n-type doped barrier region 320 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D12 may be included in a range of about 1 micron to about 10 microns. If the exemplary dimension D12 is less than about 1 micron, the n-type doped barrier region 320 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D12 is greater than about 10 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0080] Another exemplary dimension D13 includes the lateral extension of the n-type doped barrier region 320 from the outer edge of the n-type doped well 306 above the n-type doped barrier region 320. In some embodiments, the exemplary dimension D13 may be included in a range of about -5 microns (meaning that the n-type doped barrier region 320 does not extend laterally outward from the outer edge of the n-type doped well 306) to about 5 microns. If the exemplary dimension D13 is less than about -5 microns, the n-type doped barrier region 320 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D13 is greater than about 5 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0081] Another exemplary dimension D14 includes the spacing or distance between n-type doped barrier regions 320 in the ESD trigger circuit 206. The exemplary dimension D14 may correspond to the width of the portion 322 of the substrate 302 between the n-type doped barrier regions 320. In some embodiments, the exemplary dimension D14 may be included in the range of about 1 micron to about 10 microns. If the exemplary dimension D14 is less than about 1 micron, the breakdown voltage of the ESD trigger circuit 206 may be too low to allow the associated device circuit 202 to achieve high voltage operation (e.g., lower than the operating voltage of the associated device circuit 202) because the PNP ESD trigger device 218 may break down between the p-type doped well 304 of the PNP ESD trigger device 218 and the n-type doped barrier region 320. If the exemplary dimension D14 is greater than about 10 microns, the n-type doped barrier region 320 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. However, other ranges of values ​​are also within the scope of the present disclosure.

[0082] Figure 3C Another exemplary embodiment 328 of the ESD trigger circuit 206 that may be included in a semiconductor device is shown. Figure 3C As shown, an exemplary embodiment 328 of the ESD trigger circuit 206 may include a Figure 3A and Figure 3BThe exemplary embodiment 300 of the ESD trigger circuit 206 shown and described may include an arrangement of layers and / or structures similar to those of the exemplary embodiment 300 of the ESD trigger circuit 206. For example, the exemplary embodiment 328 of the ESD trigger circuit 206 may include components 302-324, except that the RPO structure 318 is omitted. Instead, the STI region 316 is included between the p-type doped emitter 222 and the p-type doped collector 224 (e.g., above the portion 324 of the substrate 302 between the p-type doped emitter 222 and the p-type doped collector 224). Including the STI region 316 instead of the RPO structure 318 reduces the process cost and complexity of manufacturing the ESD trigger circuit 206 because the STI region 316 can be formed together with other STI regions 316 in the ESD trigger circuit 206 and therefore does not require additional processing operations to form. However, the RPO structure 318 in the exemplary embodiment 300 of the ESD trigger circuit 206 may provide the ESD trigger circuit 206 with a lower on-resistance (R on ) and / or increased ESD protection triggering performance relative to the STI region 316.

[0083] As mentioned above, providing FIG. 3A to FIG. 3C As an example. Other examples can be related to FIG. 3A to FIG. 3C Described differently.

[0084] FIG. 4A to FIG. 4J is a diagram of an exemplary embodiment 400 for forming an ESD trigger circuit 206 in a semiconductor device described herein. Although the exemplary embodiment 400 includes forming a combination Figure 3A and Figure 3B The example of an exemplary implementation 300 of the ESD trigger circuit 206 is shown and described, but in combination with FIG. 4A to FIG. 4J The semiconductor processing operations and / or techniques (or a subset thereof) shown and described may still be used to manufacture other exemplary embodiments of the ESD protection circuit 206 shown and described herein. FIG. 4A to FIG. 4J One or more of the semiconductor processing operations described herein are performed in conjunction with Figure 1 In some embodiments, the method may be performed by one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 described herein. FIG. 4A to FIG. 4J One or more of the semiconductor processing operations described herein are performed by Figure 1 The process may be performed by one or more semiconductor processing tools not shown.

[0085] Steering Figure 4A, a substrate 302 may be provided. The substrate 302 may be provided as a semiconductor wafer, a semiconductor die, and / or another type of semiconductor substrate. In some embodiments, the substrate 302 may be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and / or another type of doped substrate. In some embodiments, the substrate 302 has a bulk resistivity (or volume resistivity) included in a range of about 1 ohm-cm to about 100 ohm-cm. However, other ranges of values ​​are also within the scope of the present disclosure.

[0086] like Figure 4B As shown, one or more barrier layer implantation operations may be performed to form n-type doped barrier regions 320 in substrate 302. N-type doped barrier regions 320 may be formed below the surface of substrate 302. Furthermore, n-type doped barrier regions 320 may be formed such that n-type doped barrier regions 320 are spaced apart from each other by portions 322 of substrate 302.

[0087] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form an n-type doped barrier region 320 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 302 to form an n-type doped barrier region 320. The ion implantation tool 114 may direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask may be formed on the substrate 302, and the n-type doped barrier regions 320 may be formed using a pattern formed in the implantation mask so that the n-type doped barrier regions 320 are spaced apart from each other by portions 322 of the substrate 302. In some embodiments, the n-type doped barrier regions 320 may be formed such that a concentration (e.g., of an n-type dopant) in the n-type doped barrier regions 320 may include about 1×10 17 n-type ions to about 1x10 per cubic centimeter 21 However, other value ranges are also within the scope of the present disclosure.

[0088] like Figure 4C As shown, an STI formation operation is performed to form an STI region 316 in the substrate 302. The STI region 316 can be formed over the n-type doped barrier region 320. In some embodiments, one or more other semiconductor processing operations, such as an epitaxial operation, are performed after the one or more well implant operations and before the STI formation operation to form one or more source / drain regions of the transistor 314 in the device circuit 202 of the semiconductor device. To form the STI region 316, a recess can be formed in the substrate 302, and a material for the STI region 316 can be deposited in the recess.

[0089] In some embodiments, the substrate 302 is etched using the pattern in the photoresist layer to form the grooves. In such embodiments, the deposition tool 102 forms a photoresist layer on the substrate 302. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes a portion of the photoresist layer to expose the pattern. The etching tool 108 etches the substrate 302 based on the pattern to form grooves in the substrate 302. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching the substrate 302 based on the pattern.

[0090] Deposition tool 102 can be used for PVD operation, ALD operation, CVD operation, epitaxial operation, oxidation operation, combination Figure 1 The material of STI regions 316 is deposited in another type of deposition operation and / or another suitable deposition operation as described. In some embodiments, after deposition tool 102 deposits STI regions 316 , planarization tool 110 planarizes STI regions 316 .

[0091] like Figure 4D As shown, one or more well implantation operations may be performed to form an n-type doped well 306 in the substrate 302. The n-type doped well 306 may be formed below the surface of the substrate 302. In addition, the n-type doped well 306 may be formed above and / or on the n-type doped barrier region 320. Forming the n-type doped well 306 may be part of a process of forming an n-type doped base 220 of a PNP ESD trigger device 218 included in the ESD trigger circuit 206, and / or may be part of a process of forming a p-type doped emitter 222 of the PNP ESD trigger device 218.

[0092] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form an n-type doped well 306 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 302 to form an n-type doped well 306. The ion implantation tool 114 may direct an ion beam toward the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask may be formed on the substrate 302, and the n-type doped well 306 may be formed over and / or on the n-type doped barrier region 320 using a pattern formed in the implantation mask.

[0093] like Figure 4EAs shown, one or more n+ implant operations may be performed to form n+ regions 310 in substrate 302. N+ regions 310 may be formed in n-type doped wells 306. In this manner, each n+ region 310 is included within an associated n-type doped well 306. Forming n+ regions 310 may be part of a process of forming an n-type doped base 220 of a PNP ESD trigger device 218 included in the ESD trigger circuit 206, and / or may be part of a process of forming a p-type doped emitter 222 of the PNP ESD trigger device 218.

[0094] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form the n+ region 310 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 302 to form the n+ region 310. The ion implantation tool 114 can direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask can be formed on the substrate 302, and the n+ region 310 can be formed in the n-type doped well 306 using the pattern formed in the implantation mask.

[0095] like Figure 4F As shown, one or more well implantation operations may be performed to form a p-type doped well 304 in the substrate 302. Forming the p-type doped well 304 may be part of a process for forming one or more terminals 326 of an ESD protection circuit and / or a process for forming a p-type doped collector 224 of a PNP ESD trigger device 218 included in the ESD trigger circuit 206.

[0096] The p-type doped well 304 may be formed below the surface of the substrate 302 and adjacent to one or more n-type doped wells 306. The p-type doped well 304 may be formed above and / or on portions 322 of the substrate 302 between the n-type doped barrier regions 320. Furthermore, the p-type doped well 304 may be formed such that the p-type doped well 304 is separated or spaced apart from adjacent n-type doped wells 306 by portions 324 of the substrate 302.

[0097] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form a p-type doped well 304 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., p-type ions) into the substrate 302 to form a p-type doped well 304. The ion implantation tool 114 can direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask can be formed on the substrate 302, and the p-type doped well 304 can be formed over and / or above the portion 322 in the substrate using the pattern formed in the implantation mask. In addition, the p-type doped well 304 can be formed between adjacent n-type doped wells 306 using the pattern formed in the implantation mask so that the portion 324 of the substrate 302 separates or isolates the p-type doped well 304 from the adjacent n-type doped well 306.

[0098] like Figure 4G As shown, one or more p+ implant operations may be performed to form p+ regions 308 in substrate 302. P+ regions 308 may be formed in p-type doped wells 304. In this manner, each p+ region 308 is included within an associated p-type doped well 304.

[0099] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form the p+ region 308 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., p-type ions) into the substrate 302 to form the p+ region 308. The ion implantation tool 114 can direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask can be formed on the substrate 302, and the p+ region 308 can be formed in the p-type doped well 304 using the pattern formed in the implantation mask.

[0100] In some embodiments, in combination Figures 4D to 4G The operations shown and described may be performed in another order. For example, n-type doped well 306 may be formed, followed by p-type doped well 304, followed by n+ region 310, followed by p+ region 308. As another example, n-type doped well 306 may be formed, followed by p-type doped well 304, followed by p+ region 308, followed by n+ region 310. As another example, p-type doped well 304 may be formed, followed by n-type doped well 306, followed by p+ region 308, followed by n+ region 310. As another example, p-type doped well 304 may be formed, followed by n-type doped well 306, followed by n+ region 310, followed by p+ region 308.

[0101] like Figure 4HAs shown, one or more n+ implant operations may be performed to form n+ region 314 in substrate 302. As part of the process of forming PNP ESD trigger device 218 included in ESD trigger circuit 206, n+ region 314 may be formed in n+ region 310 of n-type doped base 220.

[0102] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form the n+ region 314 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 302 to form the n+ region 314. The ion implantation tool 114 can direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask can be formed on the substrate 302, and the n+ region 314 can be formed in the n+ region 310 of the n-type doped base 220 using a pattern formed in the implantation mask.

[0103] like Fig. 4I As shown, one or more p+ implant operations may be performed to form a p+ region 312 in the substrate 302. As part of the process of forming the PNP ESD trigger device 218 included in the ESD trigger circuit 206, the p+ region 312 may be formed in the n+ region 310 of the p-type doped emitter 222. As part of the process of forming the PNP ESD trigger device 218 included in the ESD trigger circuit 206, another p+ region 312 may be formed in the p+ region 308 of the p-type doped collector 224. Another p+ region 312 may be formed in the p+ region 308 of the terminal 326 of the ESD trigger circuit 206.

[0104] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form the p+ region 312 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., p-type ions) into the substrate 302 to form the p+ region 312. The ion implantation tool 114 may direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask may be formed on the substrate 302, and the p+ region 312 may be formed in the n+ region 310 of the p-type doped emitter 222, in the p+ region 308 of the p-type doped collector 224, and / or in the p+ region 308 of the terminal 326 using the pattern formed in the implantation mask.

[0105] In some embodiments, in combination Figure 4H and Fig. 4I The operations shown and described may be performed in another order. For example, the p+ region 312 may be formed, and the n+ region 314 may be formed after the p+ region 312 is formed. Additionally and / or alternatively, in combination with Figures 4D to 4G After the operations shown and described and in conjunction with Figure 4H and Fig. 4I The operations shown and described are preceded by one or more other semiconductor processing operations, such as gate polysilicon operations, to form one or more gate structures of transistor 314 in device circuit 202 of the semiconductor device.

[0106] like Figure 4J As shown, an RPO forming operation may be performed to form an RPO structure 318 on and / or on the surface of the substrate 302. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a bonding operation, or a bonding operation. Figure 1 The material of the RPO structure 318 is deposited in another type of deposition operation as described above, and / or in another suitable deposition operation. In some embodiments, after the deposition tool 102 deposits the RPO structure 318, the planarization tool 110 planarizes the RPO structure 318. In some embodiments, the material of the RPO structure 318 is deposited as a blanket layer, and the etching tool 108 performs an etch-back operation to remove a portion of the blanket layer, wherein the remaining portion of the blanket layer corresponds to the RPO structure 318.

[0107] The RPO structure 318 may be formed such that the RPO structure 318 is included over and / or on a portion 324 of the substrate 302 between the p-type doped well 304 of the p-type doped collector 224 and the n-type doped well 306 of the p-type doped emitter 222. In some embodiments, the RPO structure 318 may be formed such that the RPO structure 318 is included over and / or on a portion of the p-type doped well 304, over and / or on a portion of the n-type doped well 306, over and / or on a portion of the p+ region 308 of the p-type doped collector 224, and / or over and / or on a portion of the n+ region 310 of the p-type doped emitter 222, among other examples.

[0108] As an alternative to performing an RPO formation operation to form RPO structure 318, RPO structure 318 may be omitted and an additional STI region 316 may be formed in the substrate as a bonding Figure 4C These additional STI regions 316 may be formed such that additional STI regions 316 are located over and / or on portions 324 of substrate 302 between p-doped well 304 of p-doped collector 224 and n-doped well 306 of p-doped emitter 222 .

[0109] As noted above, providing FIG. 4A to FIG. 4J As an example. Other examples can be related to FIG. 4A to FIG. 4J Different than described.

[0110] FIG. 5A to FIG. 5C is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. FIG. 5A to FIG. 5C The described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0111] Figure 5A and Figure 5B FIG. 5 is an exemplary implementation 500 of the ESD trigger circuit 206. Figure 5A As shown, an exemplary embodiment 500 of the ESD trigger circuit 206 may include a Figure 3A and Figure 3B The exemplary embodiment 500 of the ESD trigger circuit 206 may include components 302-324, except that it includes an n-type doped barrier strip 502 in place of one or more of the portions 322 of the substrate 302 between adjacent n-type doped barrier regions 320. The n-type doped barrier strip 502 may be included below the p-type doped well 304 of the p-type doped collector 224 in the PNP ESD trigger device 218 of the ESD trigger circuit 206, and may provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320) with minimal breakdown voltage reduction of the PNP ESD trigger device 218. In some embodiments, the n-type doped barrier strip 502 is omitted below one or more of the terminals 326 of the ESD trigger circuit 206. In some embodiments, an n-type doped barrier strip 502 is included beneath the p-type doped well 304 of one or more terminals 326 of the ESD trigger circuit 206 .

[0112] The n-type doped barrier strip 502 includes a dopant concentration and dopant type similar to the n-type doped barrier region 320. The exemplary embodiment 500 of the ESD trigger circuit 206 may be similar to the combination of FIG. 4A to FIG. 4J The n-type doped barrier strip 502 may be formed by a set of semiconductor processing operations shown and described. Figure 4B The embodiments are shown and described as being formed as part of one or more barrier layer implant operations.

[0113] Figure 5BFIG. 2 shows several exemplary dimensions of an exemplary embodiment 500 of the ESD trigger circuit 206. In some embodiments, one or more other exemplary embodiments of the ESD protection circuit 206 described herein may include a combination of Figure 5B One or more of the dimensions shown and described.

[0114] The exemplary dimension D15 includes the width of the n-type doped barrier strip 502 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D15 may be included in a range of about 0.2 microns to about 3 microns. If the exemplary dimension D15 is less than about 0.2 microns, the n-type doped barrier strip 502 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D15 is greater than about 3 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0115] Another exemplary dimension D16 includes the spacing between adjacent n-type doped barrier strips 502 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D16 may be included in a range of about 0.2 microns to about 3 microns. If the exemplary dimension D16 is less than about 0.2 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). If the exemplary dimension D16 is greater than about 3 microns, the n-type doped barrier strips 502 may not provide sufficient blocking of charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. However, other ranges of values ​​are also within the scope of the present disclosure.

[0116] In some embodiments, the number of n-type doped barrier strips 502 included under a particular p-type doped well 304 may be in the range of 2 to 10. If the number is less than 2, the n-type doped barrier strips 502 may provide only a minimal increase in electrical isolation. If the number is greater than 10, patterning the n-type doped barrier strips 502 may increase the complexity of implanting a mask to form the n-type doped barrier strips 502, which may result in an increased defect rate in the n-type doped barrier strips 502.

[0117] Figure 5C Another exemplary embodiment 504 of an ESD trigger circuit 206 that may be included in a semiconductor device is shown. Figure 5C As shown, an exemplary embodiment 504 of the ESD trigger circuit 206 may include a Figure 3C 328 of the ESD trigger circuit 206 shown and described. For example, the exemplary embodiment 504 of the ESD trigger circuit 206 may include components 302-316 and 320-324, except that it includes an n-type doped barrier strip 502 to replace the portion 322 of the substrate 302 between adjacent n-type doped barrier regions 320. The n-type doped barrier strip 502 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage. The n-type doped barrier strip 502 includes a similar dopant concentration and dopant type as the n-type doped barrier region 320.

[0118] An exemplary embodiment 504 of the ESD trigger circuit 206 may be implemented similarly to a combination of FIG. 4A to FIG. 4J The n-type doped barrier strip 502 may be formed by a set of semiconductor processing operations shown and described. Figure 4B The embodiments are shown and described as being formed as part of one or more barrier layer implant operations.

[0119] As noted above, providing FIG. 5A to FIG. 5C As an example. Other examples can be related to FIG. 5A to FIG. 5C Different than described.

[0120] FIG. 6A to FIG. 6C is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. FIG. 6A to FIG. 6C The described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0121] Fig. 6A and 6B FIG. 6 is an exemplary implementation 600 of the ESD trigger circuit 206. Fig. 6A As shown, an exemplary embodiment 600 of the ESD trigger circuit 206 may include a Figure 3A and Figure 3BThe exemplary embodiment 600 of the ESD trigger circuit 206 may include components 302-324. The exemplary embodiment 600 of the ESD trigger circuit 206 may also include a deep n-type doped barrier layer 602. The deep n-type doped barrier layer 602 may be included below the n-type doped barrier region 320 and / or below the n-type doped barrier region 320 and may provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the breakdown voltage of the PNP ESD trigger device 218 is minimally reduced due to the distance between the deep n-type doped barrier layer 602 and the p-type doped well 304 in the ESD trigger circuit 206.

[0122] The deep n-type doped barrier layer 602 may include a continuous layer extending continuously between and below the plurality of n-type doped barrier regions 320. The deep n-type doped barrier layer 602 may include a similar dopant concentration and dopant type as the n-type doped barrier regions 320. The exemplary embodiment 600 of the ESD trigger circuit 206 may be formed by combining a plurality of n-type doped barrier regions 320 and a plurality of n-type doped barrier regions 320. FIG. 4A to FIG. 4J The deep n-type doped barrier layer 602 may be formed by combining the semiconductor processing operations shown and described. Figure 4B One or more barrier layers are shown and described before or after implantation operations to form the n-type doped barrier region 320 .

[0123] Figure 6B FIG. 6 shows several exemplary dimensions of an exemplary embodiment 600 of the ESD trigger circuit 206. In some embodiments, one or more other exemplary embodiments of the ESD protection circuit 206 described herein may include a combination of Figure 6B One or more of the dimensions shown and described.

[0124] Another exemplary dimension D17 includes the thickness of the deep n-type doped barrier layer 602 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D17 may be included in the range of about 1 micron to about 10 microns. If the exemplary dimension D17 is less than about 1 micron, the deep n-type doped barrier layer 602 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D17 is greater than about 10 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0125] Another exemplary dimension D18 includes the lateral extension of the deep n-doped barrier layer 602 from the outer edge of the n-doped barrier region 320 above the deep n-doped barrier layer 602. In some embodiments, the exemplary dimension D18 may be included in a range of about -5 microns (meaning that the deep n-doped barrier layer 602 does not extend laterally outward from the outer edge of the n-doped barrier region 320) to about 5 microns. If the exemplary dimension D18 is less than about -5 microns, the deep n-doped barrier layer 602 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D18 is greater than about 5 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0126] Figure 6C Another exemplary embodiment 604 of the ESD trigger circuit 206 that may be included in a semiconductor device is shown. Figure 6C As shown, an exemplary embodiment 604 of the ESD trigger circuit 206 may include a Figure 3C 328 of the ESD trigger circuit 206 shown and described. For example, the exemplary embodiment 604 of the ESD trigger circuit 206 may include the components 302-316 and 320-324. The exemplary embodiment 604 of the ESD trigger circuit 206 may also include a deep n-type doped barrier layer 602. The deep n-type doped barrier layer 602 may be included below the n-type doped barrier region 320 and / or below the n-type doped barrier region 320, and may provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the breakdown voltage of the PNP ESD trigger device 218 is minimally reduced due to the distance between the deep n-type doped barrier layer 602 and the p-type doped well 304 in the ESD trigger circuit 206.

[0127] The deep n-type doped barrier layer 602 may include a continuous layer extending continuously between and below the plurality of n-type doped barrier regions 320. The deep n-type doped barrier layer 602 may include a similar dopant concentration and dopant type as the n-type doped barrier regions 320. An exemplary embodiment 604 of the ESD trigger circuit 206 may be formed by combining a plurality of n-type doped barrier regions 320 and a plurality of n-type doped barrier regions 320. FIG. 4A to FIG. 4J The deep n-type doped barrier layer 602 may be formed by combining the semiconductor processing operations shown and described. Figure 4B One or more barrier layers are shown and described before or after implantation operations to form the n-type doped barrier region 320 .

[0128] As noted above, providing FIG. 6A to FIG. 6C As an example. Other examples can be related to FIG. 6A to FIG. 6C Different than described.

[0129] FIG. 7A to FIG. 7C is a diagram of an exemplary embodiment 700 for forming an ESD trigger circuit 206 in a semiconductor device described herein. Although the exemplary embodiment 700 includes forming a combination Fig. 6A and Figure 6B The example of an exemplary implementation 600 of the ESD trigger circuit 206 is shown and described, but in combination with FIG. 7A to FIG. 7C The semiconductor processing operations and / or techniques (or a subset thereof) shown and described may still be used to manufacture other exemplary embodiments of the ESD protection circuit 206 shown and described herein. FIG. 7A to FIG. 7C One or more of the semiconductor processing operations described herein are performed in conjunction with Figure 1 In some embodiments, the method may be performed by one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 described herein. FIG. 7A to FIG. 7C One or more of the semiconductor processing operations described herein are performed by Figure 1 The process may be performed by one or more semiconductor processing tools not shown.

[0130] Steering Fig. 7A , a substrate 302 may be provided. The substrate 302 may be provided as a semiconductor wafer, a semiconductor die, and / or another type of semiconductor substrate. In some embodiments, the substrate 302 may be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and / or another type of doped substrate. In some embodiments, the substrate 302 has a bulk resistivity (or volume resistivity) included in a range of about 1 ohm-cm to about 100 ohm-cm. However, other ranges of values ​​are also within the scope of the present disclosure.

[0131] like Fig. 7A As further shown, a barrier layer implantation operation may be performed to form a deep n-type doped barrier layer 602 in the substrate 302. The deep n-type doped barrier layer 602 may be formed below the surface of the substrate 302.

[0132] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form the deep n-type doped barrier layer 602 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 302 to form the deep n-type doped barrier layer 602. The ion implantation tool 114 can direct an ion beam toward the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. In some embodiments, the deep n-type doped barrier layer 602 can be formed such that the concentration of (e.g., n-type dopant) in the deep n-type doped barrier layer 602 can include about 1×10 17 n-type ions to about 1x10 per cubic centimeter 21 However, other value ranges are also within the scope of the present disclosure.

[0133] like Figure 7B As shown, one or more barrier layer implant operations may be performed to form n-type doped barrier regions 320 in substrate 302. N-type doped barrier regions 320 may be formed below the surface of substrate 302. N-type doped barrier regions 320 may be formed such that n-type doped barrier regions 320 are spaced apart from each other by portions 322 of substrate 302. Additionally, n-type doped barrier regions 320 may be formed above and / or on deep n-type doped barrier layer 602.

[0134] In some embodiments, the ion implantation tool 114 performs one or more well implantation operations to form an n-type doped barrier region 320 in the substrate 302 by performing an ion implantation operation to implant ions (e.g., n-type ions) into the substrate 302 to form an n-type doped barrier region 320. The ion implantation tool 114 may direct an ion beam to the substrate 302 so that the ions are implanted below the surface of the substrate 302 to dope the substrate 302. An implantation mask may be formed on the substrate 302, and the n-type doped barrier regions 320 may be formed using a pattern formed in the implantation mask so that the n-type doped barrier regions 320 are spaced apart from each other by portions 322 of the substrate 302. In some embodiments, the n-type doped barrier regions 320 may be formed such that a concentration (e.g., of an n-type dopant) in the n-type doped barrier regions 320 may include about 1×10 17 n-type ions to about 1x10 per cubic centimeter 21 However, other value ranges are also within the scope of the present disclosure.

[0135] In some embodiments, the ion implantation tool 114 forms the n-type doped barrier region 320 before forming the deep n-type doped barrier layer 602. For example, the ion implantation tool 114 may form the n-type doped barrier region 320, and may form the deep n-type doped barrier layer 602 below and / or beneath the n-type doped barrier region 320 after forming the n-type doped barrier region 320.

[0136] like Figure 7C As shown, the combination can be performed FIG. 4C to FIG. 4J Other semiconductor processing operations are shown and described to form the exemplary embodiment 600 of the ESD trigger circuit 206 (and / or the exemplary embodiment 604 of the ESD trigger circuit 206 , and / or another exemplary embodiment of the ESD trigger circuit 206 described herein).

[0137] As noted above, providing FIG. 7A to FIG. 7C As an example. Other examples can be related to FIG. 7A to FIG. 7C Different than described.

[0138] FIG. 8A to FIG. 8C is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. FIG. 8A to FIG. 8C The described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0139] Fig. 8A and 8B FIG. 8 is an exemplary implementation 800 of the ESD trigger circuit 206. Fig. 8A As shown, an exemplary embodiment 800 of the ESD trigger circuit 206 may include a Figure 3A and Figure 3BThe exemplary embodiment 800 of the ESD trigger circuit 206 may include components 302-324. The exemplary embodiment 800 of the ESD trigger circuit 206 may also include a plurality of deep n-type doped barrier regions 802. The deep n-type doped barrier regions 802 may be included below and / or below the n-type doped barrier region 320 and may provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320). Adjacent deep n-type doped barrier regions 802 may be spaced or separated by a portion 804 of the substrate 302 below and / or below the p-type doped well 304 of the p-type doped collector 224 of the ESD trigger circuit 206, thereby providing a PNP ESD trigger device 218 with a minimal reduction in breakdown voltage. Portions 804 of substrate 302 may be located below portions 322 of substrate 302 between adjacent n-type doped barrier regions 320 and / or below portions 322 .

[0140] The deep n-type doped barrier region 802 may include a dopant concentration and dopant type similar to the n-type doped barrier region 320. The exemplary embodiment 800 of the ESD trigger circuit 206 may be similar to the combination of FIG. 4A to FIG. 4J and / or FIG. 7A to FIG. 7C The semiconductor processing operations shown and described are formed by Fig. 7A The deep n-type doped barrier region 802 is formed in place of the deep n-type doped barrier layer 602 in the barrier layer formation operation shown and described. The deep n-type doped barrier region 802 may be formed in combination with Figure 4B and / or Figure 7B One or more barrier layers are shown and described before or after implantation operations to form the n-type doped barrier region 320 .

[0141] Figure 8B FIG. 8 is a diagram showing several exemplary dimensions of an exemplary embodiment 800 of the ESD trigger circuit 206. In some embodiments, one or more other exemplary embodiments of the ESD protection circuit 206 described herein may include a combination of Figure 8B One or more of the dimensions shown and described.

[0142] Another exemplary dimension D19 includes the thickness of the deep n-type doped barrier region 802 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D19 may be included in a range of about 1 micron to about 10 microns. If the exemplary dimension D19 is less than about 1 micron, the deep n-type doped barrier region 802 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D19 is greater than about 10 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0143] Another exemplary dimension D20 includes the width of the deep n-type doped barrier region 802 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D20 may be included in a range of about 1 micron to about 5 microns. If the exemplary dimension D20 is less than about 1 micron, the deep n-type doped barrier region 802 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D20 is greater than about 5 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0144] Another exemplary dimension D21 includes the lateral extension of the deep n-doped barrier region 802 from the outer edge of the n-doped barrier region 320 above the deep n-doped barrier region 802. In some embodiments, the exemplary dimension D21 may be included in a range of about -5 microns (meaning that the deep n-doped barrier region 802 does not extend laterally outward from the outer edge of the n-doped barrier region 320) to about 5 microns. If the exemplary dimension D21 is less than about -5 microns, the deep n-doped barrier region 802 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D21 is greater than about 5 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0145] Another exemplary dimension D22 includes the spacing or distance between adjacent deep n-type doped barrier regions 802 in the ESD trigger circuit 206. The exemplary dimension D22 may correspond to the width of the portion 804 of the substrate 302 between adjacent deep n-type doped barrier regions 802. In some embodiments, the exemplary dimension D22 may be included in a range of about 0.5 microns to about 5 microns. If the exemplary dimension D22 is less than about 0.5 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202) because the PNP ESD trigger device 218 may break down between the p-type doped well 304 of the PNP ESD trigger device 218 and the deep n-type doped barrier region 802. If the exemplary dimension D22 is greater than about 5 microns, the deep n-type doped barrier region 802 may not provide adequate blocking of charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. However, other ranges of values ​​are also within the scope of the present disclosure.

[0146] Figure 8C Another exemplary embodiment 806 of the ESD trigger circuit 206 that may be included in a semiconductor device is shown. Figure 8C As shown, an exemplary embodiment 806 of the ESD trigger circuit 206 may include a Figure 3C 328 of the ESD trigger circuit 206 shown and described. For example, the exemplary embodiment 806 of the ESD trigger circuit 206 may include components 302-316 and 320-324. The exemplary embodiment 806 of the ESD trigger circuit 206 may also include a plurality of deep n-type doped barrier regions 802. The deep n-type doped barrier regions 802 may be included below the n-type doped barrier region 320 and / or below the n-type doped barrier region 320 and may provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320). Adjacent deep n-type doped barrier regions 802 may be spaced or separated by a portion 804 of the substrate 302 below the p-type doped well 304 of the p-type doped collector 224 of the ESD trigger circuit 206 and / or below the p-type doped well 304, thereby minimizing the reduction in the breakdown voltage of the PNP ESD trigger device 218 of the ESD trigger circuit 206. Portions 804 of substrate 302 may be located below portions 322 of substrate 302 between adjacent n-type doped barrier regions 320 and / or below portions 322 .

[0147] The deep n-type doped barrier region 802 may include a similar dopant concentration and dopant type as the n-type doped barrier region 320. An exemplary embodiment 806 of the ESD trigger circuit 206 may be formed by combining FIG. 4A to FIG. 4J and / or FIG. 7A to FIG. 7C The semiconductor processing operations shown and described are formed by Fig. 7A The deep n-type doped barrier region 802 is formed in place of the deep n-type doped barrier layer 602 in the barrier layer formation operation shown and described. The deep n-type doped barrier region 802 may be formed in combination with Figure 4B and / or Figure 7B One or more barrier layers are shown and described before or after implantation operations to form the n-type doped barrier region 320 .

[0148] As noted above, providing FIG. 8A to FIG. 8C As an example. Other examples can be related to FIG. 8A to FIG. 8C Described differently.

[0149] 9A to 9C is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. 9A to 9C The described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0150] Fig. 9A and 9B FIG. 9 is an exemplary implementation 900 of the ESD trigger circuit 206. Fig. 9A As shown, an exemplary embodiment 900 of the ESD trigger circuit 206 may include a Fig. 8A and Figure 8B The exemplary embodiment 800 of the ESD trigger circuit 206 shown and described may include similar arrangements of layers and / or structures. For example, the exemplary embodiment 900 of the ESD trigger circuit 206 may include components 302-324 and 802, except that it includes a deep n-type doped barrier strip 902 in place of one or more of the portions 804 of the substrate 302 between adjacent deep n-type doped barrier regions 802. The deep n-type doped barrier strip 902 may be included below the p-type doped well 304 of the p-type doped collector 224 in the PNP ESD trigger device 218 of the ESD trigger circuit 206 and may provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320 and the deep n-type doped barrier region 802) with minimal breakdown voltage reduction of the PNP ESD trigger device 218. In some embodiments, the deep n-type doped barrier strip 902 is omitted below one or more of the terminals 326 of the ESD trigger circuit 206. In some embodiments, a deep n-type doped barrier strip 902 is included beneath the p-type doped well 304 of one or more terminals 326 of the ESD trigger circuit 206 .

[0151] The deep n-type doped barrier strip 902 includes a dopant concentration and dopant type similar to the n-type doped barrier region 320 and / or the deep n-type doped barrier region 802. The exemplary embodiment 900 of the ESD trigger circuit 206 may be formed by combining a FIG. 4A to FIG. 4J and / or FIG. 7A to FIG. 7C The deep n-type doped barrier strip 902 may be formed by a set of semiconductor processing operations shown and described. Fig. 7A The barrier layer is formed as part of the implant operation shown and described.

[0152] Fig. 9B FIG. 2 shows several exemplary dimensions of an exemplary embodiment 900 of the ESD trigger circuit 206. In some embodiments, one or more other exemplary embodiments of the ESD protection circuit 206 described herein may include a combination of Fig. 9B One or more of the dimensions shown and described.

[0153] The exemplary dimension D23 includes the width of the deep n-type doped barrier strip 902 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D23 may be included in a range of about 0.2 microns to about 3 microns. If the exemplary dimension D23 is less than about 0.2 microns, the deep n-type doped barrier strip 902 may not provide sufficient blocking to charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. If the exemplary dimension D23 is greater than about 3 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0154] Another exemplary dimension D24 includes the spacing between adjacent deep n-type doped barrier strips 902 in the ESD trigger circuit 206. In some embodiments, the exemplary dimension D24 may be included in a range of about 0.2 microns to about 3 microns. If the exemplary dimension D24 is less than about 0.2 microns, the breakdown voltage of the ESD trigger circuit 206 may be too low to enable high voltage operation of the associated device circuit 202 (e.g., lower than the operating voltage of the associated device circuit 202). If the exemplary dimension D24 is greater than about 3 microns, the deep n-type doped barrier strips 902 may not provide sufficient blocking of charge carriers migrating into the substrate 302, resulting in reduced electrical isolation and reduced operating efficiency in the ESD trigger circuit 206. However, other ranges of values ​​are also within the scope of the present disclosure.

[0155] In some embodiments, the number of deep n-type doped barrier strips 902 included under a particular p-type doped well 304 may be in the range of 2 to 10. If the number is less than 2, the deep n-type doped barrier strips 902 may only provide a minimal increase in electrical isolation. If the number is greater than 10, patterning the deep n-type doped barrier strips 902 may increase the complexity of implanting a mask to form the deep n-type doped barrier strips 902, which may result in an increased defect rate of the deep n-type doped barrier strips 902.

[0156] Fig. 9C Another exemplary embodiment 904 of the ESD trigger circuit 206 that may be included in a semiconductor device is shown. Fig. 9C As shown, an exemplary embodiment 904 of the ESD trigger circuit 206 may include a Figure 8C The exemplary embodiment 904 of the ESD trigger circuit 206 may include components 302-316, 320-324, and 802. The exemplary embodiment 904 of the ESD trigger circuit 206 may also include a deep n-type doped barrier strip 902 to replace a portion 804 of the substrate 302 between adjacent deep n-type doped barrier regions 802. The deep n-type doped barrier strip 902 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320 and / or the deep n-type doped barrier region 802) with minimal reduction in the breakdown voltage of the PNP ESD trigger device 218 of the ESD trigger circuit 206.

[0157] The deep n-type doped barrier strip 902 may include a dopant concentration and dopant type similar to the n-type doped barrier region 320 and / or the deep n-type doped barrier region 802. The exemplary embodiment 904 of the ESD trigger circuit 206 may be similar to the combination of FIG. 4A to FIG. 4J and / or FIG. 7A to FIG. 7C The deep n-type doped barrier strip 902 may be formed by a set of semiconductor processing operations shown and described. Fig. 7A The barrier layer is formed as part of the implant operation shown and described.

[0158] As noted above, providing 9A to 9C As an example. Other examples can be related to 9A to 9C Described differently.

[0159] FIG. 10A to FIG. 10F is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. FIG. 10A to FIG. 10FThe described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0160] Fig. 10A FIG. 1 is an exemplary embodiment 1000 of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig. 10A As shown, an exemplary embodiment 1000 of the ESD trigger circuit 206 may include a Figure 3C 328 of the ESD trigger circuit 206 shown and described. For example, the exemplary embodiment 1000 of the ESD trigger circuit 206 may include the components 302-316 and 324. However, in the exemplary embodiment 1000 of the ESD trigger circuit 206, the n-type doped barrier region 320 and the associated portion 322 of the substrate between the n-type doped barrier region 320 are omitted, and instead an n-type doped barrier layer 1002 is included in the substrate 302 below the p-type doped well 304 and the n-type doped well 306.

[0161] The exemplary embodiment 1000 of the ESD trigger circuit 206 may also include a field plate structure 1004 on one or more of the STI regions 316 included in the substrate. For example, the field plate structure 1004 may be included on the STI region 316 between the n-type doped base 220 and the p-type doped collector 224 of the PNP ESD trigger device 218 included in the ESD trigger circuit 206. As another example, the field plate structure 1004 may be included on the STI region 316 between the p-type doped collector 224 and the p-type doped emitter 222 of the PNP ESD trigger device 218.

[0162] The field plate structure 1004 may be included to enable control of the electric field in the PNP ESD trigger device 218. Controlling the electric field in the PNP ESD trigger device 218 enables increased charge depletion in the portion 324 of the substrate 302 (e.g., between the p-type doped collector 224 and the p-type doped emitter 222), which may enable a reduced surface electric field (RESURF) effect in the portion 324 of the substrate 302. The RESURF effect may provide enhanced charge carrier mobility in the portion 324 of the substrate 302, which may further promote breakdown of the PNP ESD trigger device 218 between the p-type doped collector 224 and the p-type doped emitter 222, even when an n-type doped barrier layer 1002 is used. Field plate structure 1004 may be biased (eg, via n-doped base 220 , via p-doped emitter 222 , via p-doped collector 224 , and / or via terminal 326 ), which reduces the peak electric field strength in substrate 302 , thereby achieving a RESURF effect.

[0163] The n-type doped barrier layer 1002 may include a dopant concentration and dopant type similar to the n-type doped barrier region 320. The field plate structure 1004 may include a polysilicon (PO) structure or another type of semiconductor structure. Additionally and / or alternatively, the field plate structure 1004 may include a metal field plate, the metal field plate including one or more metals, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, one or more metal alloys, and / or another type of conductive material. The field plate structure 1004 may also include a dielectric layer, one or more sidewall spacers, and / or another type of electrical insulation layer or structure.

[0164] The exemplary embodiment 1000 of the ESD trigger circuit 206 may be implemented by combining FIG. 4A to FIG. 4J and / or FIG. 7A to FIG. 7C As shown and described, a set of semiconductor processing operations are formed. Figure 4B and / or Figure 7B As part of one or more barrier layer implant operations shown and described, an n-type doped barrier layer 1002 may be formed in place of the n-type doped barrier region 320 .

[0165] In some embodiments, the field plate structure 1004 may be combined with Figures 4D to 4G After the operations shown and described and in conjunction with Figure 4H and Fig. 4I In some embodiments, the field plate structure 1004 may be formed prior to the operations shown and described. Fig. 4I and / or Figure 7CThe field plate structure 1004 is formed after the operations shown and described. In some embodiments, the field plate structure 1004 can be formed as part of a gate formation process for forming a gate structure of a transistor 214 of a device circuit 202 of a semiconductor device. Forming the field plate structure 1004 can include a deposition tool 102 and / or an electroplating tool 112 depositing one or more layers of material (e.g., polysilicon material, dielectric material, metal material). The deposition tool 102, the exposure tool 104, and / or the development tool 106 can form one or more patterned layers or mask layers, and the etching tool 108 can use more patterned layers or mask layers to etch the deposited layers to form the field plate structure 1004.

[0166] like Fig. 10A As further shown, exemplary dimension D25 includes the length of field plate structure 1004. In some embodiments, exemplary dimension D25 may be included in a range of about 0.1 microns to about 5 microns. If exemplary dimension D25 is less than about 0.1 microns, patterning field plate structure 1004 may increase the complexity of the patterning mask used to form field plate structure 1004, which may result in an increased defect rate in field plate structure 1004. If exemplary dimension D25 is greater than about 3 microns, the breakdown voltage of ESD trigger circuit 206 may be too low to enable high voltage operation of associated device circuit 202 (e.g., lower than the operating voltage of associated device circuit 202). However, other ranges of values ​​are also within the scope of the present disclosure.

[0167] Fig. 10B FIG. 1006 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig. 10B As shown, an exemplary embodiment 1006 of the ESD trigger circuit 206 may include a Fig. 10A 1000 of the ESD trigger circuit 206. For example, the exemplary implementation 1006 of the ESD trigger circuit 206 may include the components 302-316, 324, and 1004. However, in the exemplary implementation 1006 of the ESD trigger circuit 206, the n-type doped barrier layer 1002 is replaced by an n-type doped barrier region 320 and a related portion 322 of the substrate 302 between the n-type doped barrier region 320 to further promote the breakdown of the PNP ESD trigger device 218 between the p-type doped collector 224 and the p-type doped emitter 222. The n-type doped barrier region 320 may be included below one or more n-type doped wells 306 in the ESD trigger circuit 206.

[0168] Fig. 10C FIG. 1008 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig. 10CAs shown, an exemplary embodiment 1008 of the ESD trigger circuit 206 may include a Fig. 10B The exemplary embodiment 1008 of the ESD trigger circuit 206 shown and described may include similar arrangements of layers and / or structures. For example, the exemplary embodiment 1008 of the ESD trigger circuit 206 may include the components 302-316, 324, and 1004. However, in the exemplary embodiment 1008 of the ESD trigger circuit 206, an n-type doped barrier strip 502 is included in the portion 322 of the substrate 302 between adjacent n-type doped barrier regions 320. The n-type doped barrier strip 502 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0169] Fig. 10D FIG. 1010 illustrates an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig. 10D As shown, an exemplary embodiment 1010 of the ESD trigger circuit 206 may include a Fig. 10B The exemplary embodiment 1006 of the ESD trigger circuit 206 shown and described may have similar arrangements of layers and / or structures. For example, the exemplary embodiment 1010 of the ESD trigger circuit 206 may include components 302-316, 320-324, and 1004. However, in the exemplary embodiment 1010 of the ESD trigger circuit 206, the deep n-type doped barrier layer 602 is included below the n-type doped barrier region 320. The deep n-type doped barrier layer 602 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0170] Fig.10E FIG. 1012 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.10E As shown, an exemplary embodiment 1012 of the ESD trigger circuit 206 may include a Fig. 10B1006 of the ESD trigger circuit 206 shown and described. For example, the exemplary embodiment 1010 of the ESD trigger circuit 206 may include the components 302-316, 320-324, and 1004. However, in the exemplary embodiment 1012 of the ESD trigger circuit 206, the deep n-type doped barrier region 802 is included below the n-type doped barrier region 320. The deep n-type doped barrier region 802 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320). Adjacent deep n-type doped barrier regions 802 may be spaced or separated by a portion 804 of the substrate 302 below and / or below the p-type doped well 304 of the p-type doped collector 224 of the ESD trigger circuit 206, thereby minimizing the reduction in the breakdown voltage of the PNP ESD trigger device 218 of the ESD trigger circuit 206. Portions 804 of substrate 302 may be located below portions 322 of substrate 302 between adjacent n-type doped barrier regions 320 and / or below portions 322 .

[0171] Fig.10F FIG. 1014 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.10F As shown, an exemplary embodiment 1014 of the ESD trigger circuit 206 may include a Fig.10E The exemplary embodiment 1012 of the ESD trigger circuit 206 shown and described may have similar arrangements of layers and / or structures. For example, the exemplary embodiment 1014 of the ESD trigger circuit 206 may include components 302-316, 320-324, 802, and 1004. However, in the exemplary embodiment 1014 of the ESD trigger circuit 206, a deep n-type doped barrier strip 902 is included to replace the portion 804 of the substrate 302 between adjacent deep n-type doped barrier regions 802. The deep n-type doped barrier strip 902 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0172] As noted above, providing FIG. 10A to FIG. 10F As an example. Other examples can be related to FIG. 10A to FIG. 10F Described differently.

[0173] FIG. 11A to FIG. 11K is a diagram of an exemplary implementation of the ESD trigger circuit 206 described herein. FIG. 11A to FIG. 11KThe described exemplary implementation of the ESD trigger circuit 206 may be included in a semiconductor device, such as the semiconductor device 200 , the semiconductor device 226 , the semiconductor device 228 , and / or another semiconductor device including a high voltage device.

[0174] Fig.11A FIG. 11 is an exemplary embodiment 1100 of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11A As shown, an exemplary embodiment 1100 of the ESD trigger circuit 206 may include a Figure 3C The exemplary embodiment 1100 of the ESD trigger circuit 206 may include components 302-316 and 320-324. However, in the exemplary embodiment 1100 of the ESD trigger circuit 206, the fin structure 1102 is included in the n-type doped base 220, the p-type doped emitter 222, and / or the p-type doped collector 224 of the PNP ESD trigger device 218 in the ESD trigger circuit 206. The STI strip 1104 may be included between adjacent fin structures 1102. The fin structure 1102 and the associated STI strip 1104 may enable the PNP ESD trigger device 218 included in the ESD trigger circuit 206 to achieve an even lower on-resistance (R on ). In addition, if the transistor 214 in the device circuit 202 of the semiconductor device is implemented as a high voltage finFET, the operation for forming the fin structure 1102 can be integrated into the fin formation process for forming the fin structure of the high voltage finFET, thereby minimizing the process complexity for forming the fin structure 1102 and the associated STI strip 1104.

[0175] In some embodiments, a plurality of fin structures 1102 can be included in the n-type doped base 220 of the PNP ESD trigger device 218. The plurality of fin structures 1102 and associated STI strips 1104 can extend from the top surface of the substrate 302, through the n+ region 314 of the n-type doped base 220, and into a portion of the n+ region 310 of the n-type doped base 220. In some embodiments, the plurality of fin structures 1102 can be included in the p-type doped emitter 222 of the PNP ESD trigger device 218. The plurality of fin structures 1102 and associated STI strips 1104 can extend from the top surface of the substrate 302, through the p+ region 312 of the p-type doped emitter 222, and into a portion of the n+ region 310 of the p-type doped emitter 222. In some embodiments, the plurality of fin structures 1102 can be included in the p-type doped collector 224 of the PNP ESD trigger device 218. The plurality of fin structures 1102 and associated STI strips 1104 may extend from the top surface of the substrate 302 , through the p+ region 312 of the p-type doped collector 224 , and into a portion of the p+ region 308 of the p-type doped collector 224 .

[0176] The exemplary embodiment 1100 of the ESD trigger circuit 206 may be implemented by combining FIG. 4A to FIG. 4J and / or FIG. 7A to FIG. 7C In some embodiments, the fin structure 1102 may be formed during an operating domain (OD) definition process for forming a fin structure of the transistor 214 of the device circuit 202. The STI strip 1104 may be formed as part of an STI formation process for forming the STI region 316, during which the STI region of the transistor 214 may also be formed. Thus, the STI strip 1104 may be formed in conjunction with the STI formation process. Figure 4A , Figure 4B and / or Fig. 7A The operations shown and described are followed by the formation of the fin structure 1102. The STI strip 1104 may be used as a bonding Figure 4C The STI described is formed as part of the operation.

[0177] Forming the fin structure 1102 may include a deposition tool 102, an exposure tool 104 and / or a development tool 106 may form one or more patterned layers or mask layers on the substrate 302, and an etching tool 108 may use more patterned layers or mask layers to etch the substrate 302 to form the fin structure 1102. The deposition tool 102 may then deposit dielectric material of the STI strip 1104 in the recess formed during the fin structure formation operation.

[0178] Fig. 11B FIG. 1106 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig. 11B As shown, an exemplary embodiment 1008 of the ESD trigger circuit 206 may include a Fig.11A The exemplary embodiment 1100 of the ESD trigger circuit 206 shown and described may have similar arrangements of layers and / or structures. For example, the exemplary embodiment 1106 of the ESD trigger circuit 206 may include components 302-316, 320, 324, 1102, and 1104. However, in the exemplary embodiment 1106 of the ESD trigger circuit 206, an n-type doped barrier strip 502 is included in the portion 322 of the substrate 302 between adjacent n-type doped barrier regions 320. The n-type doped barrier strip 502 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0179] Fig. 11C FIG. 1108 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig. 11C As shown, an exemplary embodiment 1108 of the ESD trigger circuit 206 may include a Fig. 10A The exemplary embodiment 1100 of the ESD trigger circuit 206 shown and described may have similar arrangements of layers and / or structures. For example, the exemplary embodiment 1108 of the ESD trigger circuit 206 may include components 302-316, 320-324, 1102, and 1104. However, in the exemplary embodiment 1108 of the ESD trigger circuit 206, the deep n-type doped barrier layer 602 is included below the n-type doped barrier region 320. The deep n-type doped barrier layer 602 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0180] Fig.11D FIG. 11 shows an exemplary embodiment 1110 of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11D As shown, an exemplary embodiment 1110 of the ESD trigger circuit 206 may include a Fig.11A1 and 11. The exemplary embodiment 1100 of the ESD trigger circuit 206 may include components 302-316, 320-324, 1102, and 1104. However, in the exemplary embodiment 1110 of the ESD trigger circuit 206, the deep n-type doped barrier region 802 is included below the n-type doped barrier region 320. The deep n-type doped barrier region 802 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320). Adjacent deep n-type doped barrier regions 802 may be spaced or separated by a portion 804 of the substrate 302 below and / or below the p-type doped well 304 of the p-type doped collector 224 of the ESD trigger circuit 206, so that the breakdown voltage of the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction. Portions 804 of substrate 302 may be located below portions 322 of substrate 302 between adjacent n-doped barrier regions 320 and / or below portions 322 .

[0181] Fig.11E FIG. 1112 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11E As shown, an exemplary embodiment 1112 of the ESD trigger circuit 206 may include a Fig.11D The exemplary embodiment 1110 of the ESD trigger circuit 206 is shown and described with similar arrangement of layers and / or structures. For example, the exemplary embodiment 1112 of the ESD trigger circuit 206 may include components 302-316, 320-324, 802, 1102, and 1104. However, in the exemplary embodiment 1112 of the ESD trigger circuit 206, a deep n-type doped barrier strip 902 is included to replace the portion 804 of the substrate 302 between adjacent deep n-type doped barrier regions 802. The deep n-type doped barrier strip 902 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0182] Fig.11F FIG. 1114 illustrates an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11F As shown, an exemplary embodiment 1114 of the ESD trigger circuit 206 may include a Fig. 10AThe exemplary embodiment 1000 of the ESD trigger circuit 206 shown and described above may be similar to the arrangement of layers and / or structures. For example, the exemplary embodiment 1114 of the ESD trigger circuit 206 may include components 302-316, 324, 1002, and 1004. However, in the exemplary embodiment 1114 of the ESD trigger circuit 206, the fin structure 1102 is included in the n-type doped base 220, the p-type doped emitter 222, and / or the p-type doped collector 224 of the PNP ESD trigger device 218 in the ESD trigger circuit 206. The STI strip 1104 may be included between adjacent fin structures 1102. The fin structure 1102 and the associated STI strip 1104 may enable the PNP ESD trigger device 218 included in the ESD trigger circuit 206 to achieve an even lower on-resistance (R on ). In addition, if the transistor 214 in the device circuit 202 of the semiconductor device is implemented as a high voltage finFET, the operation for forming the fin structure 1102 can be integrated into the fin formation process for forming the fin structure of the high voltage finFET, thereby minimizing the process complexity for forming the fin structure 1102 and the associated STI strip 1104.

[0183] Fig.11G FIG. 1116 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11G As shown, an exemplary embodiment 1116 of the ESD trigger circuit 206 may include a Fig.11F 1 and 11. The exemplary embodiment 1114 of the ESD trigger circuit 206 may include components 302-316, 324, 1004, 1102, and 1104. However, in the exemplary embodiment 1116 of the ESD trigger circuit 206, n-type doped barrier regions 320 and associated portions 322 of the substrate 302 between the n-type doped barrier regions 320 are included instead of the n-type doped barrier layer 1002 to further promote the breakdown of the PNP ESD trigger device 218 between the p-type doped collector 224 and the p-type doped emitter 222. The n-type doped barrier regions 320 may be included under one or more n-type doped wells 306 in the ESD trigger circuit 206.

[0184] Fig.11H FIG. 1118 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11H As shown, an exemplary embodiment 1118 of the ESD trigger circuit 206 may include a Fig.11GThe exemplary embodiment 1116 of the ESD trigger circuit 206 shown and described may include similar arrangements of layers and / or structures. For example, the exemplary embodiment 1118 of the ESD trigger circuit 206 may include components 302-316, 320, 324, 1004, 1102, and 1104. However, in the exemplary embodiment 1118 of the ESD trigger circuit 206, an n-type doped barrier strip 502 is included in the portion 322 of the substrate 302 between adjacent n-type doped barrier regions 320. The n-type doped barrier strip 502 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0185] Fig.11I FIG. 1120 illustrates an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11I As shown, an exemplary embodiment 1120 of the ESD trigger circuit 206 may include a Fig.11G 1102 and 1104. The exemplary embodiment 1116 of the ESD trigger circuit 206 may include similar arrangements of layers and / or structures as shown and described. For example, the exemplary embodiment 1120 of the ESD trigger circuit 206 may include components 302-316, 320-324, 1004, 1102, and 1104. However, in the exemplary embodiment 1120 of the ESD trigger circuit 206, the deep n-type doped barrier layer 602 is included below the n-type doped barrier region 320. The deep n-type doped barrier layer 602 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNP ESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0186] Fig.11J FIG. 112 shows an exemplary implementation 1122 of an ESD trigger circuit 206 that may be included in a semiconductor device. Fig.11J As shown, an exemplary embodiment 1122 of the ESD trigger circuit 206 may include a Fig.11G11. The exemplary embodiment 1116 of the ESD trigger circuit 206 shown and described may include similar arrangements of layers and / or structures. For example, the exemplary embodiment 1122 of the ESD trigger circuit 206 may include components 302-316, 320-324, 1004, 1102, and 1104. However, in the exemplary embodiment 1122 of the ESD trigger circuit 206, the deep n-type doped barrier region 802 is included below the n-type doped barrier region 320. The deep n-type doped barrier region 802 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320). Adjacent deep n-type doped barrier regions 802 may be spaced or separated by a portion 804 of the substrate 302 below and / or below the p-type doped well 304 of the p-type doped collector 224 of the ESD trigger circuit 206, thereby minimizing the breakdown voltage reduction of the PNP ESD trigger device 218 of the ESD trigger circuit 206. Portions 804 of substrate 302 may be located below portions 322 of substrate 302 between adjacent n-doped barrier regions 320 and / or below portions 322 .

[0187] Figure 11K FIG. 1124 shows an exemplary implementation of an ESD trigger circuit 206 that may be included in a semiconductor device. Figure 11K As shown, an exemplary embodiment 1124 of the ESD trigger circuit 206 may include a Fig.11J 1 and 11. The exemplary embodiment 1122 of the ESD trigger circuit 206 may include similar arrangements of layers and / or structures as shown and described. For example, the exemplary embodiment 1124 of the ESD trigger circuit 206 may include components 302-316, 320-324, 802, 1004, 1102, and 1104. However, in the exemplary embodiment 1124 of the ESD trigger circuit 206, a deep n-type doped barrier strip 902 is included to replace the portion 804 of the substrate 302 between adjacent deep n-type doped barrier regions 802. The deep n-type doped barrier strip 902 may be included to provide additional charge carrier migration blocking (e.g., in combination with the n-type doped barrier region 320), and the PNPESD trigger device 218 of the ESD trigger circuit 206 has a minimal reduction in breakdown voltage.

[0188] As noted above, providing FIG. 11A to FIG. 11K As an example. Other examples can be related to FIG. 11A to FIG. 11K Described differently.

[0189] Fig.121200 is a diagram of exemplary components of the apparatus 1200 described herein. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may include one or more of the apparatus 1200 and / or one or more components of the apparatus 1200. Fig.12 As shown, the device 1200 may include a bus 1210 , a processor 1220 , a memory 1230 , an input component 1240 , an output component 1250 , and / or a communication component 1260 .

[0190] The bus 1210 may include one or more components that enable wired and / or wireless communication between components of the device 1200. The bus 1210 may connect components such as via operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. Fig.12 Two or more components of a computer programmable logic device are coupled together. For example, bus 1210 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1220 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or another type of processing component. Processor 1220 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1220 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0191] The memory 1230 may include volatile and / or non-volatile memory. For example, the memory 1230 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1230 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 1230 may be a non-transitory computer-readable medium. The memory 1230 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the device 1200. In some embodiments, the memory 1230 may include one or more memories coupled to one or more processors (e.g., processor 1220), such as via bus 1210. The communication coupling between the processor 1220 and the memory 1230 may enable the processor 1220 to read and / or process information stored in the memory 1230 and / or store information in the memory 1230.

[0192] Input components 1240 enable device 1200 to receive input, such as user input and / or sensed input. For example, input components 1240 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a GPS sensor, a GNSS sensor, an accelerometer, a gyroscope, and / or an actuator. Output components 1250 enable device 1200 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication components 1260 enable device 1200 to communicate with other devices via wired connections and / or wireless connections. For example, communication components 1260 may include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0193] The device 1200 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1230) may store an instruction group (e.g., one or more instructions or program codes) for execution by the processor 1220. The processor 1220 may execute the instruction group to implement one or more operations or processes described herein. In some embodiments, execution of the instruction group by one or more processors 1220 causes one or more processors 1220 and / or the device 1200 to implement one or more operations or processes described herein. In some embodiments, a fixed-line circuit system may be used in place of instructions or in combination with instructions to implement one or more operations or processes described herein. Additionally or alternatively, the processor 1220 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuit systems and software.

[0194] supply Fig.12 The number and configuration of components shown are examples. Fig.12 The device 1200 may include additional components, fewer components, different components, or components configured in a different manner than the components shown. Additionally or alternatively, a set of components (e.g., one or more components) of the device 1200 may perform one or more functions described as being performed by another set of components of the device 1200.

[0195] Fig.13 is a flow chart of an exemplary process 1300 associated with forming a semiconductor device described herein. In some embodiments, Fig.13 One or more process blocks of the process are performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102-114). Additionally, or alternatively, Fig.13One or more process blocks may be performed by one or more components of the apparatus 1200 (eg, the processor 1220 , the memory 1230 , the input component 1240 , the output component 1250 , and / or the communication component 1260 ).

[0196] like Fig.13 As shown, process 1300 may include forming a plurality of n-type doped barrier regions in a substrate of a semiconductor device (block 1310). For example, one or more of semiconductor processing tools 102-114 may form a plurality of n-type doped barrier regions 320 in substrate 302 of a semiconductor device, as described herein. The semiconductor device may be semiconductor device 200, semiconductor device 226, semiconductor device 228, and / or other semiconductor devices.

[0197] like Fig.13 As further shown, the process 1300 may include forming an n-type doped base of a PNP ESD trigger device of a semiconductor device in the substrate (block 1320). For example, one or more of the semiconductor processing tools 102-114 may form an n-type doped base 220 of a PNP ESD trigger device 218 of a semiconductor device in the substrate 302, as described herein.

[0198] like Fig.13 As further shown, the process 1300 may include forming a p-type doped collector of the PNP ESD trigger device in the substrate (block 1330). For example, one or more of the semiconductor processing tools 102-114 may form the p-type doped collector 224 of the PNP ESD trigger device 218 in the substrate 302, as described herein. In some embodiments, the first portion 324 of the substrate 302 is located between the first n-type doped well 306 of the n-type doped base and the p-type doped collector 224.

[0199] like Fig.13 As further shown, the process 1300 may include forming a p-type doped emitter of the PNP ESD trigger device in the substrate (block 1340). For example, one or more of the semiconductor processing tools 102-114 may form the p-type doped emitter 222 of the PNP ESD trigger device 218 in the substrate 302, as described herein. In some embodiments, the first n-type doped barrier region 320 is located below the first n-type doped well 306 of the n-type doped base 220. In some embodiments, the second n-type doped barrier region 320 is located below the second n-type doped well 306 of the p-type doped emitter 222. In some embodiments, the third portion 322 of the substrate 302 is located between the first n-type doped barrier region 320 and the second n-type doped barrier region 320.

[0200] Process 1300 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0201] In a first embodiment, process 1300 includes forming an STI region 316 and an RPO structure 318, wherein the STI region 316 is located above a first portion 324 of the substrate 302 and between the n-type doped base 220 and the p-type doped collector 224, and wherein the RPO structure 318 is located above a second portion 324 of the substrate 302 and between the p-type doped collector 224 and the p-type doped emitter 222.

[0202] In a second embodiment, either alone or in combination with the first embodiment, process 1300 includes forming a first STI region 316 and a second STI region 316, wherein the first STI region 316 is located above a first portion 324 of the substrate 302 and between the n-type doped base 220 and the p-type doped collector 224, and wherein the second STI region 316 is located above a second portion 324 of the substrate 302 and between the p-type doped collector 224 and the p-type doped emitter 222.

[0203] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the process 1300 includes forming a deep n-type doped barrier layer 602 in the substrate 302, wherein a plurality of n-type doped barrier regions 320 are located above the deep n-type doped barrier layer 602 in the substrate 302, and wherein the deep n-type doped barrier layer 602 extends continuously between the plurality of n-type doped barrier regions 320.

[0204] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 1300 includes forming a deep n-type doped barrier layer 602 in the substrate 302 before forming a plurality of n-type doped barrier regions 320, wherein forming a plurality of n-type doped barrier regions 320 includes forming a plurality of n-type doped barrier regions 320 above the deep n-type doped barrier layer 602.

[0205] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 1300 includes forming a plurality of deep n-doped barrier regions 802 in the substrate 302, including a first deep n-doped barrier region 802 and a second deep n-doped barrier region 802, wherein the first n-doped barrier region 320 is located above the first deep n-doped barrier region 802, wherein the second n-doped barrier region 320 is located above the second deep n-doped barrier region 802, and wherein a fourth portion 804 of the substrate 302 is located between the first deep n-doped barrier region 802 and the second deep n-doped barrier region 802.

[0206] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the process 1300 includes forming a plurality of deep n-doped barrier strips 902 in the fourth portion 804 of the substrate between the first deep n-doped barrier region 802 and the second deep n-doped barrier region 802 .

[0207] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, the process 1300 includes forming a plurality of n-type doped barrier strips 502 in the third portion 322 of the substrate 302 between the first n-type doped barrier region 320 and the second n-type doped barrier region 320 .

[0208] although Fig.13 Exemplary blocks of process 1300 are shown, but in some embodiments, Fig.13 The process 1300 may include additional blocks, fewer blocks, different blocks, or blocks configured in a different manner than those depicted. Additionally or alternatively, two or more blocks in the process 1300 may be performed in parallel.

[0209] Fig.14 is a flow chart of an exemplary process 1400 associated with forming a semiconductor device described herein. In some embodiments, Fig.14 One or more process blocks of are performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally, or alternatively, Fig.14 One or more process blocks of the apparatus 1200 may be performed by one or more components of the apparatus 1200 (eg, the processor 1220 , the memory 1230 , the input component 1240 , the output component 1250 , and / or the communication component 1260 ).

[0210] like Fig.14 As shown, process 1400 may include forming a plurality of STI regions in a substrate of a semiconductor device (block 1410). For example, one or more of semiconductor processing tools 102-114 may form a plurality of STI regions 316 in substrate 302 of a semiconductor device, as described herein. The semiconductor device may be semiconductor device 200, semiconductor device 226, semiconductor device 228, and / or other semiconductor devices.

[0211] like Fig.14As further shown, for a PNP ESD trigger device of a semiconductor device, process 1400 may include forming an n-type doped base in a substrate between a first STI region and a second STI region among multiple STI regions, forming a p-type doped collector in the substrate between a second STI region and a third STI region among multiple STI regions, and forming a p-type doped emitter in the substrate between a third STI region and a fourth STI region among multiple STI regions (block 1420). For example, for a PNP ESD trigger device 218 of a semiconductor device, one or more of the semiconductor processing tools 102-114 can form an n-type doped base 220 in the substrate 302 between a first STI region 316 and a second STI region 316 in the plurality of STI regions 316, form a p-type doped collector 224 in the substrate 302 between a second STI region 316 and a third STI region 316 in the plurality of STI regions 316, and form a p-type doped emitter 222 in the substrate 302 between a third STI region 316 and a fourth STI region 316 in the plurality of STI regions 316, as described herein. In some embodiments, a first portion 324 of the substrate 302 is located between a first n-type doped well 306 of the n-type doped base 220 and a p-type doped well 304 of the p-type doped collector 224. In some embodiments, the second portion 324 of the substrate 302 is located between the p-type doped well 304 of the p-type doped collector 224 and the second n-type doped well 306 of the p-type doped emitter 222 .

[0212] like Fig.14 As further shown, the process 1400 may include forming a first field plate structure on the second STI region (block 1430). For example, one or more of the semiconductor processing tools 102-114 may form the first field plate structure 1004 on the second STI region 316 as described herein.

[0213] like Fig.14 As further shown, the process 1400 may include forming a second field plate structure on the third STI region (block 1440 ). For example, one or more of the semiconductor processing tools 102 - 114 may form the second field plate structure 1004 on the third STI region 316 , as described herein.

[0214] Process 1400 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0215] In a first embodiment, process 1400 includes forming an n-type doped barrier layer 1002 in substrate 302 before forming a plurality of STI regions 316, wherein forming an n-type doped base 220, a p-type doped collector 224, and a p-type doped emitter 222 includes forming an n-type doped base 220, a p-type doped collector 224, and a p-type doped emitter 222 above the n-type doped barrier layer 1002.

[0216] In a second embodiment, either alone or in combination with the first embodiment, process 1400 includes forming a plurality of n-type doped barrier regions 320 in substrate 302 before forming a plurality of STI regions 316, wherein forming an n-type doped base 220 includes forming an n-type doped base 220 above a first n-type doped barrier region 320 of the plurality of n-type doped barrier regions 320, and forming a p-type doped emitter 222 includes forming a p-type doped emitter 222 above a second n-type doped barrier region 320 of the plurality of n-type doped barrier regions 320.

[0217] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the process 1400 includes forming a plurality of n-type doped barrier strips 502 in the substrate 302 between the first n-type doped barrier region 320 and the second n-type doped barrier region 320 .

[0218] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 1400 includes forming a deep n-type doped barrier layer 602 in the substrate 302 before forming the plurality of n-type doped barrier regions 320, wherein forming the plurality of n-type doped barrier regions 320 includes forming the plurality of n-type doped barrier regions 320 above the deep n-type doped barrier layer 602.

[0219] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 1400 includes forming a plurality of deep n-type doped barrier regions 802 in the substrate 302 before forming the plurality of n-type doped barrier regions 320, wherein forming the plurality of n-type doped barrier regions 320 includes forming a first n-type doped barrier region 320 above a first deep n-type doped barrier region 802 among the plurality of deep n-type doped barrier regions 802, and forming a second n-type doped barrier region 320 above a second deep n-type doped barrier region 802 among the plurality of deep n-type doped barrier regions 802.

[0220] although Fig.14 Exemplary blocks of process 1400 are shown, but in some embodiments, Fig.14 The process 1400 may include additional blocks, fewer blocks, different blocks, or blocks configured in a different manner than those depicted. Additionally or alternatively, two or more blocks in the process 1400 may be performed in parallel.

[0221] Fig.15 is a flow chart of an exemplary process 1500 associated with forming a semiconductor device described herein. In some embodiments, Fig.15 One or more process blocks of are performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114). Additionally, or alternatively, Fig.15 One or more process blocks of the apparatus 1200 may be performed by one or more components of the apparatus 1200 (eg, the processor 1220 , the memory 1230 , the input component 1240 , the output component 1250 , and / or the communication component 1260 ).

[0222] like Fig.15 As shown, process 1500 may include forming an n-type doped base of a PNP ESD trigger device of a semiconductor device in a substrate of the semiconductor device, the n-type doped base including a plurality of first fin structures (block 1510). For example, one or more of semiconductor processing tools 102-114 may form an n-type doped base 220 of a PNP ESD trigger device 218 of a semiconductor device in a substrate 302 of the semiconductor device, the n-type doped base 220 including a plurality of first fin structures 1102, as described herein. The semiconductor device may be semiconductor device 200, semiconductor device 226, semiconductor device 228, and / or other semiconductor devices.

[0223] like Fig.15 As further shown, the process 1500 may include forming a p-type doped emitter of the PNP ESD trigger device in the substrate, the p-type doped emitter including a plurality of second fin structures (block 1520). For example, one or more of the semiconductor processing tools 102-114 may form a p-type doped emitter 222 of the PNP ESD trigger device 218 in the substrate 302, the p-type doped emitter 222 including a plurality of second fin structures 1102, as described herein. In some embodiments, the first portion 324 of the substrate 302 is located between the first n-type doped well 306 of the n-type doped base 220 and the p-type doped well 304 of the p-type doped collector 224.

[0224] like Fig.15As further shown, the process 1500 may include forming a p-type doped collector of the PNP ESD trigger device in the substrate, the p-type doped collector including a plurality of third fin structures (block 1530). For example, one or more of the semiconductor processing tools 102-114 may form a p-type doped collector 224 of the PNP ESD trigger device 218 in the substrate 302, the p-type doped collector 224 including a plurality of third fin structures 1102, as described herein. In some embodiments, the second portion 324 of the substrate 302 is located between the p-type doped well 304 of the p-type doped collector 224 and the second n-type doped well 306 of the p-type doped emitter 222.

[0225] Process 1500 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0226] In a first embodiment, process 1500 includes forming a plurality of n-type doped barrier regions 320 in substrate 302, wherein a first n-type doped well 306 of n-type doped base 220 is located above a first n-type doped barrier region 320 of the plurality of n-type doped barrier regions 320, wherein a second n-type doped well 306 of p-type doped emitter 222 is located above a second n-type doped barrier region 320 of the plurality of n-type doped barrier regions 320, and wherein a third portion 322 of substrate 302 is located between the first n-type doped barrier region 320 and the second n-type doped barrier region 320.

[0227] In a second embodiment, alone or in combination with the first embodiment, the process 1500 includes forming a deep n-type doped barrier layer 602, wherein a plurality of n-type doped barrier regions 320 are located above the deep n-type doped barrier layer 602 in the substrate 302, and wherein the deep n-type doped barrier layer 602 extends continuously between the plurality of n-type doped barrier regions 320.

[0228] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 1500 includes forming a plurality of deep n-doped barrier regions 802 in substrate 302, wherein a first n-doped barrier region 320 is located above a first deep n-doped barrier region 802 among the plurality of deep n-doped barrier regions 802, wherein a second n-doped barrier region 320 is located above a second deep n-doped barrier region 802 among the plurality of deep n-doped barrier regions 802, and wherein a fourth portion 804 of substrate 302 is located between the first deep n-doped barrier region 802 and the second deep n-doped barrier region 802.

[0229] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 1500 includes forming a plurality of deep n-doped barrier strips 902 in the fourth portion 804 of the substrate 302 between the first deep n-doped barrier region 802 and the second deep n-doped barrier region 802 .

[0230] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 1500 includes forming a first STI region 316 over a first portion 324 of the substrate 302, wherein the first STI region 316 is located between an n-type doped base 220 and a p-type doped collector 224; forming a second STI region 316 over a second portion 324 of the substrate 302, wherein the second STI region 316 is located between the p-type doped collector 224 and the p-type doped emitter 222; forming a first field plate structure 1004 on the first STI region 316; and forming a second field plate structure 1004 on the second STI region 316.

[0231] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the process 1500 includes forming an n-type doped barrier layer 1002 in the substrate 302, wherein the n-type doped base 220, the p-type doped emitter 222, and the p-type doped collector 224 are located above the n-type doped barrier layer 1002, and wherein the deep n-type doped barrier layer 602 extends continuously between the n-type doped base 220, the p-type doped emitter 222, and the p-type doped collector 224.

[0232] although Fig.15 Exemplary blocks of process 1500 are shown, but in some embodiments, Fig.15 The process 1500 may include additional blocks, fewer blocks, different blocks, or blocks configured in a different manner than those depicted. Additionally or alternatively, two or more blocks in the process 1500 may be performed in parallel.

[0233] In this way, a semiconductor device may include an ESD protection circuit and a high voltage ESD trigger circuit, the high voltage ESD trigger circuit being configured to trigger ESD protection for a high voltage circuit of the semiconductor device. The high voltage ESD trigger circuit may be implemented by one or more of the exemplary embodiments of the high voltage ESD trigger circuit described herein. The exemplary embodiments of the high voltage ESD trigger circuit described herein are capable of handling the high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of prematurely triggering ESD protection during normal operation of these high voltage circuits and / or prevents premature triggering of ESD protection, and enables the high voltage circuits to be protected from the effects of high voltage ESD events.

[0234] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a device circuit. The semiconductor device includes an ESD circuit coupled to the device circuit. The semiconductor device includes an ESD trigger circuit coupled to the ESD circuit and the device circuit, the ESD trigger circuit including: a substrate; a PNP ESD trigger device in the substrate and including: an n-type doped base; a p-type doped collector, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector; and a p-type doped emitter, wherein a second portion of the substrate is located between the p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter; and a plurality of n-type doped barrier regions in the substrate and including: a first n-type doped barrier region located below the first n-type doped well of the n-type doped base; and a second n-type doped barrier region located below the second n-type doped well of the p-type doped emitter, wherein a third portion of the substrate is located between the first n-type doped barrier region and the second n-type doped barrier region.

[0235] In some embodiments, the semiconductor device further comprises: a shallow trench isolation (STI) region located above a first portion of the substrate and between the n-type doped base and the p-type doped collector; and a resist protection oxide (RPO) structure located above a second portion of the substrate and between the p-type doped collector and the p-type doped emitter. In some embodiments, the semiconductor device further comprises: a first shallow trench isolation (STI) region located above the first portion of the substrate and between the n-type doped base and the p-type doped collector; and a second STI region located above the second portion of the substrate and between the p-type doped collector and the p-type doped emitter. In some embodiments, the semiconductor device further comprises: a deep n-type doped barrier layer located below a plurality of n-type doped barrier regions in the substrate, wherein the deep n-type doped barrier layer extends continuously between the plurality of n-type doped barrier regions. In some embodiments, the semiconductor device further comprises: a plurality of deep n-type doped barrier regions in the substrate and comprising: a first deep n-type doped barrier region below the first n-type doped barrier region; and a second deep n-type doped barrier region below the second n-type doped barrier region, wherein a fourth portion of the substrate is located between the first deep n-type doped barrier region and the second deep n-type doped barrier region. In some embodiments, the semiconductor device further comprises: a plurality of deep n-type doped barrier strips located in the fourth portion of the substrate and between the first deep n-type doped barrier region and the second deep n-type doped barrier region. In some embodiments, the semiconductor device further comprises: a plurality of n-type doped barrier strips located in the third portion of the substrate and between the first n-type doped barrier region and the second n-type doped barrier region.

[0236] As described in more detail above, some embodiments described herein provide a method. The method includes forming a plurality of shallow trench isolation (STI) regions in a substrate of a semiconductor device. The method includes: forming, for a PNP electrostatic discharge (ESD) trigger device of the semiconductor device: an n-type doped base located in the substrate and between a first STI region and a second STI region among a plurality of STI regions; a p-type doped collector located in the substrate and between a second STI region and a third STI region among a plurality of STI regions, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector; and a p-type doped emitter located in the substrate and between a third STI region and a fourth STI region among a plurality of STI regions, wherein a second portion of the substrate is located between a p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter. The method includes forming a first field plate structure on the second STI region. The method includes forming a second field plate structure on the third STI region.

[0237] In some embodiments, the method further comprises: before forming the plurality of STI regions, forming an n-type doped barrier layer in the substrate, wherein forming the n-type doped base, the p-type doped collector, and the p-type doped emitter comprises: forming the n-type doped base, the p-type doped collector, and the p-type doped emitter above the n-type doped barrier layer. In some embodiments, the method further comprises: before forming the plurality of STI regions, forming a plurality of n-type doped barrier regions in the substrate, wherein forming the n-type doped base comprises: forming the n-type doped base above a first n-type doped barrier region among the plurality of n-type doped barrier regions; and wherein forming the p-type doped emitter comprises: forming the p-type doped emitter above a second n-type doped barrier region among the plurality of n-type doped barrier regions. In some embodiments, the method further comprises: forming a plurality of n-type doped barrier strips in the substrate between the first n-type doped barrier region and the second n-type doped barrier region. In some embodiments, the method further comprises: before forming the plurality of n-type doped barrier regions, forming a deep n-type doped barrier layer in the substrate, wherein forming the plurality of n-type doped barrier regions comprises: forming the plurality of n-type doped barrier regions above the deep n-type doped barrier layer. In some embodiments, the method further comprises: before forming the plurality of n-type doped barrier regions, forming the plurality of deep n-type doped barrier regions in the substrate, wherein forming the plurality of n-type doped barrier regions comprises: forming a first n-type doped barrier region above a first deep n-type doped barrier region among the plurality of deep n-type doped barrier regions; and forming a second n-type doped barrier region above a second deep n-type doped barrier region among the plurality of deep n-type doped barrier regions.

[0238] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a device circuit. The semiconductor device includes an electrostatic discharge (ESD) circuit coupled to the device circuit. The semiconductor device includes an ESD trigger circuit coupled to the ESD circuit and the device circuit. The ESD trigger circuit includes: a substrate and a PNP ESD trigger device in the substrate. The PNP ESD trigger device includes: an n-type doped base, including a plurality of first fin-shaped structures; a p-type doped collector, including a plurality of second fin-shaped structures, wherein a first portion of the substrate is located between a first n-type doped well of the n-type doped base and a p-type doped well of the p-type doped collector; and a p-type doped emitter, including a plurality of third fin-shaped structures, wherein a second portion of the substrate is located between a p-type doped well of the p-type doped collector and a second n-type doped well of the p-type doped emitter.

[0239] In some embodiments, the semiconductor device further comprises: a plurality of n-type doped barrier regions located in the substrate and comprising: a first n-type doped barrier region located below the first n-type doped well of the n-type doped base; and a second n-type doped barrier region located below the second n-type doped well of the p-type doped emitter, wherein a third portion of the substrate is located between the first n-type doped barrier region and the second n-type doped barrier region. In some embodiments, the semiconductor device further comprises: a deep n-type doped barrier layer located below the plurality of n-type doped barrier regions in the substrate, wherein the deep n-type doped barrier layer extends continuously between the plurality of n-type doped barrier regions. In some embodiments, the semiconductor device further comprises: a plurality of deep n-type doped barrier regions located in the substrate and comprising: a first deep n-type doped barrier region located below the first n-type doped barrier region; and a second deep n-type doped barrier region located below the second n-type doped barrier region, wherein a fourth portion of the substrate is located between the first deep n-type doped barrier region and the second deep n-type doped barrier region. In some embodiments, the semiconductor device further comprises: a plurality of deep n-type doped barrier strips located in a fourth portion of the substrate between the first deep n-type doped barrier region and the second deep n-type doped barrier region. In some embodiments, the semiconductor device further comprises: a first shallow trench isolation (STI) region located above the first portion of the substrate and between the n-type doped base and the p-type doped collector; a second STI region located above the second portion of the substrate and between the p-type doped collector and the p-type doped emitter; a first field plate structure located on the first STI region; and a second field plate structure located on the second STI region. In some embodiments, the semiconductor device further comprises: an n-type doped barrier layer located in the substrate and below the n-type doped base, the p-type doped emitter, and the p-type doped collector, wherein the n-type doped barrier layer extends continuously between the n-type doped base, the p-type doped emitter, and the p-type doped collector.

[0240] As used herein, "satisfying a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0241] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: Device circuit; an electrostatic discharge circuit coupled to the device circuit; as well as An electrostatic discharge trigger circuit, coupled to the electrostatic discharge circuit and the device circuit, comprises: substrate; A PNP electrostatic discharge trigger device, in the substrate, comprises: n-type doped base; p-type doped collector, wherein the first portion of the substrate is located between the first n-type doped well of the n-type doped base and the p-type doped well of the p-type doped collector; and p-type doped emitter, wherein the second portion of the substrate is located between the p-type doped well of the p-type doped collector and the second n-type doped well of the p-type doped emitter; and A plurality of n-type doped barrier regions, in the substrate, comprising: a first n-type doped barrier region located below the first n-type doped well of the n-type doped base; and A second n-type doped barrier region is located below the second n-type doped well of the p-type doped emitter, The third portion of the substrate is located between the first n-type doped barrier region and the second n-type doped barrier region.

2. The semiconductor device according to claim 1, wherein: Also includes: a shallow trench isolation region located above the first portion of the substrate and between the n-type doped base and the p-type doped collector; as well as A resist protects an oxide structure over the second portion of the substrate and between the p-type doped collector and the p-type doped emitter.

3. The semiconductor device according to claim 1, wherein: Also includes: a first shallow trench isolation region located above the first portion of the substrate and between the n-type doped base and the p-type doped collector; as well as A second shallow trench isolation region is located above the second portion of the substrate and between the p-type doped collector and the p-type doped emitter.

4. The semiconductor device according to claim 1, wherein: Also includes: a deep n-type doped barrier layer located below the plurality of n-type doped barrier regions in the substrate, The deep n-type doped barrier layer extends continuously between the plurality of n-type doped barrier regions.

5. The semiconductor device according to claim 1, wherein: Also includes: A plurality of deep n-type doped barrier regions, in the substrate, comprising: a first deep n-type doped barrier region, below the first n-type doped barrier region; as well as a second deep n-type doped barrier region, below the second n-type doped barrier region, The fourth portion of the substrate is located between the first deep n-type doped barrier region and the second deep n-type doped barrier region.

6. The semiconductor device according to claim 5, wherein: Also includes: A plurality of deep n-type doped barrier strips are located in the fourth portion of the substrate and between the first deep n-type doped barrier region and the second deep n-type doped barrier region.

7. The semiconductor device according to claim 1, wherein: Also includes: A plurality of n-type doped barrier strips are located in the third portion of the substrate and between the first n-type doped barrier region and the second n-type doped barrier region.

8. A semiconductor device, characterized in that: include: Device circuit; an electrostatic discharge circuit coupled to the device circuit; as well as An electrostatic discharge trigger circuit, coupled to the electrostatic discharge circuit and the device circuit, comprises: substrate; and A PNP electrostatic discharge trigger device, in the substrate, comprises: An n-type doped base including a plurality of first fin-shaped structures; A p-type doped collector includes a plurality of second fin-shaped structures, wherein the first portion of the substrate is located between the first n-type doped well of the n-type doped base and the p-type doped well of the p-type doped collector; and A p-type doped emitter includes a plurality of third fin-shaped structures, The second portion of the substrate is located between the p-type doped well of the p-type doped collector and the second n-type doped well of the p-type doped emitter.

9. The semiconductor device according to claim 8, wherein: Also includes: a first shallow trench isolation region located above the first portion of the substrate and between the n-type doped base and the p-type doped collector; a second shallow trench isolation region located above the second portion of the substrate and between the p-type doped collector and the p-type doped emitter; A first field plate structure, located on the first shallow trench isolation region; as well as The second field plate structure is located on the second shallow trench isolation region.

10. The semiconductor device according to claim 9, wherein: Also includes: An n-type doped barrier layer is located in the substrate and below the n-type doped base, the p-type doped emitter and the p-type doped collector, The n-type doped barrier layer continuously extends between the n-type doped base, the p-type doped emitter and the p-type doped collector.

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