Display panel and display device

Abstract

The utility model discloses a display panel and a display device.The display panel comprises an array substrate, an opposite substrate and spacing columns, the array substrate comprises a first substrate and a thin film transistor arranged on the side, facing the opposite substrate, of the first substrate, and the opposite substrate comprises a second substrate and a black matrix arranged on the side, facing the array substrate, of the second substrate; the orthographic projection of the thin film transistor on the first substrate is located in the orthographic projection range of the black matrix on the first substrate, one end of the spacing column is arranged on the opposite substrate and corresponds to the position of the black matrix, and the other end of the spacing column is supported on the array substrate; wherein a retaining wall is formed on the side, facing the opposite substrate, of the array substrate, a groove is formed in the position between the retaining wall and the thin film transistor, the notch size of the groove is at least larger than the size of the end, connected with the array substrate, of the spacing column, and the orthographic projection, on the substrate, of the groove is located in the orthographic projection range, on the first substrate, of the black matrix.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of science and technology, notebooks have become an indispensable product for people's office and entertainment due to their portability and powerful functions. In order to prevent the display screen from displaying abnormal images due to collisions during transportation / travel / use, the display screen needs to be subjected to compression and vibration tests before leaving the factory. The test found that when the display screen is squeezed, the support columns inside the display screen will scratch the alignment layer due to displacement; and the scratched alignment layer will produce debris. When the display screen is vibrated, the debris will move outside the area covered by the black matrix under the vibration, causing the display screen to display abnormal images. Utility Model Content

[0003] The embodiments of the present application provide a display panel and a display device, which use grooves to limit the spacing columns and limit the movement of debris when the spacing columns scratch the alignment layer to generate debris, thereby preventing the display panel from having poor display after being squeezed and vibrated.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising an array substrate and an opposing substrate arranged opposite to each other, and a spacer, wherein the array substrate comprises a first substrate, and a thin film transistor arranged on a side of the first substrate facing the opposing substrate; the opposing substrate comprises a second substrate, and a black matrix arranged on a side of the second substrate facing the array substrate, an orthographic projection of the thin film transistor on the first substrate is located within a range of an orthographic projection of the black matrix on the first substrate, one end of the spacer is arranged on the opposing substrate and corresponds to a position of the black matrix, and the other end of the spacer is supported on the array substrate;

[0005] A retaining wall is formed on the side of the array substrate facing the opposing substrate, and the retaining wall is located on the side of the thin film transistor in the first direction. A groove is formed on the surface of the array substrate facing the opposing substrate at a position corresponding to the retaining wall and the thin film transistor, and the notch size of the groove is at least larger than the end size of the spacer column connected to the array substrate, and the orthographic projection of the groove on the substrate is within the range of the orthographic projection of the black matrix on the first substrate.

[0006] In one embodiment, the array substrate further includes:

[0007] an interlayer insulating layer, the interlayer insulating layer being arranged on a side of the first substrate facing the counter substrate, the interlayer insulating layer covering the thin film transistor;

[0008] a first alignment layer, the first alignment layer being disposed on a side of the interlayer insulating layer facing the counter substrate; and

[0009] A spacer block, the spacer block is arranged between the interlayer insulating layer and the first alignment layer, or, is arranged between the interlayer insulating layer and the first substrate, the spacer block is located on one side of the thin film transistor in the first direction, so as to form the groove on the surface of the first alignment layer facing the opposite substrate;

[0010] The retaining wall includes the spacer block, or the retaining wall at least includes the spacer block and a portion of the interlayer insulating layer located on the spacer block.

[0011] In one embodiment, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode, the gate electrode is arranged on a side of the first substrate facing the opposite substrate, the gate insulating layer is arranged on a side of the first substrate facing the opposite substrate and covers the gate electrode, the active layer is arranged on a side of the gate insulating layer facing the opposite substrate, the source electrode and the drain electrode are arranged on a side of the active layer facing the opposite substrate and are arranged corresponding to the conductor portion of the active layer;

[0012] The spacer block and the gate are located in the same film layer, the spacer block is located on one side of the gate in the first direction, and in the thickness direction of the display panel, the thickness of the spacer block is greater than the thickness of the gate;

[0013] The gate insulating layer covers the spacer block, and the interlayer insulating layer is arranged on a side of the gate insulating layer facing the counter substrate and covers the active layer, the source electrode and the drain electrode;

[0014] The blocking wall includes the spacer block, and a portion of the gate insulating layer and a portion of the interlayer insulating layer located on the spacer block.

[0015] In one embodiment, the array substrate further comprises a metal dam, the metal dam is provided in the same layer as the gate, and the metal dam is located on one side of the gate in the first direction, and in the thickness direction of the display panel, the thickness of the metal dam is greater than the thickness of the gate;

[0016] Wherein, the spacer block includes the metal dam.

[0017] In one embodiment, the spacer block is disposed between the interlayer insulating layer and the first alignment layer, and the spacer block and the interlayer insulating layer are made of the same material;

[0018] Wherein, the retaining wall includes the spacer block.

[0019] In one embodiment, the black matrix forms a first projection on the first substrate;

[0020] The thin film transistor forms a second projection on the first substrate;

[0021] The spacer block forms a third projection on the first substrate, and an edge of the third projection close to the second projection coincides with an edge of the first projection.

[0022] In one embodiment, the array substrate further comprises a first alignment layer, the first alignment layer is located on a side of the thin film transistor facing the opposite substrate, the first alignment layer covers the retaining wall and the thin film transistor, and the groove is correspondingly formed on a side of the first alignment layer facing the opposite substrate;

[0023] The array substrate further includes an anti-slip structure, which is located on a side of the first alignment layer facing the counter substrate and is at least arranged on a bottom wall of the groove.

[0024] In one embodiment, the anti-slip structure includes an anti-slip film layer, which is located on the side of the first alignment layer facing the opposing substrate and covers the bottom wall and side walls of the groove, and the friction coefficient of the anti-slip film layer is greater than the friction coefficient of the first alignment layer.

[0025] In one embodiment, the anti-slip structure includes a plurality of anti-slip protrusions arranged in a pattern, and the plurality of anti-slip protrusions are located on a side of the first alignment layer facing the counter substrate and distributed on a bottom wall and side walls of the groove.

[0026] In a second aspect, an embodiment of the present application further provides a display device, comprising the above-mentioned display panel.

[0027] Beneficial effect: In the display panel provided by the present application, the orthographic projection of the thin film transistor of the array substrate on the first substrate is located within the orthographic projection range of the black matrix of the opposing substrate on the first substrate; one end of the spacer is arranged on the opposing substrate and corresponds to the position of the black matrix, and the other end of the spacer is supported on the array substrate; a retaining wall is formed on the side of the array substrate facing the opposing substrate, and the retaining wall is located on the side of the thin film transistor in the first direction; on the surface of the side of the array substrate facing the opposing substrate, a groove is formed at a position corresponding to the retaining wall and the thin film transistor, and when the display panel is squeezed and the spacer is displaced, the spacer moves into the groove and is limited by the groove, so that the first alignment layer on the array substrate cannot be scratched; and because the orthographic projection of the groove on the substrate is located within the orthographic projection range of the black matrix on the first substrate, even if the spacer slides in the first alignment layer to generate debris, the debris will be confined in the groove, thereby being confined within the area covered by the black matrix, so that the display panel will not have a starry sky display screen abnormality. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0029] Figure 1 A first film layer diagram of a display panel provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of the displacement of the spacer column provided in an embodiment of the present application;

[0031] Figure 3 A second film layer diagram of a display panel provided in an embodiment of the present application;

[0032] Figure 4 A third film layer diagram of a display panel provided in an embodiment of the present application;

[0033] Figure 5 A fourth film layer diagram of a display panel provided in an embodiment of the present application;

[0034] Figure 6a and Figure 6b A schematic diagram of the positions of the spacer blocks and the black matrix provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0036] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and cannot be understood as limiting the present application. In addition, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature merely means that the first feature is higher in level than the second feature or that the first feature is lower in level than the second feature, and does not indicate a direct connection relationship.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only, and the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0038] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "connect" and "connect" should be understood in a broad sense without specifically limiting the connection method. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0039] The disclosure below provides many different embodiments to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0040] The embodiments of the present application provide an array substrate and a display panel. The display panel may be a display panel of a mobile phone, a computer, a tablet, a display screen, etc., and is not limited here.

[0041] In a first aspect, an embodiment of the present application provides a display panel 100. The display panel 100 includes an array substrate 1 and an opposing substrate 2 that are arranged opposite to each other, and a spacer 3 supported between the array substrate 1 and the opposing substrate 2.

[0042] See also Figure 1 and Figure 2The array substrate 1 comprises a first substrate 11, and a thin film transistor 12 disposed on a side of the first substrate 11 facing the counter substrate 2; the counter substrate 2 comprises a second substrate 21, and a black matrix 22 disposed on a side of the second substrate 21 facing the array substrate 1, the orthographic projection of the thin film transistor 12 on the first substrate 11 is located within the orthographic projection range of the black matrix 22 on the first substrate 11, one end of the spacer 3 is disposed on the counter substrate 2 and corresponds to the position of the black matrix 22, and the other end of the spacer 3 is supported on the array substrate 1. A column substrate 1; wherein a retaining wall 13 is formed on the side of the array substrate 1 facing the opposing substrate 2, and the retaining wall 13 is located on the side of the thin film transistor 12 in the first direction F1. On the surface of the side of the array substrate 1 facing the opposing substrate 2, a groove 14 is formed at a position corresponding to the position between the retaining wall 13 and the thin film transistor 12, and the notch size of the groove 14 is at least larger than the end size of the spacer column 3 connected to the array substrate 1, and the orthographic projection of the groove 14 on the substrate is located within the orthographic projection range of the black matrix 22 on the first substrate 11.

[0043] In the display panel 100 provided in the present application, the orthographic projection of the thin film transistor 12 of the array substrate 1 on the first substrate 11 is located within the orthographic projection range of the black matrix 22 of the opposing substrate 2 on the first substrate 11; one end of the spacer 3 is arranged on the opposing substrate 2 and corresponds to the position of the black matrix 22, and the other end of the spacer 3 is supported on the array substrate 1; a retaining wall 13 is formed on the side of the array substrate 1 facing the opposing substrate 2, and the retaining wall 13 is located on the side of the thin film transistor 12 in the first direction F1, that is, the orthographic projection of the retaining wall 13 on the first substrate 11 is staggered with the orthographic projection of the thin film transistor 12 on the first substrate 11, and the array substrate 1 faces the opposing substrate 2. A groove 14 is formed on one side surface of the substrate 2 at a position corresponding to the retaining wall 13 and the thin film transistor 12. When the display panel 100 is squeezed and the spacer column 3 is displaced, the spacer column 3 moves into the groove 14 and is limited by the groove 14, so that the first alignment layer 16 on the array substrate 1 cannot be scratched; and because the orthographic projection of the groove 14 on the substrate is within the orthographic projection range of the black matrix 22 on the first substrate 11, even if the spacer column 3 slides on the first alignment layer 16 to produce debris, the debris will be confined in the groove 14, and thus confined to the area covered by the black matrix 22, so that the display panel 100 will not have an abnormal display screen full of stars.

[0044] The present application does not impose any specific restrictions on the shape of the spacer column 3. The spacer column 3 may be in any of the following shapes: cylindrical, truncated cone, prism, etc. Figure 1 The shape of the spacer column 3 is set to be a truncated cone, that is, the cross-sectional shape of the spacer column 3 is an inverted trapezoid, and the diameter of the end of the spacer column 3 connected to the opposing substrate 2 is larger than the diameter of the end of the spacer column 3 connected to the array substrate 1.

[0045] Thus, it can be understood that the present application does not impose any specific restrictions on the size of the groove 14. The notch size of the groove 14 is larger than the end size of the spacer column 3 connected to the array substrate 1, so that the end of the spacer column 3 can be accommodated when the spacer column 3 is displaced, thereby limiting the spacer column 3. In some embodiments, the groove 14 can also be made larger, for example, the notch size of the groove 14 is larger than the end size of the spacer column 3 connected to the opposing substrate 2; or, in some other embodiments, the groove 14 is arranged to expand outward in the direction from its bottom wall to its notch, and the side wall of the groove 14 is adapted to the shape of the spacer column 3.

[0046] In some embodiments, please refer to Figure 1 The opposing substrate 2 is a color film substrate, and the opposing substrate 2 also includes a color filter layer 23, a protective layer 24 and a second alignment layer 25. The color filter layer 23 is arranged on the side of the second substrate 21 facing the array substrate 1, and the multiple color blocks 231 of the color filter layer 23 are distributed in the black matrix 22. The protective layer 24 is arranged on the side of the color filter layer 23 facing the array substrate 1 and covers the color filter layer 23 and the black matrix 22. One end of the spacer 3 can be directly formed on the surface of the side of the protective layer 24 facing the array substrate 1, and the other end of the spacer 3 extends toward the array substrate 1 and is connected to the array substrate 1. The second alignment layer 25 is arranged on the side of the protective layer 24 facing the array substrate 1.

[0047] It can be known that alignment grooves are formed on both the first alignment layer 16 and the second alignment layer 25 , and the alignment grooves are used to make the liquid crystal molecules in the liquid crystal layer have a pre-tilt angle. One end of the spacer 3 connected to the array substrate 1 is in direct contact with the first alignment layer 16 .

[0048] The present application does not impose any specific restrictions on the location and structure of the retaining wall 13. The array substrate 1 further includes an interlayer insulating layer 15, a first alignment layer 16 and a spacer block 131; the interlayer insulating layer 15 is disposed on the side of the first substrate 11 facing the opposing substrate 2, and the interlayer insulating layer 15 covers the thin film transistor 12; the first alignment layer 16 is disposed on the side of the interlayer insulating layer 15 facing the opposing substrate 2; the spacer block 131 is disposed between the interlayer insulating layer 15 and the first alignment layer 16, or, between the interlayer insulating layer 15 and the first substrate 11, and the spacer block 131 is located on the side of the thin film transistor 12 in the first direction F1, so as to form the groove 14 on the surface of the first alignment layer 16 facing the opposing substrate 2; wherein the retaining wall 13 includes the spacer block 131, or the retaining wall 13 at least includes the spacer block 131 and a portion of the interlayer insulating layer 15 located on the spacer block 131.

[0049] That is, by arranging the spacer block 131 on either side of the interlayer insulating layer 15, the terrain of the position is raised, and the spacer block 131 is located on the side of the thin film transistor 12 in the first direction F1, that is, the orthographic projection of the spacer block 131 on the first substrate 11 is staggered with the orthographic projection of the thin film transistor 12 on the first substrate 11; the first alignment layer 16 is arranged on the side of the interlayer insulating layer 15 facing the opposite substrate 2, and the side of the first alignment layer 16 facing the opposite substrate 2 will form the groove 14 as the film layer settles. When the spacer block 131 is arranged on the side of the interlayer insulating layer 15 facing the opposite substrate 2, the retaining wall 13 includes the spacer block 131; when the spacer block 131 is arranged between the interlayer insulating layer 15 and the first substrate 11, the retaining wall 13 at least includes the spacer block 131 and a portion of the interlayer insulating layer 15 located on the spacer block 131.

[0050] It can be known that in the present application, the display panel 100 is set as a liquid crystal display panel 100, and the display panel 100 also includes a liquid crystal layer (not shown in the figure) arranged between the array substrate 1 and the opposing substrate 2. The present application does not make any specific restrictions on the display panel 100. The display panel 100 can be a FFS (full name in English: Fringe Field Switching, Chinese abbreviation: fringe field switch) liquid crystal display panel 100, or a HFS (full name in English: High transmission Fringe Field Switching, Chinese abbreviation: high transmission fringe field switching) liquid crystal display panel 100, or other existing types of liquid crystal display panels 100, which are not limited here.

[0051] The following is an example of an HFS liquid crystal display panel 100. The array substrate 1 includes a first metal layer, a gate insulating layer 122, an active layer 123, and a second metal layer. The first metal layer is arranged on the side of the first substrate 11 facing the opposing substrate 2, and the first metal layer includes a gate 121. The gate insulating layer 122 is arranged on the side of the first substrate 11 facing the opposing substrate 2 and covers the gate 121. The active layer 123 is arranged on the side of the gate insulating layer 122 facing the opposing substrate 2 and corresponds to the gate 121. 1; the second metal layer is located on the side of the active layer 123 facing the opposing substrate 2, and the second metal layer includes a source 124 and a drain 125 overlapped with the conductor part of the active layer 123; the interlayer insulating layer 15 is arranged on the side of the gate insulating layer 122 facing the opposing substrate 2, and covers the active layer 123, the source 124 and the drain 125; the thin film transistor 12 includes the gate 121, the gate insulating layer 122, the active layer 123, the source 124 and the drain 125.

[0052] The array substrate 1 also includes a pixel electrode 18 and a common electrode 19; the pixel electrode 18 is arranged on the side of the gate insulating layer 122 facing the opposing substrate 2, and the pixel electrode 18 is overlapped with the drain 125; the common electrode 19 is arranged on the side of the interlayer insulating layer 15 facing the opposing substrate 2 and is electrically connected to the first metal layer via a via; a storage capacitor is formed between the pixel electrode 18 and the common electrode 19.

[0053] Please refer again Figure 1 In the first embodiment of the present application, the spacer block 131 and the gate 121 are located in the same film layer, and the spacer block 131 is located on one side of the gate 121 in the first direction F1, that is, the orthographic projection of the spacer block 131 on the first substrate 11 and the orthographic projection of the gate 121 on the first substrate 11 are offset, and in the thickness direction of the display panel 100, the thickness of the spacer block 131 is greater than the thickness of the gate 121; wherein the gate insulating layer 122 covers the spacer block 131, and the interlayer insulating layer 15 is arranged on the side of the gate insulating layer 122 facing the opposing substrate 2 and covers the active layer 123, the source 124 and the drain 125; the retaining wall 13 includes the spacer block 131, and a portion of the gate insulating layer 122 and a portion of the interlayer insulating layer 15 located on the spacer block 131.

[0054] In the first embodiment, a spacer block 131 is provided on the first substrate 11, and the thickness of the spacer block 131 is greater than the thickness of the gate 121, so that a terrain difference is formed on the first substrate 11. When a plurality of film layers are subsequently deposited on the first substrate 11, the natural sedimentation of the plurality of film layers forms the groove 14 on the side of the first alignment layer 16 facing the opposing substrate 2. When the display panel 100 is squeezed and the spacer column 3 is displaced, the spacer column 3 moves into the groove 14 and is limited by the groove 14, so that the first alignment layer 16 on the array substrate 1 cannot be scratched. Moreover, since the orthographic projection of the groove 14 on the substrate is within the orthographic projection range of the black matrix 22 on the first substrate 11, even if the spacer column 3 slides on the first alignment layer 16 to generate debris, the debris will be confined in the groove 14, and thus confined to the area covered by the black matrix 22, so that the display panel 100 will not have an abnormal display screen full of stars.

[0055] It should be noted that the present application does not limit the material of the spacer block 131 , and the material of the spacer block 131 may be an inorganic material or a metal material.

[0056] In one embodiment, the array substrate 1 also includes a metal dam 132, and the metal dam 132 is arranged in the same layer as the gate 121, and the metal dam 132 is located on one side of the gate 121 in the first direction F1, that is, the orthographic projection of the metal dam 132 on the first substrate 11 and the orthographic projection of the gate 121 on the first substrate 11 are offset, and in the thickness direction of the display panel 100, the thickness of the metal dam 132 is greater than the thickness of the gate 121; wherein the spacer block 131 includes the metal dam 132.

[0057] That is, a first metal layer of the entire surface can be provided on the side of the first substrate 11 facing the counter substrate 2; a photoresist layer is formed on the first metal layer, and the photoresist layer is exposed and developed using a halftone mask as a mask, so as to pattern the photoresist layer, wherein the photoresist layer includes a first photoresist pattern and a second photoresist pattern, and the thickness of the first photoresist pattern is less than the thickness of the second photoresist pattern; the first metal layer is etched, and the first metal layer not covered by the photoresist pattern is etched away, and the first metal layer covered by the first photoresist pattern is partially etched, so as to form the gate 121 with a smaller thickness, and the first metal layer covered by the second photoresist pattern forms the spacer block 131 with a larger thickness. In this way, compared with forming the spacer block 131 using other materials, this method can simplify the process of forming the spacer block 131; and the electrical property of the spacer block 131 is an open circuit, and the spacer block 131 is neither electrically connected to the gate 121 in the first metal layer nor connected to any other electrical signal.

[0058] See also Figure 3 In the second embodiment of the present application, the spacer block 131 is arranged between the interlayer insulating layer 15 and the first alignment layer 16, and the spacer block 131 is made of the same material as the interlayer insulating layer 15; wherein the retaining wall 13 includes the spacer block 131.

[0059] The difference from the first embodiment is that, in the second embodiment, the spacer block 131 is located on the side of the interlayer insulating layer 15 facing the opposing substrate 2, so as to form a potential difference on the interlayer insulating layer 15, and the first alignment layer 16 is arranged on the interlayer insulating layer 15. The first alignment layer 16 will form the groove 14 on the side facing the opposing substrate 2 as the potential difference changes. When the display panel 100 is squeezed and the spacer column 3 is displaced, the spacer column 3 moves into the groove 14 and is limited by the groove 14, so that the first alignment layer 16 on the array substrate 1 cannot be scratched; and because the orthographic projection of the groove 14 on the substrate is located within the orthographic projection range of the black matrix 22 on the first substrate 11, even if the spacer column 3 slides on the first alignment layer 16 to generate debris, the debris will be confined in the groove 14, and thus confined to the area covered by the black matrix 22, so that the display panel 100 will not have a starry sky display abnormality.

[0060] Understandably, please refer to Figure 2In the actual manufacturing process, the spacer block 131 is located on the side of the common electrode 19 layer facing the opposing substrate 2 and is directly arranged on the common electrode 19. By arranging the spacer block 131 of inorganic material on the common electrode 19, not only can the terrain of the position be raised to facilitate the formation of the groove 14, but also no interference with the common electrode 19 is generated.

[0061] The present application does not impose any specific restrictions on the position of the spacer block 131 relative to the black matrix 22 , as long as the orthographic projection of the groove 14 formed by the spacer block 131 on the substrate is within the orthographic projection range of the black matrix 22 on the first substrate 11 .

[0062] In one embodiment, see Figure 6a , a third projection C formed by the spacer block 131 on the first substrate 11 partially overlaps with a first projection A formed by the black matrix 22 on the first substrate 11 .

[0063] It is understandable that when the gap between the spacer block 131 and the thin film transistor 12 is small, the gap will be filled with the stacking of the film layers, so that the groove 14 cannot be formed or the size of the formed groove 14 is too small to accommodate the spacer column 3; when the gap between the spacer block 131 and the thin film transistor 12 is large, although the formed groove 14 can limit the spacer column 3, once the groove 14 exceeds the coverage area of ​​the black matrix 22, there is still a risk of abnormal display. In one embodiment of the present application, please refer to Figure 6b The black matrix 22 forms a first projection A on the first substrate 11; the thin film transistor 12 forms a second projection B on the first substrate 11; the spacer block 131 forms a third projection C on the first substrate 11, and the edge of the third projection C close to the second projection B coincides with the edge of the first projection A.

[0064] That is to say, in this embodiment, the inner edge of the orthographic projection of the spacer block 131 on the first substrate 11 coincides with the outer edge of the orthographic projection of the black matrix 22 on the first substrate 11, which not only maximizes the size of the groove 14 but also ensures that the groove 14 is located within the area covered by the black matrix 22. Even if the spacer column 3 slips on the first alignment layer 16 to produce debris, the debris will be confined to the area covered by the black matrix 22, thereby preventing the display panel 100 from displaying an abnormal screen full of stars.

[0065] It can be known that when the size of the groove 14 is larger than the size of the spacer column 3, as the display panel 100 is squeezed, the spacer column 3 will also slide in the groove 14. In order to avoid the spacer column 3 from sliding in the groove 14 and generating more debris, in some embodiments of the present application, the array substrate 1 also includes a first alignment layer 16, and the first alignment layer 16 is located on the side of the thin film transistor 12 facing the opposing substrate 2. The first alignment layer 16 covers the retaining wall 13 and the thin film transistor 12, and the groove 14 is correspondingly formed on the side of the first alignment layer 16 facing the opposing substrate 2; the array substrate 1 also includes an anti-slip structure 17, and the anti-slip structure 17 is located on the side of the first alignment layer 16 facing the opposing substrate 2, and is at least arranged on the bottom wall of the groove 14.

[0066] By providing the anti-slip structure 17 at least on the bottom wall of the groove 14, the friction force of the inner wall of the groove 14 can be increased. When the spacer column 3 slides into the groove 14, it will not slide in the groove 14 even if it is squeezed, thereby reducing scratches on the alignment layer and the generation of debris.

[0067] The present application does not limit the location of the anti-slip structure 17 . The anti-slip structure 17 may be disposed only on the bottom wall of the groove 14 , or on the bottom wall and side walls of the groove 14 .

[0068] See also Figure 4 In the third embodiment of the present application, the anti-slip structure 17 includes an anti-slip film layer 171, which is located on the side of the first alignment layer 16 facing the opposing substrate 2 and covers the bottom wall and side wall of the groove 14, and the friction coefficient of the anti-slip film layer 171 is greater than the friction coefficient of the first alignment layer 16.

[0069] In the third embodiment of the present application, by coating the bottom wall and side wall of the groove 14 with the anti-slip film layer 171, the friction coefficient of the inner wall of the groove 14 is made greater than the friction coefficient of the first alignment layer 16. Even if the display panel 100 is squeezed, the spacer column 3 is not easy to slide in the groove 14, which can not only prevent the first alignment layer 16 from being scratched by the spacer column 3, but also prevent the generation of more debris.

[0070] See also Figure 5 In the fourth embodiment of the present application, the anti-slip structure 17 includes a plurality of anti-slip protrusions 172 arranged in a pattern, and the plurality of anti-slip protrusions 172 are located on the side of the first alignment layer 16 facing the opposing substrate 2 and are distributed on the bottom wall and side walls of the groove 14.

[0071] The difference from the third embodiment is that in the fourth embodiment, the first alignment layer 16 can be patterned to form a plurality of anti-slip protrusions 172 on the bottom wall and side walls of the groove 14, thereby increasing the friction coefficient of the bottom wall and side walls of the groove 14; even if the display panel 100 is squeezed, the spacer column 3 is not easy to slide in the groove 14, which can not only prevent the first alignment layer 16 from being scratched by the spacer column 3, but also prevent the generation of more debris.

[0072] In a second aspect, an embodiment of the present application further provides a display device. The display device includes a display panel 100. It should be noted that the display panel 100 is configured as the above-mentioned display panel 100, that is, the display panel 100 includes all the technical features of the above-mentioned display panel 100, and the display device includes all the embodiments of the above-mentioned display panel 100, and also has all the technical effects of the above-mentioned embodiments, which will not be described one by one here.

[0073] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The invention comprises an array substrate and an opposing substrate which are arranged opposite to each other, and a spacer, wherein the array substrate comprises a first substrate, and a thin film transistor which is arranged on a side of the first substrate facing the opposing substrate; the opposing substrate comprises a second substrate, and a black matrix which is arranged on a side of the second substrate facing the array substrate; the orthographic projection of the thin film transistor on the first substrate is located within the orthographic projection range of the black matrix on the first substrate; one end of the spacer is arranged on the opposing substrate and corresponds to the position of the black matrix, and the other end of the spacer is supported on the array substrate; A retaining wall is formed on the side of the array substrate facing the opposing substrate, and the retaining wall is located on the side of the thin film transistor in the first direction. A groove is formed on the surface of the array substrate facing the opposing substrate at a position corresponding to the retaining wall and the thin film transistor, and the notch size of the groove is at least larger than the end size of the spacer column connected to the array substrate, and the orthographic projection of the groove on the substrate is within the range of the orthographic projection of the black matrix on the first substrate.

2. The display panel according to claim 1, wherein: The array substrate further includes: an interlayer insulating layer, the interlayer insulating layer being arranged on a side of the first substrate facing the counter substrate, the interlayer insulating layer covering the thin film transistor; a first alignment layer, the first alignment layer being disposed on a side of the interlayer insulating layer facing the counter substrate; and A spacer block, the spacer block is arranged between the interlayer insulating layer and the first alignment layer, or, is arranged between the interlayer insulating layer and the first substrate, the spacer block is located on one side of the thin film transistor in the first direction, so as to form the groove on the surface of the first alignment layer facing the opposite substrate; The retaining wall includes the spacer block, or the retaining wall at least includes the spacer block and a portion of the interlayer insulating layer located on the spacer block.

3. The display panel according to claim 2, wherein: The thin film transistor comprises a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein the gate electrode is arranged on a side of the first substrate facing the opposite substrate, the gate insulating layer is arranged on a side of the first substrate facing the opposite substrate and covers the gate electrode, the active layer is arranged on a side of the gate insulating layer facing the opposite substrate, the source electrode and the drain electrode are arranged on a side of the active layer facing the opposite substrate and are arranged corresponding to the conductor portion of the active layer; The spacer block and the gate are located in the same film layer, the spacer block is located on one side of the gate in the first direction, and in the thickness direction of the display panel, the thickness of the spacer block is greater than the thickness of the gate; The gate insulating layer covers the spacer block, and the interlayer insulating layer is arranged on a side of the gate insulating layer facing the counter substrate and covers the active layer, the source electrode and the drain electrode; The blocking wall includes the spacer block, and a portion of the gate insulating layer and a portion of the interlayer insulating layer located on the spacer block.

4. The display panel according to claim 3, wherein: The array substrate further comprises a metal dam, which is provided in the same layer as the gate and is located on one side of the gate in the first direction, and in the thickness direction of the display panel, the thickness of the metal dam is greater than the thickness of the gate; Wherein, the spacer block includes the metal dam.

5. The display panel according to claim 2, wherein: The spacer block is disposed between the interlayer insulating layer and the first alignment layer, and the spacer block is made of the same material as the interlayer insulating layer; Wherein, the retaining wall includes the spacer block.

6. The display panel according to claim 2, wherein: The black matrix forms a first projection on the first substrate; The thin film transistor forms a second projection on the first substrate; The spacer block forms a third projection on the first substrate, and an edge of the third projection close to the second projection coincides with an edge of the first projection.

7. The display panel according to claim 1, wherein: The array substrate further comprises a first alignment layer, the first alignment layer is located on a side of the thin film transistor facing the opposite substrate, the first alignment layer covers the retaining wall and the thin film transistor, and the groove is correspondingly formed on a side of the first alignment layer facing the opposite substrate; The array substrate further includes an anti-slip structure, which is located on a side of the first alignment layer facing the opposite substrate and is at least arranged on a bottom wall of the groove.

8. The display panel according to claim 7, wherein: The anti-slip structure includes an anti-slip film layer, which is located on the side of the first alignment layer facing the opposing substrate and covers the bottom wall and side walls of the groove. The friction coefficient of the anti-slip film layer is greater than the friction coefficient of the first alignment layer.

9. The display panel according to claim 7, wherein: The anti-skid structure includes a plurality of anti-skid protrusions arranged in a pattern, the plurality of anti-skid protrusions are located on a side of the first alignment layer facing the counter substrate and are distributed on a bottom wall and a side wall of the groove.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-9.

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