Chip packaging shell, chip packaging structure and power electronic device
By mixing the configuration of whole wafer chips and discrete chips in the chip package housing, the problem of difficulty in achieving faster switching frequency, lower driving power and lower chip loss in the prior art is solved, and a more efficient power electronic device packaging effect is achieved.
Patent Information
- Application Number
- CN202421486144.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2034-06-27
AI Technical Summary
When the existing chip crimping structure achieves high voltage and high current, it is difficult to simultaneously have faster switching frequency, lower driving power and lower chip loss.
A chip package housing is designed, which contains at least two unit package spaces inside for a hybrid configuration of a whole wafer chip and a discrete chip. A more efficient power electronics package is achieved by combining the advantages of two types of chips in a single package housing.
It realizes faster switching frequency, higher voltage and current levels and lower chip losses for power semiconductor devices, while meeting the requirements of bidirectional flow, bidirectional pressure bearing and bidirectional switching under special operating conditions.
Smart Images
Figure CN222867666U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging shell, a chip packaging structure and a power electronic device. Background Art
[0002] High-voltage and large-capacity power electronic devices have been widely used in industrial variable-frequency speed regulation, wind power grid connection, rail transit, DC transmission and other fields. In order to achieve high voltage and high current, the crimping type power electronic device packaging structure has gradually become the mainstream packaging form of existing high-voltage and large-capacity power electronic devices due to its higher power density, double-sided heat dissipation and failure short circuit. The existing crimping type packaging structure of power electronic devices is mainly divided into two types: discrete small chip parallel crimping structure and whole wafer chip crimping structure.
[0003] Representative power electronic devices with whole wafer chip pressing structure include diodes, thyristors, gate turn-off thyristors (GTO), gate commutated thyristors (GCT), emitter turn-off thyristors (ETO), etc. Since this type of power electronic device has lower processing difficulty, it is usually pressed in the form of whole wafer. The main advantages of this type of whole wafer chip are larger current capacity and lower chip loss.
[0004] Representative power electronic devices of the discrete small chip parallel compression structure include metal oxide field effect transistors (MOSFET), insulated gate bipolar transistors (IGBT), ion implantation enhancement transistors (IEGT), etc. Due to higher process requirements, discrete small chips are usually obtained by whole wafer cutting, and then they are compressed in parallel after chip consistency screening. The main advantages of this type of discrete small chip are faster switching frequency and lower driving power.
[0005] Although the above two types of chip pressing structures have their own advantages, the discrete small chip parallel pressing structure will have a large chip loss, and the whole wafer chip pressing structure cannot achieve a faster switching frequency and lower driving power, which makes the design and development of the existing chip pressing structure still have drawbacks. Summary of the invention
[0006] Based on this, it is necessary to provide a chip packaging shell, a chip packaging structure and a power electronic device to address the above-mentioned technical problems.
[0007] The present application provides a chip packaging shell, wherein the chip packaging shell has a packaging chamber inside, and the packaging chamber includes at least two unit packaging spaces, each of the unit packaging spaces is used to package one type of chip, so that at least two unit packaging spaces can be used to package at least two types of chips, and the at least two types of chips include at least whole wafer chips and discrete chips.
[0008] In one embodiment, the packaging chamber includes a first unit packaging space and a second unit packaging space, the second unit packaging space is an annular space, and the second unit packaging space surrounds the outside of the first unit packaging space, wherein:
[0009] The first unit packaging space is used to arrange the whole wafer chip, and the second unit packaging space is used to arrange the discrete chip, the number of the discrete chips is configured to be several, and the plurality of discrete chips are arranged around the circumference of the first unit packaging space along the second unit packaging space; or,
[0010] The first unit packaging space is used to set the discrete chip, the number of the discrete chips is configured to be several, the whole wafer chip is configured as a ring chip with a through hole in the middle, and the second unit packaging space is used to set the whole wafer chip, and the whole wafer chip is set around the circumference of the first unit packaging space along the second unit packaging space.
[0011] In one embodiment, the packaging chamber also includes a third unit packaging space, which is an annular space. The third unit packaging space surrounds the outer circle of the second unit packaging space. When the second unit packaging space is used to set an annular whole wafer chip, the first unit packaging space and the third unit packaging space are used to jointly set a plurality of the discrete chips, so that the plurality of the discrete chips are distributed in the inner circle and the outer circle of the second unit packaging space at the same time.
[0012] In one embodiment, a first chip packaging component is disposed in the first unit packaging space, and a second chip packaging component is disposed in the second unit packaging space, wherein:
[0013] The whole wafer chip is arranged on the first chip packaging component, thereby indirectly packaging it in the first unit packaging space through the first chip packaging component, the number of the second chip packaging components is configured as a plurality, and the plurality of second chip packaging components are arranged around the circumference of the first unit packaging space along the second unit packaging space, and each of the second chip packaging components is used to arrange one discrete chip, thereby indirectly packaging the plurality of discrete chips in the second unit packaging space through the plurality of second chip packaging components; or,
[0014] The number of the first chip packaging components is configured as several, each of the discrete chips is arranged on one of the first chip packaging components, and is thereby indirectly packaged in the first unit packaging space through the several first chip packaging components, and the annular whole wafer chip is arranged on the second chip packaging component, and is thereby indirectly packaged in the second unit packaging space through the second chip packaging component.
[0015] In one of the embodiments, a third chip packaging component is disposed in the third unit packaging space, and the number of the third chip packaging components is configured to be several, each of the third chip packaging components is used to set one of the discrete chips, thereby indirectly packaging several of the discrete chips in the third unit packaging space through several of the third chip packaging components.
[0016] In one embodiment, the chip packaging shell is a tubular shell, which includes a first unit packaging space and a second unit packaging space. The first unit packaging space is located at the central position of the chip packaging shell, and the central axis of the tubular shell passes through the first unit packaging space. The second unit packaging space is arranged around the central axis of the tubular shell in the circumference of the first unit packaging space.
[0017] In one embodiment, the first unit packaging space is used to arrange the whole wafer chip at the central position of the tubular housing, and the second unit packaging space is used to arrange a plurality of discrete chips around the whole wafer chip; or,
[0018] The first unit packaging space is used to arrange the discrete chip at the central position of the tubular housing, and the second unit packaging space is used to arrange a ring-shaped whole wafer chip around the discrete chip.
[0019] In one embodiment, the tubular shell further includes a third unit packaging space, which is an annular space and is arranged in an outer circle of the second unit packaging space around the central axis of the tubular shell. The third unit packaging space is used to arrange the discrete chip in the outer circle of the second unit packaging space.
[0020] The present application provides a chip packaging structure, the chip packaging structure comprising:
[0021] The chip packaging shell;
[0022] A whole wafer chip, wherein the whole wafer chip is arranged in a packaging cavity of the chip packaging shell;
[0023] A discrete chip is disposed in a packaging cavity of the chip packaging shell.
[0024] The present application provides a power electronic device, wherein the power electronic device comprises the chip packaging structure.
[0025] In the above-mentioned chip packaging shell, chip packaging structure and power electronic device, whole wafer chips and discrete chips are mixed in the packaging chamber of a single chip packaging shell, and the effective area of the two types of chips is configured in combination with the actual application conditions. The combination of the two types of chips complements each other and can simultaneously achieve faster switching frequencies, higher voltage and current levels, and lower chip losses of power semiconductor devices. At the same time, by connecting different types of chips in reverse parallel in the packaging chamber of a single chip packaging shell, the requirements under special conditions such as bidirectional flow, bidirectional pressure bearing, and bidirectional switching can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A three-dimensional schematic diagram of a chip packaging structure provided in one embodiment of the present application.
[0027] Figure 2 An exploded schematic diagram of a chip packaging structure provided in one embodiment of the present application.
[0028] Figure Number:
[0029] 1000, chip packaging shell; 2000, whole wafer chip; 3000, discrete chip;
[0030] 1000a, packaging chamber; 1100, first chip packaging component; 1200, second chip packaging component;
[0031] 1110, center boss; 1120, peripheral boss;
[0032] 1210. Separation element. DETAILED DESCRIPTION
[0033] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0034] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
[0035] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0036] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.
[0037] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0038] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.
[0039] See also Figure 1 and Figure 2 As shown, the present application provides a chip packaging shell 1000, the chip packaging shell 1000 has a packaging chamber 1000a inside, the packaging chamber 1000a includes at least two unit packaging spaces, each unit packaging space is used to package a type of chip, so that at least two unit packaging spaces can be used to package at least two types of chips, and the at least two types of chips include at least a whole wafer chip 2000 and a discrete chip 3000.
[0040] The types of whole wafer chips 2000 may include diodes, thyristors, gate turn-off thyristors (ETO), integrated gate commutated thyristors (IGCT) and emitter turn-off thyristors (ETO). The types of discrete chips 3000 may include diodes, junction field effect oxide transistors (MOSFET), insulated gate bipolar transistors (IGBT), ion implantation enhancement transistors (IEGT) and bi-mode insulated gate transistors (BIGT).
[0041] The multiple unit packaging spaces divided out in the above-mentioned packaging chamber 1000a belong to the division in the packaging chamber 1000a according to factors such as spatial position, spatial size, and spatial shape. The division can be a physical division or a virtual simple spatial division, and there is no need to use physical structures such as partitions and partitions for division. No limitation is made here. As long as multiple unit packaging spaces can be divided out in the packaging chamber 1000a, technical personnel in this field can adopt a suitable method to divide the space according to actual needs.
[0042] The number of unit packaging spaces of the packaging chamber 1000a can be designed according to the number of chip types to be packaged. For example, in one embodiment, the packaging chamber 1000a includes a first unit packaging space and a second unit packaging space. At this time, the number of unit packaging spaces is two. In the two unit packaging spaces, the first unit packaging space can be used to set the whole wafer chip 2000, and the second unit packaging space can be used to set the discrete chip 3000. Therefore, the space size, space shape, etc. of the first unit packaging space can be designed specifically according to the whole wafer chip 2000 to be packaged. At the same time, in order to package a number of discrete chips 3000, the second unit packaging space can be set as an annular space, and the second unit packaging space is arranged around the first unit packaging space. The number of discrete chips 3000 is configured as several, and multiple discrete chips 3000 are arranged around the circumference of the first unit packaging space along the second unit packaging space, so that multiple discrete chips 3000 can be packaged around the whole wafer chip 2000.
[0043] In addition, in another embodiment, the whole wafer chip 2000 can be configured as a ring-shaped chip with a through hole in the middle, so the ring-shaped second unit packaging space can also be used to package the ring-shaped whole wafer chip 2000. For example, the first unit packaging space is used to set the discrete chips 3000, the number of discrete chips 3000 is configured as a plurality, and the second unit packaging space in the form of a ring space is used to set the whole wafer chip 2000 which is also in the form of a ring. In this case, the whole wafer chip 2000 can be arranged around the circumference of the first unit packaging space along the second unit packaging space.
[0044] Since many whole wafer chip 2000 type devices will place their own gate at the edge outer ring position of the device, this ring-shaped whole wafer chip 2000 is located on the periphery of several discrete chips 3000. It is more suitable for this type of whole wafer chip 2000. For example, a mixed crimped edge gate IGCT chip and a discrete diode chip can realize unidirectional current flow and switch control of the device through IGCT, and reverse freewheeling of the device through diode chips, ultimately realizing bidirectional current flow of the device.
[0045] Furthermore, the packaging chamber 1000a may also include a third unit packaging space, which is an annular space, and the third unit packaging space surrounds the outer ring of the second unit packaging space. Therefore, when the second unit packaging space is used to set the annular whole wafer chip 2000, the first unit packaging space and the third unit packaging space are used to jointly set a plurality of discrete chips 3000, so that the plurality of discrete chips 3000 are distributed in the inner ring and the outer ring of the second unit packaging space at the same time, and a plurality of discrete chips 3000, a ring-shaped whole wafer chip 2000 and another plurality of discrete chips 3000 are respectively set in the direction from the first unit packaging space, the second unit packaging space to the third unit packaging space.
[0046] The whole wafer chip 2000 or the discrete chip 3000 can be packaged in the first unit packaging space or the second unit packaging space in a variety of ways. For example, in one embodiment, a first chip packaging component 1100 is disposed in the first unit packaging space, and the whole wafer chip 2000 is disposed on the first chip packaging component 1100, thereby indirectly packaged in the first unit packaging space through the first chip packaging component 1100. The first chip packaging component 1100 can be specifically designed based on the shape, size, etc. of the whole wafer chip 2000 to facilitate packaging of the whole wafer chip 2000.
[0047] In addition, when the second unit packaging space is used to set the annular whole wafer chip 2000, the number of the first chip packaging components 1100 can be configured as several, and each discrete chip 3000 is set on a first chip packaging component 1100, thereby indirectly packaged in the first unit packaging space through several first chip packaging components 1100. At this time, the annular whole wafer chip 2000 can be set on the second chip packaging component 1200, thereby indirectly packaged in the second unit packaging space through the second chip packaging component 1200.
[0048] Furthermore, a third chip packaging component is provided in the third unit packaging space, and the number of the third chip packaging components is configured as a plurality, each of which is used to provide a discrete chip 3000, thereby indirectly packaging a plurality of discrete chips 3000 in the third unit packaging space through the plurality of third chip packaging components. At this time, all discrete chips 3000 can be indirectly packaged in the first unit packaging space and the third unit packaging space through the first chip packaging component 1100 and the third chip packaging component, respectively.
[0049] In one embodiment, the first chip package component 1100 is configured as a first chip package boss disposed in the first unit package space, and the whole wafer chip 2000 is disposed on the first chip package boss. The first chip package component 1100 may include a central boss 1110 and a peripheral boss 1120, wherein the number of the peripheral bosses 1120 is configured as a plurality, and the plurality of peripheral bosses 1120 surround the central boss 1110 along the circumference of the central boss 1110, thereby jointly constituting a basic structure that can be used to support the whole wafer chip 2000.
[0050] A second chip packaging component 1200 is disposed in the second unit packaging space, and the number of the second chip packaging components 1200 is configured as a plurality of them. The plurality of second chip packaging components 1200 are disposed around the circumference of the first unit packaging space along the second unit packaging space, and each discrete chip 3000 is disposed on a second chip packaging component 1200, thereby indirectly packaging the discrete chip 3000 in the second unit packaging space through the second chip packaging component 1200. The second chip packaging component 1200 can be specifically designed based on the number, shape, size, etc. of the discrete chips 3000 to facilitate packaging of the discrete chips 3000. The second chip packaging component 1200 is configured as a second chip packaging boss disposed in the second unit packaging space, and each discrete chip 3000 is disposed on a second chip packaging boss.
[0051] A plurality of second chip packaging components 1200 may be uniformly arranged around the circumference of the first unit packaging space, and adjacent second chip packaging components 1200 may be spaced apart by appropriate gaps. Alternatively, in one embodiment, the second unit packaging space may also be provided with a plurality of partitioning components 1210 along a ring shape, and the plurality of partitioning components 1210 are used to divide the second unit packaging space into a plurality of sub-spaces surrounding the first unit packaging space, and each second chip packaging component 1200 is provided in one sub-space.
[0052] In another embodiment, if the first unit packaging space is used to package discrete chips 3000, then it is necessary to set a plurality of first chip packaging components in the first unit packaging space, and the plurality of first chip packaging components can be evenly distributed in the first unit packaging space, and each discrete chip 3000 is set on a first chip packaging component. At the same time, if there is a third unit packaging space, it is necessary to set a plurality of third chip packaging components in the third unit packaging space, and the plurality of third chip packaging components can be arranged along the third unit packaging space around the outer circle of the second unit packaging space, and each discrete chip 3000 is arranged on a third chip packaging component. Those skilled in the art can select a suitable arrangement according to actual needs, which is not limited here.
[0053] In addition, the whole wafer chip 2000 or the discrete chip 3000 may be directly packaged in the first unit packaging space and the second unit packaging space of the chip packaging shell 1000 without the aid of other components. Technical personnel in this field may select a suitable packaging method according to actual needs, which is not limited here.
[0054] The chip packaging shell 1000 can be set to a variety of shapes, sizes, etc. according to requirements. For example, in one embodiment, the chip packaging shell 1000 is a tubular shell. In one embodiment, the tubular shell includes a first unit packaging space and a second unit packaging space. The first unit packaging space is located at the center of the chip packaging shell 1000. The central axis of the tubular shell passes through the first unit packaging space. The first unit packaging space is used to set the whole wafer chip 2000 at the central position of the tubular shell. The second unit packaging space is set around the central axis of the tubular shell in the circumference of the first unit packaging space. The second unit packaging space is used to set a plurality of discrete chips 3000 around the whole wafer chip 2000.
[0055] In addition, the first unit packaging space can also be used to set a discrete chip 3000 at the central position of the tubular housing, and the second unit packaging space is used to set a ring-shaped whole wafer chip 2000 around the discrete chip 3000. Further, the tubular housing also includes a third unit packaging space, which is an annular space. The third unit packaging space is set around the central axis of the tubular housing on the outer ring of the second unit packaging space, and the third unit packaging space can be used to set the discrete chip 3000 on the outer ring of the second unit packaging space.
[0056] The present application provides a chip packaging structure, which includes the above-mentioned chip packaging shell 1000, a whole wafer chip 2000 and a discrete chip 3000, wherein the whole wafer chip 2000 is arranged in a packaging chamber 1000a of the chip packaging shell 1000, and the discrete chip 3000 is arranged in a packaging chamber 1000a of the chip packaging shell 1000. The whole wafer chip 2000 and the discrete chip 3000 can be distributed in the packaging chamber 1000a of the chip packaging shell 1000 in the manner described above.
[0057] Therefore, by mixing the whole wafer chip 2000 and the discrete chip 3000 in the packaging chamber 1000a of the single chip packaging shell 1000, and configuring the effective area occupied by the two types of chips in combination with the actual application conditions. The combination of the two types of chips complements each other's advantages, and can simultaneously achieve faster switching frequency, higher voltage and current levels, and lower chip losses of power semiconductor devices. At the same time, by anti-parallel connection of different types of chips in the packaging chamber 1000a of the single chip packaging shell 1000, the requirements under special working conditions such as bidirectional flow, bidirectional pressure bearing, and bidirectional switching can be achieved.
[0058] For example, hybrid crimped IGBT / IGCT devices, by configuring the right number of IGBT chips and a reasonable IGCT wafer size, supplemented by the optimal driving strategy that has been analyzed and verified, can simultaneously achieve faster switching speeds for the IGBT devices themselves, more flexible on-off modulation, and higher current surge capabilities and lower device losses for the IGCT devices.
[0059] The present application provides a power electronic device, which includes the above-mentioned chip packaging structure. Since the specific structure, functional principle and technical effect of the above-mentioned chip packaging structure are described in detail in the previous text, they will not be repeated here. Any technical content related to the above-mentioned chip packaging structure can refer to the previous records.
[0060] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0061] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A chip packaging shell, characterized in that: The chip packaging shell has a packaging cavity inside, and the packaging cavity includes at least two unit packaging spaces. Each unit packaging space is used to package one type of chip, so that at least two unit packaging spaces can be used to package at least two types of chips, and the at least two types of chips include at least whole wafer chips and discrete chips.
2. The chip package shell according to claim 1, characterized in that: The packaging chamber comprises a first unit packaging space and a second unit packaging space, wherein the second unit packaging space is an annular space, and the second unit packaging space surrounds the outside of the first unit packaging space, wherein: The first unit packaging space is used to arrange the whole wafer chip, and the second unit packaging space is used to arrange the discrete chip, the number of the discrete chips is configured to be several, and the plurality of discrete chips are arranged around the circumference of the first unit packaging space along the second unit packaging space; or, The first unit packaging space is used to set the discrete chip, the number of the discrete chips is configured to be several, the whole wafer chip is configured as a ring chip with a through hole in the middle, and the second unit packaging space is used to set the whole wafer chip, and the whole wafer chip is set around the circumference of the first unit packaging space along the second unit packaging space.
3. The chip package shell according to claim 2, characterized in that: The packaging chamber also includes a third unit packaging space, which is an annular space. The third unit packaging space surrounds the outer circle of the second unit packaging space. When the second unit packaging space is used to set an annular whole wafer chip, the first unit packaging space and the third unit packaging space are used to jointly set a plurality of the discrete chips, so that the plurality of the discrete chips are distributed in the inner circle and the outer circle of the second unit packaging space at the same time.
4. The chip package shell according to claim 2, characterized in that: A first chip packaging component is disposed in the first unit packaging space, and a second chip packaging component is disposed in the second unit packaging space, wherein: The whole wafer chip is arranged on the first chip packaging component, thereby indirectly packaging it in the first unit packaging space through the first chip packaging component, the number of the second chip packaging components is configured as a plurality, and the plurality of second chip packaging components are arranged around the circumference of the first unit packaging space along the second unit packaging space, and each of the second chip packaging components is used to arrange one discrete chip, thereby indirectly packaging the plurality of discrete chips in the second unit packaging space through the plurality of second chip packaging components; or, The number of the first chip packaging components is configured as several, each of the discrete chips is arranged on one of the first chip packaging components, and is thereby indirectly packaged in the first unit packaging space through the several first chip packaging components, and the annular whole wafer chip is arranged on the second chip packaging component, and is thereby indirectly packaged in the second unit packaging space through the second chip packaging component.
5. The chip packaging shell according to claim 3, characterized in that: A third chip packaging component is arranged in the third unit packaging space, and the number of the third chip packaging components is configured as several, each of the third chip packaging components is used to set one of the discrete chips, thereby indirectly packaging several of the discrete chips in the third unit packaging space through several of the third chip packaging components.
6. The chip package shell according to claim 1, characterized in that: The chip packaging shell is a tubular shell, which includes a first unit packaging space and a second unit packaging space. The first unit packaging space is located at the central position of the chip packaging shell, and the central axis of the tubular shell passes through the first unit packaging space. The second unit packaging space is arranged around the central axis of the tubular shell in the circumference of the first unit packaging space.
7. The chip package shell according to claim 6, characterized in that: The first unit packaging space is used to arrange the whole wafer chip at the central position of the tubular housing, and the second unit packaging space is used to arrange a plurality of discrete chips around the whole wafer chip; or, The first unit packaging space is used to arrange the discrete chip at the central position of the tubular housing, and the second unit packaging space is used to arrange a ring-shaped whole wafer chip around the discrete chip.
8. The chip package shell according to claim 7, characterized in that: The tubular shell also includes a third unit packaging space, which is an annular space and is arranged in the outer circle of the second unit packaging space around the central axis of the tubular shell. The third unit packaging space is used to arrange the discrete chip in the outer circle of the second unit packaging space.
9. A chip packaging structure, characterized in that: The chip packaging structure comprises: The chip package shell according to any one of claims 1 to 8; A whole wafer chip, wherein the whole wafer chip is arranged in a packaging cavity of the chip packaging shell; A discrete chip is disposed in a packaging cavity of the chip packaging shell.
10. A power electronic device, characterized in that: The power electronic device comprises the chip packaging structure as claimed in claim 9.