Overcurrent protection circuit

Abstract

The utility model discloses an overcurrent protection circuit, and belongs to the technical field of protection circuits of frequency converters. The objective of the utility model is to solve the technical problem of misoperation caused by over-current detection signal feedback on a frequency converter. According to the technical scheme, the overcurrent protection circuit comprises a sampling end used for obtaining a sampling signal A of current, the sampling end is connected with an even number of phase inverters to output a sampling signal B, the sampling signal A and the sampling signal B are connected with the input end of an NAND gate, and the output end of the NAND gate is used for outputting an overcurrent protection feedback signal, so that frequent start and stop are reduced, and the overcurrent protection effect is improved. And misjudgment of over-current protection of the frequency converter caused by external interference signals is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of protection circuits for frequency converters, and in particular to an overcurrent protection circuit. Background Art

[0002] The overcurrent protection function of the inverter is the guarantee for the normal and stable operation of the inverter and the motor it controls. Unreasonable overcurrent protection control logic will affect the normal and stable operation of the inverter or reduce the service life of the inverter and the motor.

[0003] In the past, the method used was mainly to convert the sampled current into a voltage signal and transmit it to the comparator. After the comparator compares the voltage signal with the preset reference value, the output signal of the comparator is used as the feedback signal for overcurrent protection. However, this overcurrent protection method has many problems. For example, if the sampled voltage signal has a slight fluctuation above and below the preset reference value of the comparator, the output signal of the comparator will frequently switch between high and low levels. The inverter receives a feedback signal with frequent high and low level switching, which will cause the inverter to frequently enter overcurrent protection. Not only can it not work normally, but it is also easy to damage the inverter. In another case, the comparator voltage signal is interfered by an external signal, resulting in malfunction, causing the output signal of the comparator to switch between high and low levels, thereby causing the microcontroller to misjudge the overcurrent protection, making the inverter unable to operate stably. Utility Model Content

[0004] In view of the above-mentioned shortcomings (problems) of the prior art, the utility model provides a new overcurrent protection circuit, which can effectively solve the above problems, reduce frequent starts and stops, and is not prone to misjudgment of the inverter overcurrent protection due to external interference signals.

[0005] To achieve the above objectives and other related objectives, this application adopts the following technical solutions:

[0006] An overcurrent protection circuit includes a sampling end for obtaining a current sampling signal A, the sampling end is connected to an even number of inverters for outputting a sampling signal B, the sampling signal A and the sampling signal B are respectively connected to the input ends of a NAND gate, and the output end of the NAND gate is used to output an overcurrent protection feedback signal.

[0007] Preferably, the sampling end is connected to sampling circuit 1, and the sampling circuit 1 includes resistor R1, resistor R2, resistor R3, resistor R4, capacitor C1 and transistor N1. One end of resistor R1 is used to connect to the inverter and one end of resistor R2. The other end of resistor R1 is grounded. The other end of resistor R2 is connected to one end of resistor R3 and the base of transistor N1. The collector of transistor N1 is connected to one end of resistor R4 and one end of capacitor C1 and outputs sampling signal A. The other end of resistor R4 is connected to voltage source VCC. The other end of resistor R3, the emitter of transistor N1 and the other end of capacitor C1 are grounded.

[0008] Preferably, a resistor-capacitor filter is connected between two adjacent inverters.

[0009] Preferably, the RC filter comprises a resistor R5 and a capacitor C2, the resistor R5 is used to be connected between two inverters, and the capacitor C2 is used to be grounded through the capacitor C2 at the output end of the resistor.

[0010] Preferably, the output end of the NAND gate is connected to a feedback circuit, which includes a resistor R7, an electron R8, a transistor N2 and a resistor R6. The output end of the NAND gate is connected to one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R7 and the base of the transistor N2, the other end of the resistor R7 and the emitter of the transistor N2 are grounded, the collector of the transistor N2 is connected to one end of the resistor R6 and is used to output a feedback signal of overcurrent protection, and the other end of the resistor R6 is connected to the voltage source VCC.

[0011] Preferably, the sampling end is connected to sampling circuit 2, and the sampling circuit 2 includes resistor R1, resistor R2, resistor R3, resistor R4, resistor R9, capacitor C3, capacitor C1 and comparator U5. One end of resistor R1 is used to connect the frequency converter and one end of resistor R3, the other end of resistor R1 is grounded, the other end of resistor R3 is connected to the inverting end of comparator U5, the non-inverting end of comparator U5 is connected to one end of resistor R2, one end of capacitor C3 and one end of resistor R4, the other end of capacitor C3 and the other end of resistor R2 are grounded, the other end of resistor R4 is connected to one end of resistor R9 and voltage source VCC, the other end of resistor R9, one end of capacitor C1 and the output end of comparator U1 are connected in common and output sampling signal A, and the other end of capacitor C1 is grounded.

[0012] In summary, the present application includes at least one of the following beneficial technical effects:

[0013] This solution uses two inverters and resistors and capacitors to make the current signal generate a signal that is the same as the current signal but delayed. The two signals jointly control the NAND gate trigger, and the NAND gate (trigger) outputs the feedback signal of the overcurrent protection. This solution can extend the overcurrent protection time, reduce frequent starts and stops, and is not prone to misjudgment of the inverter overcurrent protection due to external interference signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit schematic diagram of Embodiment 1 of the present application;

[0015] Figure 2 This is a circuit diagram of the second embodiment of the present application.

[0016] Description of main reference numerals:

[0017] 100, sampling end; 200, sampling circuit 1; 300, sampling circuit 2; 400, resistor-capacitor filter; 500, feedback circuit. DETAILED DESCRIPTION

[0018] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0020] The specific implementation methods of the present application will be further described below in conjunction with the accompanying drawings.

[0021] Embodiment 1:

[0022] The present application discloses an overcurrent protection circuit. Figure 1 As shown, it includes a sampling terminal 100 for obtaining a current sampling signal A. The sampling terminal 100 is connected to an even number of inverters to output a sampling signal B. The sampling signal A and the sampling signal B are respectively connected to the input terminals of a NAND gate. The output terminal of the NAND gate is used to output a feedback signal of an overcurrent protection.

[0023] Specifically, the sampling end 100 is connected to a sampling circuit 200, and the sampling circuit 200 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and a transistor N1. One end of the resistor R1 is used to connect to the inverter and to one end of the resistor R2. The other end of the resistor R1 is grounded. The other end of the resistor R2 is connected to one end of the resistor R3 and the base of the transistor N1. The collector of the transistor N1 is connected to one end of the resistor R4 and one end of the capacitor C1 and outputs a sampling signal A. The other end of the resistor R4 is connected to a voltage source VCC. The other end of the resistor R3, the emitter of the transistor N1 and the other end of the capacitor C1 are grounded.

[0024] Preferably, a resistor-capacitor filter is connected between two adjacent inverters.

[0025] Preferably, the RC filter comprises a resistor R5 and a capacitor C2, the resistor R5 is used to be connected between two inverters, and the capacitor C2 is used to be grounded through the capacitor C2 at the output end of the resistor.

[0026] Preferably, the output end of the NAND gate is connected to a feedback circuit, which includes a resistor R7, an electron R8, a transistor N2 and a resistor R6. The output end of the NAND gate is connected to one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R7 and the base of the transistor N2, the other end of the resistor R7 and the emitter of the transistor N2 are grounded, the collector of the transistor N2 is connected to one end of the resistor R6 and is used to output a feedback signal for overcurrent protection, and the other end of the resistor R6 is connected to the voltage source VCC.

[0027] The voltage signal V1 is obtained from the (sampling) resistor R1 of the frequency converter to drive the transistor N1 switch, thereby obtaining a signal A at the transistor collector. Signal A passes through two inverters and the resistor and capacitor between the inverters to obtain a delayed signal B with the same level as signal A. Signal A and signal B are used as the input of the NAND gate trigger U4. The output of U4 controls the switch of the transistor N2, and a signal C is obtained at the transistor collector. Signal C is used as the feedback signal of the overcurrent protection. The frequency converter determines whether to enter the overcurrent protection through signal C.

[0028] The power part of the inverter is a conventional circuit and is not protected by this patent, so it will not be described in detail.

[0029] The combination of the inverter and the NAND gate trigger is used to make the rising and falling edges of the inverter's overcurrent feedback signal waveform faster and extend the overcurrent protection time so that the inverter will not start and stop frequently. The transistors N1, N2, and the capacitors C1, C2 also make the overcurrent feedback signal C less susceptible to external interference signals, avoiding misjudgment of overcurrent protection, thereby making the inverter work more stable.

[0030] This circuit has the following working conditions:

[0031] 1. When the inverter is working, the voltage V1 is generated on R1 through the R1 sampling resistor. When the value of V1 cannot drive the transistor N1 to conduct, the collector signal A of N1 outputs a high level. After signal A passes through U2 and U3, the signal B is a high level.

[0032] At this time, because both signal A and signal B are high level, U4 outputs low level, N2 is not conducting, and signal C always outputs high level. The inverter receives signal C as high level and determines that the working current is normal. The inverter is controlled to work stably.

[0033] 2. When the value of V1 can drive transistor N1 to turn on within T1 time, the collector signal A of N1 changes from high level to low level.

[0034] Signal A outputs a high level through inverter U2 and charges C2 through R5. The charging time is recorded as T2. After C2 is charged, the signal outputs a low level signal B through inverter U3.

[0035] At this time, in the T1+T2 time period, one of the signals A and B is at a low level, and both signals output a high level after passing through the NAND gate U4. The high level output of U4 controls N2 to turn on, causing the signal C to change from a high level to a low level. The inverter receives the signal C as a low level and enters the overcurrent protection, and the inverter stops working.

[0036] In summary, when signal A and signal B output high level at the same time, U4 outputs low level, and signal C outputs high level as the current feedback signal, and the inverter maintains stable operation. If signal A is low level or signal B is low level, or both are low level, U4 outputs high level, and signal C outputs low level as the current feedback signal, and the inverter receives the overcurrent protection signal and stops working. In this way, the overcurrent protection time is extended, so that the inverter will not start and stop frequently.

[0037] Embodiment 2:

[0038] Based on the above embodiment 1, the difference is that another sampling circuit is used. If the transistor circuit of the output signal A is changed to use a comparator output mode, the principle is still valid.

[0039] principle Figure 1 In the example, the V1 signal is used to drive the N1 transistor switch to obtain the signal A. The V1 signal is changed to be compared with the comparator reference voltage, so that the comparator outputs the signal A. The inverter and NAND gate logic combination circuit of the subsequent stage remain unchanged.

[0040] For a specific example, refer to Figure 2As shown, the sampling end 100 is connected to the sampling circuit 2. The sampling circuit 2 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R9, a capacitor C3, a capacitor C1 and a comparator U5. One end of the resistor R1 is used to connect the frequency converter and one end of the resistor R3. The other end of the resistor R1 is grounded. The other end of the resistor R3 is connected to the inverting end of the comparator U5. The inverting end of the comparator U5 is connected to one end of the resistor R2, one end of the capacitor C3 and one end of the resistor R4. The other end of the capacitor C3 and the other end of the resistor R2 are grounded. The other end of the resistor R4 is connected to one end of the resistor R9 and the voltage source VCC. The other end of the resistor R9, one end of the capacitor C1 and the output end of the comparator U1 are connected together and output the sampling signal A. The other end of the capacitor C1 is grounded.

[0041] The V1 signal is obtained through the (sampling) resistor R1 as the input of one end of the comparator, and compared with the Vref reference voltage at the other end. The output of the comparator is signal A. When the V1 voltage is less than the reference voltage, signal A outputs a high level. When the V1 voltage is greater than the reference voltage, signal A outputs a low level.

[0042] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An overcurrent protection circuit, comprising a sampling terminal (100) for obtaining a current sampling signal A, characterized in that: The sampling end (100) is connected to an even number of inverters to output a sampling signal B, the sampling signal A and the sampling signal B are respectively connected to the input ends of a NAND gate, and the output end of the NAND gate is used to output an overcurrent protection feedback signal.

2. An overcurrent protection circuit according to claim 1, characterized in that: The sampling end (100) is connected to a sampling circuit 1 (200), and the sampling circuit 1 (200) comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and a transistor N1. One end of the resistor R1 is used to connect to the frequency converter and to one end of the resistor R2. The other end of the resistor R1 is grounded. The other end of the resistor R2 is connected to one end of the resistor R3 and the base of the transistor N1. The collector of the transistor N1 is connected to one end of the resistor R4 and one end of the capacitor C1 and outputs a sampling signal A. The other end of the resistor R4 is connected to a voltage source VCC. The other end of the resistor R3, the emitter of the transistor N1 and the other end of the capacitor C1 are grounded.

3. An overcurrent protection circuit according to claim 2, characterized in that: A resistor-capacitor filter is connected between two adjacent inverters.

4. An overcurrent protection circuit according to claim 3, characterized in that: The RC filter comprises a resistor R5 and a capacitor C2. The resistor R5 is used to be connected between two inverters, and the capacitor C2 is used to be grounded through the capacitor C2 at the output end of the resistor.

5. An overcurrent protection circuit according to claim 4, characterized in that: The output end of the NAND gate is connected to a feedback circuit, which includes a resistor R7, an electron R8, a transistor N2 and a resistor R6. The output end of the NAND gate is connected to one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R7 and the base of the transistor N2, the other end of the resistor R7 and the emitter of the transistor N2 are grounded, the collector of the transistor N2 is connected to one end of the resistor R6 and is used to output a feedback signal of overcurrent protection, and the other end of the resistor R6 is connected to the voltage source VCC.

6. The overcurrent protection circuit according to claim 1, characterized in that: The sampling end (100) is connected to a second sampling circuit, which comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R9, a capacitor C3, a capacitor C1 and a comparator U5. One end of the resistor R1 is used to connect to the frequency converter and one end of the resistor R3. The other end of the resistor R1 is grounded. The other end of the resistor R3 is connected to the inverting end of the comparator U5. The non-inverting end of the comparator U5 is connected to one end of the resistor R2, one end of the capacitor C3 and one end of the resistor R4. The other end of the capacitor C3 and the other end of the resistor R2 are grounded. The other end of the resistor R4 is connected to one end of the resistor R9 and a voltage source VCC. The other end of the resistor R9, one end of the capacitor C1 and the output end of the comparator U1 are connected in common and output a sampling signal A. The other end of the capacitor C1 is grounded.

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