Double-shaft anti-seismic signal processing circuit of vortex shedding flowmeter

Abstract

The utility model belongs to the technical field of measurement, and relates to a double-shaft anti-seismic signal processing circuit of a vortex shedding flowmeter, which is characterized in that the output ends of a main probe and a Y-axis auxiliary probe of the circuit are respectively connected with the input end of a differential amplification circuit 1 through a charge amplification circuit 1 and a charge amplification circuit 2; the output end of the X-axis auxiliary probe is connected with the input end of the differential amplification circuit 2 through the charge amplification circuit 3, the output end of the differential amplification circuit 1 is connected with the input end of the differential amplification circuit 2, and the output end of the differential amplification circuit 2 and the output end of the CPU are connected with the input end of the shaping circuit and the input end of the AD conversion circuit through the adjustable gain amplification circuit. The output ends of the AD conversion circuit and the shaping circuit are connected with the input end of the CPU; vibration signals in two axial directions are obtained through the Y-direction auxiliary probe and the X-direction auxiliary probe, the anti-vibration effect is achieved through differential operation with signals of the main probe, and the measurement lower limit of the vortex shedding flowmeter is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of vortex flowmeters, in particular to a double-axis anti-vibration signal processing circuit for a vortex flowmeter. Background Art

[0002] Vortex flowmeter is a volume flowmeter that measures the volume flow rate of gas, steam or liquid, the volume flow rate of standard conditions or the mass flow rate based on the Karman vortex principle. It is characterized by small pressure loss, large measuring range, high accuracy, and is almost unaffected by fluid density, pressure, temperature, viscosity and other parameters when measuring the working volume flow rate.

[0003] Each vortex flowmeter has a triangular column installed in the center of the pipe. The triangular column is an obstacle that interferes with the flow field. Downstream of the triangular column is a piezoelectric sensor used to record the slightest pressure difference generated by the flowing fluid. If the fluid does not flow, no vortex will be generated. Once the fluid starts to flow and reaches a certain flow rate, vortices will gradually form downstream of the triangular column. These vortices are alternately separated on both sides of the triangular column and carried away by the fluid. At this time, high-pressure and low-pressure areas are formed downstream of the triangular column, resulting in a phenomenon called "Karman vortex street". These pressure differences are perfectly matched to the frequency of the passing vortices and are accurately measured by the piezoelectric sensor. The distance between two consecutive vortices corresponds to a specific volume of the fluid. Therefore, counting the passing vortices can calculate the total flow rate.

[0004] At present, most vortex flowmeters do not have anti-seismic protection. The instrument part of the vortex flowmeter is easily affected by external vibration during actual use, which affects the accuracy of the flowmeter and brings more troubles to the working process. The interference caused by vibration will also affect the measurement lower limit of the vortex flowmeter. The vibration interference reduces the signal-to-noise ratio at low flow rates and affects the measurement accuracy. Utility Model Content

[0005] The utility model aims to overcome the shortcomings of the prior art and provide a dual-axis anti-vibration signal processing circuit for a vortex flowmeter.

[0006] In order to achieve the purpose of the utility model, the utility model is implemented by adopting the following technical solution.

[0007] A dual-axis anti-seismic signal processing circuit for a vortex flowmeter includes a main probe, a Y-axis auxiliary probe, an X-axis auxiliary probe, a charge amplifier circuit 1, a charge amplifier circuit 2, a charge amplifier circuit 3, a differential amplifier circuit 1, a differential amplifier circuit 2, an adjustable gain amplifier circuit, an AD conversion circuit, a shaping circuit and a CPU, wherein:

[0008] The output ends of the main probe and the Y-axis auxiliary probe are connected to the input end of the differential amplifier circuit 1 through the charge amplifier circuit 1 and the charge amplifier circuit 2 respectively;

[0009] The output end of the X-axis auxiliary probe is connected to the input end of the differential amplifier circuit 2 through the charge amplifier circuit 3;

[0010] The output end of the differential amplifier circuit 1 is connected to the input end of the differential amplifier circuit 2;

[0011] The output ends of the differential amplifier circuit 2 and the CPU are respectively connected to the input ends of the shaping circuit and the AD conversion circuit through an adjustable gain amplifier circuit;

[0012] The output ends of the AD conversion circuit and the shaping circuit are connected to the input end of the CPU.

[0013] As a preferred solution of the utility model, the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 are respectively composed of a charge amplifier circuit, and the charge amplifier circuit is composed of a probe U1, a resistor R1, a resistor R2, a resistor R3, an operational amplifier U3, a capacitor C1, a capacitor C2, a capacitor C4 and a capacitor C6, wherein:

[0014] The probes U1 are respectively the main probe, the Y-direction auxiliary probe and the X-direction auxiliary probe, so as to respectively constitute the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3;

[0015] The output terminal 1 of the probe U1 is connected to the in-phase input terminal 3 of the operational amplifier U3 through the capacitor C4;

[0016] The output terminal 2 of the probe U1 is connected to the inverting input terminal 4 of the operational amplifier U3 through the capacitor C6;

[0017] The connection line between the output terminal 1 of the probe U1 and the capacitor C4 is connected to the connection line between the output terminal 2 of the probe U1 and the capacitor C6 via the resistor R3;

[0018] The connection line between the capacitor C6 and the inverting input terminal 4 of the operational amplifier U3 is connected to the output terminal 1 of the operational amplifier U3 through the resistor R1 and the capacitor C1 connected in parallel, so as to form the output terminals S1, S2 and S3 of the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 respectively;

[0019] The connection line between the capacitor C4 and the in-phase input terminal 3 of the operational amplifier U3 is connected to the power supply VCC / 2 through the parallel resistor R2 and the capacitor C2;

[0020] The voltage input terminal 5 of the operational amplifier U3 is connected to the power supply VCC, and the ground terminal 2 is grounded.

[0021] As a preferred solution of the utility model, the output terminal S1 of the charge amplifier circuit 1 is connected to the inverting input terminal 4 of the operational amplifier U4 through the capacitor C7;

[0022] The output terminal S2 of the charge amplifier circuit 2 is connected to the in-phase input terminal 3 of the operational amplifier U4 through the capacitor C9;

[0023] The connection line between the output terminal S1 of the charge amplifier circuit 1 and the capacitor C7 is connected to the connection line between the output terminal S2 of the charge amplifier circuit 2 and the capacitor C9 through the resistor R4;

[0024] The connection line between the capacitor C9 and the in-phase input terminal 3 of the operational amplifier U4 is connected to the power supply VCC / 2 through the parallel resistor R6 and the capacitor C10;

[0025] The voltage input terminal 5 of the operational amplifier U4 is connected to the power supply VCC, and the ground terminal 2 is grounded;

[0026] The connection line between the capacitor C7 and the inverting input terminal 4 of the operational amplifier U4 is connected to the output terminal 1 of the operational amplifier U4 through the parallel resistor R7 and the capacitor C11, forming the output terminal of the differential amplifier circuit 1;

[0027] The output terminal S3 of the charge amplifier circuit 3 is connected to the in-phase input terminal 3 of the operational amplifier U6 through the capacitor C13;

[0028] The output end of the differential amplifier circuit 1 is connected to the inverting input end 4 of the operational amplifier U6 via the capacitor C22;

[0029] The connection line between the output terminal S3 of the charge amplifier circuit 3 and the capacitor C13 is connected to the connection line between the output terminal of the differential amplifier circuit 1 and the capacitor C22 through the resistor R10;

[0030] The connection line between the capacitor C22 and the inverting input terminal 4 of the operational amplifier U6 is connected to the output terminal 1 of the operational amplifier U6 through the parallel resistor R8 and the capacitor C8, forming the output terminal S4 of the differential amplifier circuit 2;

[0031] The connection line between the capacitor C13 and the in-phase input terminal 3 of the operational amplifier U6 is connected to the power supply VCC / 2 through the parallel resistor R9 and the capacitor C12;

[0032] The voltage input terminal 5 of the operational amplifier U6 is connected to the power supply VCC, and the ground terminal 2 is grounded.

[0033] As a preferred solution of the present utility model, the output terminal S4 of the differential amplifier circuit 2 is connected to the in-phase input terminal 3 of the operational amplifier U2 through the resistor R14;

[0034] The connection line between the resistor R14 and the in-phase input terminal 3 of the operational amplifier U2 is connected to the power supply VCC / 2 through the capacitor C5;

[0035] The voltage input terminal 5 of the operational amplifier U2 is connected to the power supply VCC, and the ground terminal 2 is grounded;

[0036] The inverting input terminal 4 of the operational amplifier U2 is connected to the output terminal 1 of the operational amplifier U2 through a resistor R15 and a capacitor C14 connected in parallel, forming an output terminal S5 of the adjustable gain amplifier circuit;

[0037] The inverting input terminal 4 of the operational amplifier U2 is also connected to the output terminals 3 of the electronic analog switches SW5, SW6, SW7 and SW8 respectively through the resistors R16, R17, R24 and R25;

[0038] The control terminals 4 of the electronic analog switches SW5, SW6, SW7 and SW8 are connected to the IO interfaces 1, 2, 3 and 4 of the CPU respectively;

[0039] The voltage input terminals 2 of the electronic analog switches SW5, SW6, SW7 and SW8 are all connected to the power supply VCC / 2.

[0040] As a preferred solution of the utility model, the output terminal S5 of the adjustable gain amplifier circuit is connected to the in-phase input terminal 3 of the operational amplifier U20 through the resistor R11;

[0041] The voltage input terminal 5 of the operational amplifier U20 is connected to the power supply VCC, and the ground terminal 2 is grounded;

[0042] The inverting input terminal 4 of the operational amplifier U20 is grounded through a resistor R65 and a capacitor C52 connected in parallel, and is connected to a power source VCC through a resistor R63;

[0043] The output terminal 1 of the operational amplifier U20 outputs a signal S6.

[0044] Compared with the prior art, the beneficial effects achieved by the utility model are:

[0045] In the utility model, the differential compensation of the main probe signal by the auxiliary probes of the X and Y axes can effectively remove the vibration interference in the main probe signal and avoid the influence of the vibration interference; and the CPU controls the adjustable gain amplifier circuit to realize automatic gain control of the signal, ensure the signal strength, realize accurate measurement of the vortex flowmeter signal under low flow rate, and reduce the measurement lower limit. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a structural schematic diagram of the dual-axis anti-seismic signal processing circuit;

[0047] Figure 2 is a circuit diagram of the charge amplifier circuit;

[0048] Figure 3 is a circuit diagram of the differential amplifier circuit 1 and the differential amplifier circuit 2;

[0049] Figure 4 A circuit diagram of the adjustable gain amplifier circuit;

[0050] Figure 5 is a circuit diagram of the shaping circuit. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0052] As an embodiment of the present utility model, Figure 1 As shown, a dual-axis anti-seismic signal processing circuit of a vortex flowmeter includes a main probe, a Y-axis auxiliary probe, an X-axis auxiliary probe, a charge amplifier circuit 1, a charge amplifier circuit 2, a charge amplifier circuit 3, a differential amplifier circuit 1, a differential amplifier circuit 2, an adjustable gain amplifier circuit, an AD conversion circuit, a shaping circuit and a CPU, wherein:

[0053] The output ends of the main probe and the Y-axis auxiliary probe are connected to the input end of the differential amplifier circuit 1 through the charge amplifier circuit 1 and the charge amplifier circuit 2 respectively;

[0054] The output end of the X-axis auxiliary probe is connected to the input end of the differential amplifier circuit 2 through the charge amplifier circuit 3;

[0055] The output end of the differential amplifier circuit 1 is connected to the input end of the differential amplifier circuit 2;

[0056] The output ends of the differential amplifier circuit 2 and the CPU are respectively connected to the input ends of the shaping circuit and the AD conversion circuit through an adjustable gain amplifier circuit;

[0057] The output ends of the AD conversion circuit and the shaping circuit are connected to the input end of the CPU.

[0058] As an embodiment of the present utility model, Figure 2As shown, the structures of the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 are as follows: the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 are respectively composed of a charge amplifier circuit, and the charge amplifier circuit is composed of a probe U1, a resistor R1, a resistor R2, a resistor R3, an operational amplifier U3, a capacitor C1, a capacitor C2, a capacitor C4 and a capacitor C6, wherein:

[0059] The probes U1 are respectively the main probe, the Y-direction auxiliary probe and the X-direction auxiliary probe, so as to respectively constitute the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3;

[0060] The output terminal 1 of the probe U1 is connected to the in-phase input terminal 3 of the operational amplifier U3 through the capacitor C4;

[0061] The output terminal 2 of the probe U1 is connected to the inverting input terminal 4 of the operational amplifier U3 through the capacitor C6;

[0062] The connection line between the output terminal 1 of the probe U1 and the capacitor C4 is connected to the connection line between the output terminal 2 of the probe U1 and the capacitor C6 via the resistor R3;

[0063] The connection line between the capacitor C6 and the inverting input terminal 4 of the operational amplifier U3 is connected to the output terminal 1 of the operational amplifier U3 through the resistor R1 and the capacitor C1 connected in parallel, so as to form the output terminals S1, S2 and S3 of the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 respectively;

[0064] The connection line between the capacitor C4 and the in-phase input terminal 3 of the operational amplifier U3 is connected to the power supply VCC / 2 through the parallel resistor R2 and the capacitor C2;

[0065] The voltage input terminal 5 of the operational amplifier U3 is connected to the power supply VCC, and the ground terminal 2 is grounded.

[0066] As an embodiment of the present utility model, Figure 3 As shown, the structures and connection relationship of the differential amplifier circuit 1 and the differential amplifier circuit 2 are as follows: the output terminal S1 of the charge amplifier circuit 1 is connected to the inverting input terminal 4 of the operational amplifier U4 through the capacitor C7;

[0067] The output terminal S2 of the charge amplifier circuit 2 is connected to the in-phase input terminal 3 of the operational amplifier U4 through the capacitor C9;

[0068] The connection line between the output terminal S1 of the charge amplifier circuit 1 and the capacitor C7 is connected to the connection line between the output terminal S2 of the charge amplifier circuit 2 and the capacitor C9 through the resistor R4;

[0069] The connection line between the capacitor C9 and the in-phase input terminal 3 of the operational amplifier U4 is connected to the power supply VCC / 2 through the parallel resistor R6 and the capacitor C10;

[0070] The voltage input terminal 5 of the operational amplifier U4 is connected to the power supply VCC, and the ground terminal 2 is grounded;

[0071] The connection line between the capacitor C7 and the inverting input terminal 4 of the operational amplifier U4 is connected to the output terminal 1 of the operational amplifier U4 through the parallel resistor R7 and the capacitor C11, forming the output terminal of the differential amplifier circuit 1;

[0072] The output terminal S3 of the charge amplifier circuit 3 is connected to the in-phase input terminal 3 of the operational amplifier U6 through the capacitor C13;

[0073] The output end of the differential amplifier circuit 1 is connected to the inverting input end 4 of the operational amplifier U6 via the capacitor C22;

[0074] The connection line between the output terminal S3 of the charge amplifier circuit 3 and the capacitor C13 is connected to the connection line between the output terminal of the differential amplifier circuit 1 and the capacitor C22 through the resistor R10;

[0075] The connection line between the capacitor C22 and the inverting input terminal 4 of the operational amplifier U6 is connected to the output terminal 1 of the operational amplifier U6 through the parallel resistor R8 and the capacitor C8, forming the output terminal S4 of the differential amplifier circuit 2;

[0076] The connection line between the capacitor C13 and the in-phase input terminal 3 of the operational amplifier U6 is connected to the power supply VCC / 2 through the parallel resistor R9 and the capacitor C12;

[0077] The voltage input terminal 5 of the operational amplifier U6 is connected to the power supply VCC, and the ground terminal 2 is grounded.

[0078] As an embodiment of the present utility model, Figure 4 As shown, the structure of the adjustable gain amplifier circuit is as follows: the output terminal S4 of the differential amplifier circuit 2 is connected to the in-phase input terminal 3 of the operational amplifier U2 through the resistor R14;

[0079] The connection line between the resistor R14 and the in-phase input terminal 3 of the operational amplifier U2 is connected to the power supply VCC / 2 through the capacitor C5;

[0080] The voltage input terminal 5 of the operational amplifier U2 is connected to the power supply VCC, and the ground terminal 2 is grounded;

[0081] The inverting input terminal 4 of the operational amplifier U2 is connected to the output terminal 1 of the operational amplifier U2 through a resistor R15 and a capacitor C14 connected in parallel, forming an output terminal S5 of the adjustable gain amplifier circuit;

[0082] The inverting input terminal 4 of the operational amplifier U2 is also connected to the output terminals 3 of the electronic analog switches SW5, SW6, SW7 and SW8 respectively through the resistors R16, R17, R24 and R25;

[0083] The control terminals 4 of the electronic analog switches SW5, SW6, SW7 and SW8 are connected to the IO interfaces 1, 2, 3 and 4 of the CPU respectively;

[0084] The voltage input terminals 2 of the electronic analog switches SW5, SW6, SW7 and SW8 are all connected to the power supply VCC / 2.

[0085] As an embodiment of the present utility model, Figure 5 As shown, the structure of the shaping circuit is as follows: the output terminal S5 of the adjustable gain amplifier circuit is connected to the in-phase input terminal 3 of the operational amplifier U20 through the resistor R11;

[0086] The voltage input terminal 5 of the operational amplifier U20 is connected to the power supply VCC, and the ground terminal 2 is grounded;

[0087] The inverting input terminal 4 of the operational amplifier U20 is grounded through a resistor R65 and a capacitor C52 connected in parallel, and is connected to a power source VCC through a resistor R63;

[0088] The output terminal 1 of the operational amplifier U20 outputs a signal S6.

[0089] In this embodiment, the main probe is a flow measurement probe, the Y-axis auxiliary probe is a Y-axis vibration interference measurement probe, and the X-axis auxiliary probe is an X-axis vibration interference measurement probe. The vibration interference signal measured by the auxiliary probes of the X and Y axes is used to perform differential compensation on the main probe signal, which can effectively remove the vibration interference in the main probe signal and avoid the influence of vibration interference. At the same time, the signal amplitude is measured by the AD conversion module of the CPU, and the adjustable gain amplifier circuit is controlled to realize automatic gain control of the signal and ensure the signal strength. After adjustment by the shaping circuit, the frequency signal is collected by the CPU and converted into a flow value by calculation. This method can realize accurate measurement of the vortex flowmeter signal under low flow rate and reduce the measurement lower limit.

[0090] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A dual-axis anti-seismic signal processing circuit for a vortex flowmeter, characterized in that: It includes a main probe, a Y-axis auxiliary probe, an X-axis auxiliary probe, a charge amplifier circuit 1, a charge amplifier circuit 2, a charge amplifier circuit 3, a differential amplifier circuit 1, a differential amplifier circuit 2, an adjustable gain amplifier circuit, an AD conversion circuit, a shaping circuit and a CPU, wherein: The output ends of the main probe and the Y-axis auxiliary probe are connected to the input end of the differential amplifier circuit 1 through the charge amplifier circuit 1 and the charge amplifier circuit 2 respectively; The output end of the X-axis auxiliary probe is connected to the input end of the differential amplifier circuit 2 through the charge amplifier circuit 3; The output end of the differential amplifier circuit 1 is connected to the input end of the differential amplifier circuit 2; The output ends of the differential amplifier circuit 2 and the CPU are respectively connected to the input ends of the shaping circuit and the AD conversion circuit through an adjustable gain amplifier circuit; The output ends of the AD conversion circuit and the shaping circuit are connected to the input end of the CPU.

2. A dual-axis anti-seismic signal processing circuit for a vortex flowmeter according to claim 1, characterized in that: The charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 are respectively composed of a charge amplifier circuit, and the charge amplifier circuit is composed of a probe U1, a resistor R1, a resistor R2, a resistor R3, an operational amplifier U3, a capacitor C1, a capacitor C2, a capacitor C4 and a capacitor C6, wherein: The probes U1 are respectively the main probe, the Y-direction auxiliary probe and the X-direction auxiliary probe, so as to respectively constitute the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3; The output terminal 1 of the probe U1 is connected to the in-phase input terminal 3 of the operational amplifier U3 through the capacitor C4; The output terminal 2 of the probe U1 is connected to the inverting input terminal 4 of the operational amplifier U3 through the capacitor C6; The connection line between the output terminal 1 of the probe U1 and the capacitor C4 is connected to the connection line between the output terminal 2 of the probe U1 and the capacitor C6 via the resistor R3; The connection line between the capacitor C6 and the inverting input terminal 4 of the operational amplifier U3 is connected to the output terminal 1 of the operational amplifier U3 through the resistor R1 and the capacitor C1 connected in parallel, so as to form the output terminals S1, S2 and S3 of the charge amplifier circuit 1, the charge amplifier circuit 2 and the charge amplifier circuit 3 respectively; The connection line between the capacitor C4 and the in-phase input terminal 3 of the operational amplifier U3 is connected to the power supply VCC / 2 through the parallel resistor R2 and the capacitor C2; The voltage input terminal 5 of the operational amplifier U3 is connected to the power supply VCC, and the ground terminal 2 is grounded.

3. A dual-axis anti-seismic signal processing circuit for a vortex flowmeter according to claim 1 or 2, characterized in that: The output terminal S1 of the charge amplifier circuit 1 is connected to the inverting input terminal 4 of the operational amplifier U4 through the capacitor C7; The output terminal S2 of the charge amplifier circuit 2 is connected to the in-phase input terminal 3 of the operational amplifier U4 through the capacitor C9; The connection line between the output terminal S1 of the charge amplifier circuit 1 and the capacitor C7 is connected to the connection line between the output terminal S2 of the charge amplifier circuit 2 and the capacitor C9 through the resistor R4; The connection line between the capacitor C9 and the in-phase input terminal 3 of the operational amplifier U4 is connected to the power supply VCC / 2 through the parallel resistor R6 and the capacitor C10; The voltage input terminal 5 of the operational amplifier U4 is connected to the power supply VCC, and the ground terminal 2 is grounded; The connection line between the capacitor C7 and the inverting input terminal 4 of the operational amplifier U4 is connected to the output terminal 1 of the operational amplifier U4 through the parallel resistor R7 and the capacitor C11, forming the output terminal of the differential amplifier circuit 1; The output terminal S3 of the charge amplifier circuit 3 is connected to the in-phase input terminal 3 of the operational amplifier U6 through the capacitor C13; The output end of the differential amplifier circuit 1 is connected to the inverting input end 4 of the operational amplifier U6 via the capacitor C22; The connection line between the output terminal S3 of the charge amplifier circuit 3 and the capacitor C13 is connected to the connection line between the output terminal of the differential amplifier circuit 1 and the capacitor C22 through the resistor R10; The connection line between the capacitor C22 and the inverting input terminal 4 of the operational amplifier U6 is connected to the output terminal 1 of the operational amplifier U6 through the parallel resistor R8 and the capacitor C8, forming the output terminal S4 of the differential amplifier circuit 2; The connection line between the capacitor C13 and the in-phase input terminal 3 of the operational amplifier U6 is connected to the power supply VCC / 2 through the parallel resistor R9 and the capacitor C12; The voltage input terminal 5 of the operational amplifier U6 is connected to the power supply VCC, and the ground terminal 2 is grounded.

4. A dual-axis anti-seismic signal processing circuit for a vortex flowmeter according to claim 3, characterized in that: The output terminal S4 of the differential amplifier circuit 2 is connected to the in-phase input terminal 3 of the operational amplifier U2 through the resistor R14; The connection line between the resistor R14 and the in-phase input terminal 3 of the operational amplifier U2 is connected to the power supply VCC / 2 through the capacitor C5; The voltage input terminal 5 of the operational amplifier U2 is connected to the power supply VCC, and the ground terminal 2 is grounded; The inverting input terminal 4 of the operational amplifier U2 is connected to the output terminal 1 of the operational amplifier U2 through a resistor R15 and a capacitor C14 connected in parallel, forming an output terminal S5 of the adjustable gain amplifier circuit; The inverting input terminal 4 of the operational amplifier U2 is also connected to the output terminals 3 of the electronic analog switches SW5, SW6, SW7 and SW8 respectively through the resistors R16, R17, R24 and R25; The control terminals 4 of the electronic analog switches SW5, SW6, SW7 and SW8 are connected to the IO interfaces 1, 2, 3 and 4 of the CPU respectively; The voltage input terminals 2 of the electronic analog switches SW5, SW6, SW7 and SW8 are all connected to the power supply VCC / 2.

5. A dual-axis anti-seismic signal processing circuit for a vortex flowmeter according to claim 4, characterized in that: The output terminal S5 of the adjustable gain amplifier circuit is connected to the in-phase input terminal 3 of the operational amplifier U20 through the resistor R11; The voltage input terminal 5 of the operational amplifier U20 is connected to the power supply VCC, and the ground terminal 2 is grounded; The inverting input terminal 4 of the operational amplifier U20 is grounded through a resistor R65 and a capacitor C52 connected in parallel, and is connected to a power source VCC through a resistor R63; The output terminal 1 of the operational amplifier U20 outputs a signal S6.

Images