Semiconductor device

Abstract

A semiconductor device includes a first transistor, a second transistor, an interlayer dielectric layer, and a back side gate track. The first transistor and the second transistor are arranged in a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, and a first source / drain epitaxial structure and a second source / drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, a gate structure surrounding the second channel layer, and a third source / drain epitaxial structure and a fourth source / drain epitaxial structure connected to the second channel layer. A portion of the interlayer dielectric layer is sandwiched between the first and third source / drain epitaxial structures. The back side gate track is under the interlayer dielectric layer and is electrically connected to the gate structure. A portion of the interlayer dielectric layer is directly over the back side gate track.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) has decreased. This process of scaling down can improve production efficiency and reduce associated costs. Such scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. Utility Model Content

[0003] According to some embodiments, a semiconductor device includes a first transistor, a second transistor, an interlayer dielectric layer, and a backside gate track. The first transistor and the second transistor are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source / drain epitaxial structure connected to the first channel layer, and a second source / drain epitaxial structure. The second transistor includes a second channel layer, a gate structure surrounding the second channel layer, a third source / drain epitaxial structure connected to the second channel layer, and a fourth source / drain epitaxial structure. The interlayer dielectric layer surrounds the first transistor and the second transistor. A portion of the interlayer dielectric layer is sandwiched between the first source / drain epitaxial structure and the third source / drain epitaxial structure. The backside gate track is below the interlayer dielectric layer and is electrically connected to the gate structure. The portion of the interlayer dielectric layer sandwiched between the first source / drain epitaxial structure and the third source / drain epitaxial structure is directly above the backside gate track.

[0004] According to some embodiments, a semiconductor device includes a transistor array and a backside gate track. The transistor array includes a first portion and a second portion. The first portion includes a plurality of first transistors arranged in a first direction in a top view. The second portion includes a plurality of second transistors arranged in the first direction in a top view. The first portion and the second portion are arranged in a second direction different from the first direction in a top view. The backside gate track is below the transistor array and electrically connected to a plurality of gate structures of the first transistors. The backside gate track extends in the first direction and between the first portion and the second portion of the transistor array in a top view.

[0005] According to some embodiments, a semiconductor device includes a first transistor, a second transistor, a backside gate track and a backside gate via. The first transistor and the second transistor are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source / drain epitaxial structure connected to the first channel layer, and a second source / drain epitaxial structure. The second transistor includes a second channel layer, a gate structure surrounding the second channel layer, a third source / drain epitaxial structure connected to the second channel layer, and a fourth source / drain epitaxial structure. The backside gate track is below the first transistor and the second transistor and electrically connected to the gate structure, wherein the backside gate track extends in a second direction different from the first direction. The backside gate via is between the gate structure and the backside gate track, wherein the backside gate track is electrically connected to the gate structure via the backside gate via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some aspects of the present disclosure are described in the accompanying Figure 1 The following detailed description is best understood when read together. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 15E A method of manufacturing a semiconductor device (or integrated circuit structure) at various stages according to some embodiments of the present disclosure is illustrated;

[0008] FIG. 16A to FIG. 16D depicts a method of manufacturing an interconnect structure at various stages according to some embodiments of the present disclosure;

[0009] Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A depicts simplified cross-sectional views of epitaxial layers, gate structures, gate conductive lines, backside gate vias, and backside gate tracks according to some embodiments of the present disclosure;

[0010] Fig. 17B , Fig.18B , Fig.19B , Fig. 20B and Fig.21B A simplified top view of an epitaxial layer, a gate structure, a gate conductive line, a backside gate via, and a backside gate track according to some embodiments of the present disclosure is shown;

[0011] Fig. 22 and Fig.23 is a performance comparison of semiconductor devices including different numbers of backside gate tracks;

[0012] Figures 24 to 25BA method of manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown.

[0013]

Explanation of symbols

[0014] 100:Semiconductor device

[0015] 100':Semiconductor Devices

[0016] 102: Installation area

[0017] 104: Surrounding area

[0018] 106: Groove

[0019] 110:Substrate

[0020] 112: base part

[0021] 120: Epitaxial stacking

[0022] 122,124: Epitaxial layer

[0023] 130a, 130b: Fin structure

[0024] 140: Isolation Structure

[0025] 150: Back side gate through hole

[0026] 160: dummy gate structure

[0027] 162: dummy gate dielectric layer

[0028] 164: dummy gate electrode layer

[0029] 166: Hard Mask

[0030] 170: Gate spacer

[0031] 180: Internal spacer

[0032] 190:Metal alloy layer

[0033] 210: First ILD layer

[0034] 220: Gate structure

[0035] 222: Gate dielectric layer

[0036] 224: Work function metal layer

[0037] 226: Filler Metal

[0038] 230: Second ILD layer

[0039] 240: Gate conductive wire

[0040] 250a, 250b: Source / drain contacts

[0041] 255a, 255b: Source / drain contacts

[0042] 260: Third ILD layer

[0043] 272:Front side gate through hole

[0044] 274: Source / Drain Via

[0045] 276:Through hole

[0046] 280: Fourth ILD layer

[0047] 290: first gate trace

[0048] 310: First source / drain trace

[0049] 315: First source / drain trace

[0050] 320: Interconnection structure

[0051] 322,324,326:Through hole

[0052] 332: Second gate trace

[0053] 334,336: Second source / drain trace

[0054] 342,344:Through hole

[0055] 352,354: Third source / drain trace

[0056] 360: Fifth ILD layer

[0057] 370: Rear gate track

[0058] 910: Hard mask layer

[0059] CH: Channel area

[0060] D1: Dimension

[0061] D2,D3: Distance

[0062] Da, Db, Dc, Dd, De, Df: epitaxial structure

[0063] GT1, GT2, GT3: Gate trench

[0064] L1, L2, L3, L4: Length

[0065] O1, O2, O3: Open

[0066] R1: Groove

[0067] Sa, Sb, Sc, Sd, Se, Sf: epitaxial structure

[0068] S / D: Source / Drain region

[0069] TR: Transistor Array

[0070] TRa: Part 1

[0071] TRb: Part 2

[0072] W1,W2,W3,W4: Width

[0073] X,Y,Z: axis

[0074] II,II-II,III-III,IV-IV: Tangent DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify some embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, some embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0076] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used in some embodiments of the present disclosure to describe the relationship of one element or feature to another element or feature(s) depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure may be similarly interpreted accordingly.

[0077] As used in some embodiments of the present disclosure, "approximately," "about," "approximately," or "substantially" shall generally refer to within 20%, 10%, or 5% of a given value or range. In some embodiments of the present disclosure, the quantities given are approximate, meaning that the terms "approximately," "about," "approximately," or "substantially" can be inferred if not explicitly stated. One of ordinary skill in the art will understand that dimensions may vary according to different technology nodes. One of ordinary skill in the art will recognize that dimensions depend on the specific device type, technology generation, minimum feature size, and the like. Therefore, the term should be interpreted in accordance with the technology being evaluated.

[0078] As used in some embodiments of the present disclosure, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO2 (e.g., greater than 3.9). As used in some embodiments of the present disclosure, the term "low-k" refers to a low dielectric constant. In the field of semiconductor device structures and manufacturing processes, low-k refers to a dielectric constant that is less than the dielectric constant of SiO2 (e.g., less than 3.9). As used in some embodiments of the present disclosure, the term "p-type" defines a structure, layer and / or region doped with a p-type dopant (such as boron). As used in some embodiments of the present disclosure, the term "n-type" defines a structure, layer and / or region doped with an n-type dopant (such as phosphorus). As used in some embodiments of the present disclosure, the term "conductive" refers to a conductive structure, layer and / or region. As used in some embodiments of the present disclosure, a source / drain region may refer to a source or a drain, individually or collectively depending on the context.

[0079] Nanostructure transistor (e.g., gate all around (GAA) transistor) structures can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing the production of patterns with, for example, a smaller pitch than can be obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0080] Some embodiments of the present disclosure are directed to semiconductor devices and methods of forming the same. More specifically, some embodiments of the present disclosure are directed to radio frequency (RF) devices that include one or more buried gate conductive lines to reduce gate resistance without increasing parasitic capacitance of the device. In some embodiments, the RF device is a planar metal-oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), and / or a nanostructure (e.g., a nanosheet device, a nanowire device, or the like).

[0081] Figures 1 to 15E A method of manufacturing a semiconductor device (or integrated circuit structure) 100 at various stages according to some embodiments of the present disclosure is illustrated. In addition to the semiconductor device 100, Figures 1 to 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A Also depicted are axis X, axis Y, and axis Z directions. In some embodiments, Figures 1 to 15E The semiconductor device shown in the figure may be an intermediate device manufactured during the processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors and inductors and / or active components such as p-type FET (PFET), n-type FET (NFET), multi-gate FET, MOSFET, complementary metal-oxide semiconductor (CMOS) transistor, bipolar transistor, high-voltage transistor, high-frequency transistor, other memory cells and combinations thereof.

[0082] Figures 1 to 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A is a perspective view of some embodiments of semiconductor device 100 at an intermediate stage during fabrication. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10A , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B is a cross-sectional view of some embodiments of the semiconductor device 100 at an intermediate stage during fabrication along a first cut line (eg, cut line II), the first cut line being along a longitudinal direction of the gate structure. Figure 4C , Figure 5C , Figure 6C , Fig.9D , Fig. 10C , Fig.11D , Fig.12D , Fig.13D , Fig.14D and Fig.15D is a cross-sectional view of some embodiments of the semiconductor device 100 at an intermediate stage during the manufacturing along a second cut line (eg, cut line II-II), the second cut line being along a longitudinal direction of the buried gate conductive line. Fig.6D , Fig.7D , Fig.8D , Fig.9E , Fig. 10D , Fig.11E , Fig.12E , Fig.13E , Fig.14E and Fig.15E is a cross-sectional view of some embodiments of the semiconductor device 100 at an intermediate stage during fabrication along a third tangent line (eg, tangent line III-III), the third tangent line being along a longitudinal direction of the channel. Figure 7C , Figure 8C , Fig. 9C , Fig. 10B , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C and Fig. 15C is a cross-sectional view of some embodiments of the semiconductor device 100 at an intermediate stage during the manufacturing process along a fourth cutting line (eg, cutting line IV-IV), the fourth cutting line being along a longitudinal direction of the source / drain epitaxial structure.

[0083] refer to Figure 1A substrate 110 is provided. The substrate 110 includes a device region 102 and a peripheral region 104. In some embodiments, the substrate 110 is made of: a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide); or the like. In addition, the substrate 110 may include an epitaxial layer (epi layer), which may apply strain to enhance performance, and / or may include a silicon-on-insulator (SOI) structure.

[0084] An epitaxial stack 120 is formed on a substrate 110 via epitaxy so that the epitaxial stack 120 forms a crystalline layer. The epitaxial stack 120 includes an epitaxial layer 122 of a first composition inserted by an epitaxial layer 124 of a second composition. The first and second compositions may be different. In some embodiments, the epitaxial layer 122 is SiGe and the epitaxial layer 124 is silicon (Si). However, other embodiments are possible, including those providing first and second compositions with different etching selectivities.

[0085] The epitaxial layer 124 or a portion thereof may form a nanostructure channel of a nanostructure transistor. The term nanostructure is used in some embodiments of the present disclosure to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions of circular and substantially circular cross-sections, and includes beam-shaped or strip-shaped material portions of, for example, cylindrical or substantially rectangular cross-sections. For example, a nanostructure is a nanosheet, a nanowire, a nanoplate, or a nanoring, depending on its geometry. The use of the epitaxial layer 124 to define one or more channels of a device is discussed further below.

[0086] It should be noted that the three layers of epitaxial layers 122 and the three layers of epitaxial layers 124 are arranged alternately, such as Figure 1 , which is for illustrative purposes only and is not intended to limit the specific contents listed in the scope of the patent application. It is understood that any number of epitaxial layers can be formed in the epitaxial stack 120; the number of layers depends on the desired number of channel regions of the transistor. In some embodiments, the number of epitaxial layers 124 is between 2 and 10.

[0087] As described in more detail below, the epitaxial layer 124 can be used as a channel region of a subsequently formed semiconductor device, and the thickness is selected based on device performance considerations. The epitaxial layer 122 in the channel region can eventually be removed and used to define the vertical distance between adjacent channel regions of a subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. Therefore, the epitaxial layer 122 can also be called a sacrificial layer, and the epitaxial layer 124 can also be called a channel layer.

[0088] refer to Figure 2 , a plurality of fin structures 130a and a plurality of fin structures 130a-130b are formed extending from the device region 102 of the substrate 110. In various embodiments, each of the fin structures 130a and the fin structures 130b includes a portion of each of the epitaxial layers of the epitaxial stack 120 including the epitaxial layer 122 and the epitaxial layer 124 formed from the base portion 112 of the substrate 110. The fin structures 130a and the fin structures 130b can be manufactured using a suitable process including a double patterning process or a multiple patterning process. Figure 2 As shown in , the fin structure 130a and the fin structure 130b may have different pitches. For example, the distance between adjacent fin structures 130a and 130b is greater than the pitch of the fin structure 130a and also greater than the pitch of the fin structure 130b. In some embodiments, the length L1 of each of the fin structure 130a and the fin structure 130b is in the range of about 10 nanometers (nm) to about 200 micrometers (μm), and the width W1 of the fin structure 130a and the fin structure 130b is in the range of about 10nm to about 200μm.

[0089] exist Figure 1 and Figure 2 In the embodiment shown in , a patterned hard mask (HM) layer 910 is formed over the epitaxial stack 120 before patterning the fin structures 130a and 130b. The hard mask layer 910 is then used to protect areas of the substrate 110 and the layers formed thereon while an etching process forms trenches 106 through the hard mask layer 910, through the epitaxial stack 120, and into the substrate 110 in unprotected areas, leaving a plurality of extended fin structures 130a and 130b. The trenches 106 may be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof.

[0090] Next, if Figure 3 As shown in FIG. 1 , in the groove 106 (see Figure 2) and forming an isolation structure 140 around the bottom portion of the fin structure 130a and the fin structure 130b. The isolation structure 140 may include a liner oxide (not shown). The liner oxide may be formed by a thermal oxide formed by thermal oxidation of a surface layer of the substrate 110. The liner oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The isolation structure 140 may also include a dielectric material above the liner oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like. The isolation structure 140 is then recessed so that the top portions of the fin structure 130a and the fin structure 130b protrude higher than the top surface of the adjacent isolation structure 140, thereby forming a protruding fin.

[0091] refer to FIG. 4A to FIG. 4C ,in Figure 4B It is along Figure 4A The cross-sectional view taken along the tangent line II in Figure 4C It is along Figure 4A 1. A cross-sectional view taken along the line II-II in FIG. After forming the isolation structure 140, a gate through hole opening O1 is formed in the isolation structure 140 and between the fin structure 130a and the fin structure 130b. For example, the gate through hole opening O1 passes through the isolation structure 140 and exposes the substrate 110. The gate through hole opening O1 may be formed by using a single or multiple etching processes.

[0092] refer to FIG. 5A to FIG. 5C ,in Figure 5B It is along Figure 5A The cross-sectional view taken along the tangent line II in Figure 5C It is along Figure 5A The cross-sectional view taken along the line II-II in FIG. Figure 4B and Figure 4C) and between the fin structure 130a and the fin structure 130b. Forming the backside gate via 150 includes depositing one or more metal materials to overfill the gate via opening O1, and then performing an etch-back process to remove excess metal material outside the gate via opening O1. The backside gate via 150 may include a metal material such as Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, and combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the backside gate via 150 may further include one or more barrier / adhesion layers (not shown) to protect the isolation structure 140 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, a dimension (length or width or diameter) D1 of the backside gate via 150 is in a range from about 10 nm to about 500 nm.

[0093] refer to FIG. 6A to FIG. 6D ,in Figure 6B It is along Fig. 6A The cross-sectional view taken along the tangent line II in Figure 6C It is along Fig. 6A The cross-sectional view is taken along the tangent line II-II in Fig.6D It is along Fig. 6A . A dummy gate structure 160 is formed above the substrate 110 and is at least partially disposed above the fin structure 130a and the fin structure 130b. The portion of the dummy gate structure 160 underlying the fin structure 130a and the fin structure 130b may be referred to as a channel region CH. The dummy gate structure 160 may also define a source / drain (S / D) region S / D of the fin structures 130a and 130b, for example, a region of the fin structures 130a and 130b that is adjacent to the channel region CH and on an opposite side of the channel region CH. In addition, as Figure 6C As shown in FIG. 1 , the dummy gate structure 160 covers the backside gate via 150 .

[0094] The dummy gate formation operation first forms a dummy gate dielectric layer 162 over the fin structure 130a and the fin structure 130b and the backside gate through hole 150. Subsequently, a dummy gate electrode layer 164 and a hard mask 166 are formed over the dummy gate dielectric layer 162. The hard mask 166 is then patterned, and then the dummy gate electrode layer 164 is patterned by using the patterned hard mask 166 as an etching mask. In some embodiments, after the dummy gate electrode layer 164 is patterned, the dummy gate dielectric layer 162 is removed from the source / drain regions S / D of the fin structure 130a and the fin structure 130b. The etching process may include wet etching, dry etching, and / or a combination thereof. The etching process is selected to selectively etch the dummy gate dielectric layer 162 without substantially etching the fin structure 130a and the fin structure 130b, the dummy gate electrode layer 164, and the hard mask 166.

[0095] After the formation of the dummy gate structure 160 is completed, a gate spacer 170 is formed on the sidewall of the dummy gate structure 160. The gate spacer 170 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film and / or a combination thereof. For example, the gate spacer 170 may be formed by depositing a dielectric material over the dummy gate structure 160 using a suitable deposition process. An anisotropic etching process is then performed on the deposited spacer material layer to expose portions of the fin structure 130a and the fin structure 130b that are not covered by the dummy gate structure 160 (e.g., in the source / drain regions of the fin structure 130a and the fin structure 130b). The portion of the spacer material layer directly over the dummy gate structure 160 may be completely removed by this anisotropic etching process. Portions of the spacer material layer on the sidewalls of the dummy gate structure 160 may remain, forming gate sidewall spacers, which are denoted as gate spacers 170 for simplicity.

[0096] refer to FIG. 7A to FIG. 7D ,in Figure 7B It is along Fig. 7A The cross-sectional view taken along the tangent line II, Figure 7C It is along Fig. 7A The cross-sectional view is taken along the tangent line IV-IV of Fig.7D It is along Fig. 7ANext, the exposed portions of the fin structures 130a and 130b that laterally extend beyond the gate spacer 170 (e.g., in the source / drain regions S / D of the fin structures 130b and 130a) are etched by, for example, an anisotropic etching process using the dummy gate structure 160 and the gate spacer 170 as an etching mask, thereby generating recesses R1 in the fin structures 130a and 130b and between the corresponding dummy gate structures 160. After the anisotropic etching, the end surfaces of the epitaxial layer 122 and the epitaxial layer (or channel layer) 124 are substantially coterminal with the respective outermost sidewalls of the gate spacer 170 due to the anisotropic etching.

[0097] Subsequently, by using a suitable etching technique, the epitaxial layer 122 is laterally or horizontally recessed, thereby producing each vertical lateral groove between the corresponding epitaxial layer (or channel layer) 124. This operation can be performed by using a selective etching process. As an example and not limitation, the epitaxial layer 122 is SiGe and the epitaxial layer (or channel layer) 124 is silicon, thereby allowing selective etching of the epitaxial layer 122. As a result, the epitaxial layer (or channel layer) 124 extends laterally through the opposite end surfaces of the epitaxial layer 122.

[0098] Inner spacers 180 are formed in the grooves, respectively. For example, a dielectric material layer is formed over the substrate 110, and one or more etching operations are performed to form the inner spacers 180. In some embodiments, the inner spacers 180 include a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof, and are different from the material of the gate spacers 170. In some embodiments, the inner spacers 180 are silicon nitride. The inner spacers 180 may completely fill the grooves. The dielectric material layer may be formed using CVD including PECVD, PEALD, ALD, or other suitable processes. The etching operation includes one or more wet and / or dry etching operations. In some embodiments, the etching is an isotropic etching.

[0099] refer to FIG. 8A to FIG. 8D ,in Figure 8B It is along Fig. 8A The cross-sectional view taken along the tangent line II, Figure 8C It is along Fig. 8A The cross-sectional view is taken along the tangent line IV-IV of Fig.8D It is along the Fig. 8A The source / drain epitaxial structure Sa and the source / drain epitaxial structure Da are formed in the source / drain region S / D of the fin structure 130a (see Figure 5A ), the source / drain epitaxial structure Sb and the source / drain epitaxial structure Db are formed on the source / drain region S / D of the fin structure 130b (see Figure 5A The source / drain epitaxial structure Sa is spaced apart from the source / drain epitaxial structure Sb by a distance D2, and the source / drain epitaxial structure Da is spaced apart from the source / drain epitaxial structure Db by a distance D2.

[0100] The source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db may be formed by performing an epitaxial growth process of providing epitaxial material on the fin structure 130a and the fin structure 130b. During the epitaxial growth process, the dummy gate structure 160, the gate spacer 170, and the inner spacer 180 confine the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db to the source / drain region S / D. In some embodiments, the lattice constants of the epitaxial structure Sa, the epitaxial structure Sb, the epitaxial structure Da, and the epitaxial structure Db are different from the lattice constant of the epitaxial layer 124, so that the epitaxial layer 124 may be strained or stressed by the epitaxial structure Sa, the epitaxial structure Sb, the epitaxial structure Da, and the epitaxial structure Db, thereby improving the carrier mobility of the semiconductor device and enhancing the device performance. The epitaxial process includes CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the epitaxial layer 124.

[0101] In some embodiments, the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db may be in-situ doped by introducing doping species during the epitaxial process, and the doping species include: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. If the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db are ex-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db. In some exemplary embodiments, the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db in the n-type transistor include SiP, and the source / drain epitaxial structure in the p-type transistor includes GeSnB and / or SiGeSnB.

[0102] refer to 9A to 9E ,in Fig. 9B It is along Fig. 9A The cross-sectional view taken along the tangent line II in Fig. 9C It is along Fig. 9A The cross-sectional view taken along the tangent line IV-IV in Fig.9D It is along Fig. 9A The cross-sectional view is taken along the tangent line II-II in Fig.9E It is along Fig. 9A A first interlayer dielectric (ILD) layer 210 is formed on the substrate 110. For clarity, the first interlayer dielectric (ILD) layer 210 is formed on the substrate 110. Fig. 9Adenoted by dashed lines. In some embodiments, a contact etch stop layer (CESL) is also formed before forming the first ILD layer 210. In some examples, the CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having different etching selectivities from the first ILD layer 210. The CESL may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the first ILD layer 210 includes an oxide formed by tetraethyl orthosilicate (TEOS), undoped silicon glass, or a doped silicon oxide material such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials having different etching selectivities from the CESL. The first ILD layer 210 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the first ILD layer 210 , the wafer may be subjected to a high thermal budget process to anneal the first ILD layer 210 .

[0103] In some examples, after depositing the first ILD layer 210, a planarization process may be performed to remove excess material of the first ILD layer 210. For example, the planarization process includes a chemical mechanical planarization (CMP) process that removes portions of the first ILD layer 210 (and the CESL layer, if present) covering the dummy gate structure 160 and planarizes the top surface of the semiconductor device 100. In some embodiments, the CMP process also removes the hard mask 166 (e.g., Fig. 8A , Figure 8B and Fig.8D ) and expose the dummy gate electrode layer 164.

[0104] Thereafter, the dummy gate structure 160 (eg, Fig. 8A , Figure 8B and Fig.8D ), and then remove the epitaxial layer (ie, sacrificial layer) 122 (as shown in Figure 8B and Fig.8D). In some embodiments, the dummy gate structure 160 is removed by using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), and the selective etching process etches the material in the dummy gate structure 160 at a faster etching rate than etching other materials (e.g., the gate spacers 170 and / or the first ILD layer 210), thereby generating a gate trench GT1 between the corresponding gate spacers 170, and the epitaxial layer 122 is exposed in the gate trench GT1. Subsequently, the epitaxial layer 122 in the gate trench GT1 is removed by using another selective etching process, and the selective etching process etches the epitaxial layer 122 at a faster etching rate than etching the epitaxial layer (or channel layer) 124, thereby forming an opening between adjacent epitaxial layers (i.e., channel layers) 124. In this way, the epitaxial layer 124 becomes a nanosheet suspended above the substrate 110 and between the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db. This operation is also called a channel release process. In some embodiments, the epitaxial layer 124 can be interchangeably referred to as a nanostructure (nanowire, nanoplate and nanoring, nanosheet, etc., depending on its geometry). For example, in some other embodiments, due to the selective etching process for completely removing the epitaxial layer 122, the epitaxial layer 124 can be trimmed to have a substantially circular shape (i.e., a cylindrical shape). In this case, the resulting epitaxial layer 124 can be referred to as a nanowire. In some other embodiments, the epitaxial layer 124 has an elliptical or diamond cross-sectional shape.

[0105] Thereafter, a gate dielectric layer 222 is formed to line the gate trench GT1. The gate dielectric layer 222 covers the backside gate via 150 in the gate trench GT1. The gate dielectric layer 222 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer above the interface layer. As used and described in some embodiments of the present disclosure, the high-k gate dielectric includes a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (~3.9). In some embodiments, the interface layer of the gate dielectric layer 222 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 222 may include hafnium oxide (HfO2). In addition, the gate dielectric layer 222 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof.

[0106] refer to FIG. 10A to FIG. 10D .right Fig. 9A The structure of FIG. 1 is patterned so that the portion of the gate dielectric layer 222 covering the top surface of the backside gate through hole 150 is removed. Fig. 10A and Fig. 10C For example, in Fig. 9A A patterned mask layer is formed over the structure of . The patterned mask layer exposes portions of the gate dielectric layer 222 that cover the top surface of the backside gate via 150. Subsequently, an etching process is performed to remove these portions of the gate dielectric layer 222 so that the top surface of the backside gate via 150 is exposed. The patterned mask layer is removed after the etching process.

[0107] refer to FIG. 11A to FIG. 11E ,in Fig. 11B It is along Fig.11A The cross-sectional view taken along the tangent line II in Fig. 11C It is along Fig.11A The cross-sectional view taken along the tangent line IV-IV in Fig.11DIt is along Fig.11A The cross-sectional view is taken along the tangent line II-II in Fig.11E It is along Fig.11A . A gate electrode (including a work function metal layer 224 and a filling metal 226) is formed in the gate trench GT1 to form a gate structure 220. The gate structure 220 may be the final gate of the GAA-FET. The formation of the gate structure 220 may include multiple deposition processes for forming various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material.

[0108] The work function metal layer 224 may include a work function metal to provide a suitable work function for the gate structure 220. For n-type FETs, the work function metal layer 224 may include one or more n-type work function metals (N metals). The n-type work function metals may illustratively include, but are not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for p-type FETs, the work function metal layer 224 may include one or more p-type work function metals (P metals). The p-type work function metal may illustratively include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0109] In some embodiments, the fill metal 226 may illustratively include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0110] refer to FIG. 12A to FIG. 12E ,in Fig. 12B It is along Fig. 12A The cross-sectional view taken along the tangent line II in Fig. 12C It is along Fig. 12A The cross-sectional view taken along the tangent line IV-IV in Fig.12D It is along Fig. 12A The cross-sectional view taken along the tangent line II-II in Fig.12E It is along Fig. 12A A second ILD layer 230 is formed on the substrate 110. For clarity, the second ILD layer 230 is formed on the substrate 110. Fig. 12AIn some embodiments, the second ILD layer 230 includes an oxide formed by tetraethyl orthosilicate (TEOS), undoped silica glass, or a doped silicon oxide material such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The second ILD layer 230 can be deposited by a PECVD process or other suitable deposition techniques.

[0111] Subsequently, the second ILD layer 230 is patterned to form source / drain contact openings O2 extending downward through the second ILD layer 230 and the first ILD layer 210 to reach the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db. Next, a metal alloy layer 190 is formed on the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db, respectively. The metal alloy layer 190, which is a silicide layer, is formed in the source / drain contact openings O2 and on the exposed source / drain epitaxial structures Sa, Sb, Da, and Db, respectively, by a self-aligned silicide (self-aligned polysilicide) process. The silicide process converts the surface portions of the source / drain epitaxial structures Sa, Sb, Da, and Db into silicide contacts. The silicide process involves the deposition of a metal that undergoes a silicidation reaction with silicon (Si). To form silicide contacts on the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db, a metal material is blanket deposited on the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db. After the wafer is heated to a temperature at which the metal reacts with the silicon of the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db to form contacts, the unreacted metal is removed. The silicide contacts remain above the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db, while the unreacted metal is removed from other areas. The silicide layer may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, erbium silicide, palladium silicide, combinations thereof, or other suitable materials. In some embodiments, the metal alloy layer 190 may include germanium.

[0112] Source / drain contacts 250a, 250b, 255a, and 255b are formed to fill the source / drain contact opening O2. Source / drain contact 250a is electrically connected to source / drain epitaxial structure Sa, source / drain contact 250b is electrically connected to source / drain epitaxial structure Sb, source / drain contact 255a is electrically connected to source / drain epitaxial structure Da, and source / drain contact 255b is electrically connected to source / drain epitaxial structure Db. Source / drain contact 250a is spaced apart from source / drain contact 250b by a distance D3, and source / drain contact 255a is spaced apart from source / drain contact 255b by a distance D3.

[0113] After forming the source / drain contacts 250a, 250b, 255a, and 255b, a transistor array TR is formed over the substrate 110. The transistor array TR includes a first portion TRa and a second portion TRb arranged along the Y direction. Each of the first portion TRa and the second portion TRb includes at least one transistor. For example, Fig. 12A In the embodiment, each of the first portion TRa and the second portion TRb includes four transistors arranged along the X direction.

[0114] The second ILD layer 230 is further patterned to form a gate trench GT2 extending downward to the gate structure 220. The second ILD layer 230 can be patterned by using suitable optical lithography and etching techniques. A gate conductive line 240 is formed to fill the gate trench GT2. The gate conductive line 240 is above the transistor array TR and electrically and physically interconnects the gate structure 220.

[0115] The source / drain contact 250a, the source / drain contact 250b, the source / drain contact 255a and the source / drain contact 255b, and the gate conductive line 240 are formed by using the following (example and not limitation) steps: depositing a metal material to overfill the source / drain contact opening O2 or the gate trench GT2, followed by a CMP process to remove the excess metal material outside the source / drain contact opening O2 or the gate trench GT2. As a result of the CMP process, the source / drain contact 250a, the source / drain contact 250b, the source / drain contact 255a and the source / drain contact 255b, and the gate conductive line 240 have a top surface that is substantially coplanar with the second ILD layer 230. The source / drain contacts 250a, 250b, 255a, 255b, and the gate conductive line 240 may include a metal material such as Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the source / drain contacts 250a, 250b, 255a, 255b, and the gate conductive line 240 may further include one or more barrier / adhesion layers (not shown) to protect the second ILD layer 230 (and the first ILD layer 210) from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like.

[0116] refer to FIG. 13A to FIG. 13E ,in Fig. 13B It is along Fig.13A The cross-sectional view taken along the tangent line II in Fig. 13C It is along Fig.13A The cross-sectional view taken along the tangent line IV-IV in Fig.13D It is along Fig.13A The cross-sectional view is taken along the tangent line II-II in Fig.13E It is along Fig.13A A third ILD layer 260 is formed on the substrate 110. For clarity, the third ILD layer 260 is formed on the substrate 110. Fig.13A The materials, configurations, dimensions, processes and / or operations associated with the third ILD layer 260 are shown in dashed lines. Fig. 12A The second ILD layer 230 is similar or identical to the second ILD layer 230 .

[0117] Subsequently, a front side gate via 272 and a source / drain via 274 are formed in the third ILD layer 260. Fig.13A and Fig.13DAs shown in FIG. 1 , at least one through-hole 276 is formed, which extends downward through the third ILD layer 260, the second ILD layer 230, the first ILD layer 210, and the isolation structure 140 to the peripheral region 104 of the substrate 110. The front side gate through-hole 272, the source / drain through-hole 274, and the through-hole 276 are formed using the following (example and not limitation) steps: etching the third ILD layer 260 (as well as the second ILD layer 230, the first ILD layer 210, and the isolation structure 140) to form an opening therein, depositing one or more metal materials to overfill the opening, and then performing a CMP process to remove excess metal materials outside the opening. As a result of the CMP process, the front side gate through-hole 272, the source / drain through-hole 274, and the through-hole 276 have a top surface that is substantially coplanar with the third ILD layer 260. The front side gate via 272 is electrically and physically connected to the gate conductive line 240, and the source / drain via 274 is electrically and physically connected to the source / drain contact 250a or the source / drain contact 250b. The front side gate via 272, the source / drain via 274, and the through hole 276 may include a metal material such as Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, and combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the front side gate via 272, the source / drain via 274, and the through hole 276 may further include one or more barrier / adhesion layers (not shown) to protect the third ILD layer 260 (as well as the second ILD layer 230, the first ILD layer 210, and the isolation structure 140) from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like.

[0118] refer to FIG. 14A to FIG. 14E ,in Fig. 14B It is along Fig.14A The cross-sectional view taken along the tangent line II in Fig. 14C It is along Fig.14A The cross-sectional view taken along the tangent line IV-IV in Fig.14D It is along Fig.14A The cross-sectional view is taken along the tangent line II-II in Fig.14E It is along Fig.14A A fourth ILD layer 280 is formed on the substrate 110. For clarity, the fourth ILD layer 280 is formed on the substrate 110. Fig.14A The materials, configurations, dimensions, processes and / or operations associated with the fourth ILD layer 280 are shown in dashed lines. Fig. 12A The second ILD layer 230 is similar or identical to the second ILD layer 230 .

[0119] Subsequently, a first gate trace 290 and first source / drain traces 310 and 315 are formed in the fourth ILD layer 280 and over the transistor array TR (see FIG. Fig. 12A ). The first gate trace 290 interconnects the front side gate via 272 and the through hole 276 and is electrically connected to the gate structure 220. The first source / drain trace 310 interconnects some of the source / drain vias 274 and is electrically connected to the source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb. The first source / drain trace 315 interconnects some of the source / drain vias 274 and is electrically connected to the source / drain epitaxial structure Da and the source / drain epitaxial structure Db. In some embodiments, each of the first source / drain trace 310 and the first source / drain trace 315 has a length L2 in the range of about 10 nm to about 200 μm and a width W2 in the range of about 10 nm to about 500 nm.

[0120] The first gate trace 290 and the first source / drain traces 310 and 315 are formed using the following (by way of example and not limitation): etching the fourth ILD layer 280 to form trenches therein, depositing one or more metal materials to overfill the openings, and then performing a CMP process to remove excess metal materials outside the openings. As a result of the CMP process, the first gate trace 290 and the first source / drain traces 310 and 315 have top surfaces that are substantially coplanar with the fourth ILD layer 280. The first gate trace 290 and the first source / drain traces 310 and 315 may include metal materials such as Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the first gate trace 290 and the first source / drain traces 310 and 315 may further include one or more barrier / adhesion layers (not shown) to protect the fourth ILD layer 280 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like.

[0121] refer to FIG. 15A to FIG. 15E ,in Fig. 15B It is along Fig.15A The cross-sectional view taken along the tangent line II in Fig. 15C It is along Fig.15A The cross-sectional view taken along the tangent line IV-IV in Fig.15D It is along Fig.15A The cross-sectional view is taken along the tangent line II-II in Fig.15E It is along Fig.15A2. A cross-sectional view taken along the line III-III in FIG. 2. An interconnect structure 320 is formed over the fourth ILD layer 280. The design of the interconnect structure 320 may vary according to different circuit requirements.

[0122] Then, the substrate 110 and the base portion 112 are removed (see Fig.14A , Fig. 14B , Fig. 14C and Fig.14E ). In this way, the isolation structure 140, the backside gate via 150, and the through hole 276 are exposed. In some embodiments, the removal process includes thinning the substrate 110 from the back side of the substrate 110 until the isolation structure 140 is exposed. The base portion 112 is then removed by using a selective etching process that etches the base portion 112 at a faster etching rate than etching the isolation structure 140 (e.g., dielectric material). In some embodiments, the selective etching process for selectively removing the base portion 112 may be a wet etching process using a wet etching solution such as tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), NH4OH, the like, or a combination thereof.

[0123] Subsequently, a fifth ILD layer 360 is formed (for clarity, it is shown in FIG. Fig.15A The fifth ILD layer 360 is formed by a plurality of layers (indicated by dashed lines) to cover the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da and the source / drain epitaxial structure Db, the gate structure 220, the isolation structure 140, the backside gate via 150 and the back side of the through hole 276. The materials, configurations, dimensions, processes and / or operations related to the fifth ILD layer 360 are similar to those of FIG. Fig. 12A The second ILD layer 230 is similar or identical to the second ILD layer 230 .

[0124] Next, a backside gate track 370 is formed in the fifth ILD layer 360. The backside gate track 370 is electrically and physically connected to the backside gate via 150 and the through hole 276. Fig.15D , the through hole 276 extends from the first gate trace 290 to the backside gate track 370. The backside gate track 370 may include a metal material such as Pt, Ti, TiN, Al, W, WN, Ru, RuO, Ta, Ni, Co, Cu, Ag, Au, combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the backside gate track 370 may further include one or more barrier / adhesion layers (not shown) to protect the fifth ILD layer 360 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like.

[0125] Therefore, the semiconductor device 100 is FIG. 15A to FIG. 15E The semiconductor device 100 includes a transistor array TR (see Fig. 12A ), the backside gate track 370, the through hole 276 and the first gate trace 290. The transistor array TR includes a first portion TRa and a second portion TRb arranged along the Y direction. Each of the first portion TRa and the second portion TRb includes at least one transistor. For example, in Fig. 12A In the embodiment of the present invention, each of the first part TRa and the second part TRb includes four transistors. Each of the transistors in the first part TRa has an epitaxial layer 124, a gate structure 220 surrounding the epitaxial layer 124, a source / drain epitaxial structure Sa and a source / drain epitaxial structure Da connected to the epitaxial layer 124, and a source / drain contact 250a and a source / drain contact 255a respectively connected to the source / drain epitaxial structure Sa and the source / drain epitaxial structure Da. Each of the transistors in the second part TRb has an epitaxial layer 124, a gate structure 220 surrounding the epitaxial layer 124, a source / drain epitaxial structure Sb and a source / drain epitaxial structure Db connected to the epitaxial layer 124, and a source / drain contact 250b and a source / drain contact 255b respectively connected to the source / drain epitaxial structure Sb and the source / drain epitaxial structure Db.

[0126] The source / drain epitaxial structure Sa (or source / drain epitaxial structure Da) and the source / drain epitaxial structure Sb (or source / drain epitaxial structure Db) are separated by a distance D2. Similarly, the source / drain contact 250a (or source / drain contact 255a) and the source / drain contact 255b (or source / drain contact 255b) are substantially separated by a distance D3. The source / drain epitaxial structure Sa (or source / drain epitaxial structure Da) and the source / drain epitaxial structure Sb (or source / drain epitaxial structure Db) are arranged along the Y direction, and the source / drain contact 250a (or source / drain contact 255a) and the source / drain contact 255b (or source / drain contact 255b) are arranged along the Y direction.

[0127] The first ILD layer 210 surrounds the transistors of the transistor array TR. A portion 212 of the first ILD layer 210 is located in the middle of the adjacent source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb (or the source / drain epitaxial structure Da and the source / drain epitaxial structure Db), or is sandwiched between the adjacent source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb (or the source / drain epitaxial structure Da and the source / drain epitaxial structure Db). In other words, the source / drain epitaxial structure Sa (or the source / drain epitaxial structure Da), the portion 212 of the first ILD layer 210, and the source / drain epitaxial structure Sb (or the source / drain epitaxial structure Db) are arranged along the Y direction.

[0128] The backside gate via 150 is embedded in the isolation structure 140 below the first ILD layer 210 and is connected to the gate structure 220. The backside gate track 370 is below the first ILD layer 210 and the transistor array TR. The backside gate track 370 extends along the X direction. The backside gate via 150 is between the gate structure 220 and the backside gate track 370, so that the backside gate track 370 is electrically connected to the gate structure 220 via the backside gate via 150. Therefore, the backside gate track 370 is electrically connected to the gate structure 220 via the backside gate via 150. The portion 212 of the first ILD layer 210 is directly above the backside gate track 370. In other words, the backside gate track 370 is between the first portion Tra and the second portion TRb of the transistor array TR in the top view. That is, the transistors of the transistor array TR are not formed directly above the backside gate track 370.

[0129] With such a configuration, the overlap area between the backside gate track 370 and the source / drain structures (e.g., source / drain epitaxial structure Sa, source / drain epitaxial structure Sb, source / drain epitaxial structure Da, source / drain epitaxial structure Db, and source / drain contacts 250a, source / drain contacts 250b, source / drain contacts 255a, and source / drain contacts 255b) is reduced (e.g., the overlap area between the backside gate track 370 and the source / drain structures is reduced). Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A As the parasitic capacitance is reduced, the cutoff frequency f of the semiconductor device 100 is reduced. T (Current Gain (I out / I in )=1) will not decrease too much, such as Fig. 22 In addition, the gate voltage may be applied not only to the gate conductive line 240 but also to the back gate rail 370, thereby reducing the gate resistance. For example, the gate conductive line 240 and the back gate rail 370 are on opposite sides of the transistor. As the gate resistance decreases, the maximum oscillation frequency f of the semiconductor device 100 increases. MAX (Power gain (P out / P in )=1) can be effectively improved, such as Fig.23 as shown in .

[0130] like Fig. 15C and Fig.14AAs shown in FIG. 1 , the first source / drain trace 310 is over the source / drain contact 250a and the source / drain contact 250b and interconnects them, while the first source / drain trace 315 interconnects the source / drain contacts 255a and 255b. Therefore, the series resistance of the source / drain contact 250a and the source / drain contact 250b (the source / drain contact 255a and the source / drain contact 255b) can be reduced.

[0131] exist Fig. 15B In the embodiment, the width W3 of the backside gate track 370 is in the range of about 10 nm to about 5 μm. Fig.15D In the embodiment, the length L3 of the backside gate track 370 is in the range of about 10 nm to about 200 μm. FIG. 15A to FIG. 15E In the embodiment, the through-hole 276 is connected to the first gate trace 290. However, in some other embodiments, the through-hole 276 can be directly connected to a gate trace in the interconnect structure 320 (eg, the second gate trace 332 or a higher gate trace, if present).

[0132] FIG. 16A to FIG. 16D A method of manufacturing an interconnect structure 320 at various stages according to some embodiments of the present disclosure is shown. Fig.16A After forming the first gate trace 290 and the first source / drain traces 310 and 315, Fig.14A Another ILD layer is formed over the structure. Subsequently, a plurality of vias 322, a plurality of vias 324, and a plurality of vias 326 are formed in the ILD layer. Vias 322 are connected to the first gate trace 290, vias 324 are connected to the first source / drain trace 310, and vias 326 are connected to the first drain / source trace 315. The materials, configurations, dimensions, processes, and / or operations associated with vias 322, 324, and 326 are similar to those of Fig.13A The front side gate vias 272 and source / drain vias 274 are similar or identical.

[0133] refer to Fig.16A and Fig. 16B .exist Fig.16A Another ILD layer is formed above the structure. Subsequently, a second gate trace 332 and second source / drain traces 334 and 336 are formed in the ILD layer. The second gate trace 332 is electrically connected to the first gate trace 290 via the via 322, the second source / drain trace 334 is electrically connected to the first source / drain trace 310 via the via 324, and the second source / drain trace 336 is electrically connected to the first source / drain trace 315 via some of the vias 326. The materials, configurations, dimensions, processes and / or operations related to the second gate trace 332 and the second source / drain traces 334 and 336 are similar to those of the embodiment of the present invention. Fig.14AThe first gate trace 290 and the first source / drain traces 310 and 315 are similar or identical.

[0134] refer to Fig. 16C .exist Fig. 16B Another ILD layer is formed over the structure. Subsequently, a plurality of vias 342 and a plurality of vias 344 are formed in the ILD layer. The vias 342 are connected to the second source / drain traces 334, and the vias 344 are connected to the second source / drain traces 336. The materials, configurations, dimensions, processes and / or operations associated with the vias 342 and 344 are similar to those of Fig.13A The front side gate vias 272 and source / drain vias 274 are similar or identical.

[0135] refer to Fig. 16C and Fig.16D .exist Fig. 16C Another ILD layer is formed over the structure of . Subsequently, a third source / drain trace 352 and a third source / drain trace 354 are formed in the ILD layer. The third source / drain trace 352 is electrically connected to the second source / drain trace 334 via the via 342, and the third source / drain trace 354 is electrically connected to the second source / drain trace 336 via some of the vias 344. The materials, configurations, dimensions, processes and / or operations associated with the third source / drain trace 352 and the third source / drain trace 354 are similar to those of the embodiment of the present invention. Fig.14A The first gate trace 290 and the first source / drain traces 310 and 315 are similar or identical.

[0136] It should be noted that the number of the backside gate rails 370 is not limited to one. The number of the backside gate rails 370 may be in the range of 1 to about 4000. Therefore, depending on the number of the backside gate rails 370, the source / drain epitaxial structures connected to the same first source / drain trace are in the range of 1 to about 4000. Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A A simplified cross-sectional view of the epitaxial layer 124, the gate structure 220, the gate conductive line 240, the backside gate via 150 and the backside gate track 370 according to some embodiments of the present disclosure is shown. Fig. 17B , Fig.18B , Fig.19B , Fig. 20B and Fig.21B A simplified top view of the epitaxial layer 124 , the gate structure 220 , the gate conductive line 240 , the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, and the backside gate track 370 is shown according to some embodiments of the present disclosure.

[0137] exist FIG. 17A to FIG. 17B , each of the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da, and the source / drain epitaxial structure Db is connected to five stacks of the epitaxial layer 124. The source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb are separated from each other, and the source / drain epitaxial structure Da and the source / drain epitaxial structure Db are separated from each other. The number of the backside gate rails 370 is one. The backside gate rails 370 are between the source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb and between the source / drain epitaxial structure Da and the source / drain epitaxial structure Db in the top view. In some embodiments, each of the gate structures 220 has a length L4 in the range of about 10 nm to about 200 μm and a width W4 in the range of about 10 nm to about 500 nm between the gate conductive lines 240.

[0138] exist FIG. 18A to FIG. 18B In the embodiment, each of the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, and the source / drain epitaxial structure Dc is connected to three or four stacks of the epitaxial layer 124. The source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, and the source / drain epitaxial structure Sc are separated from each other, and the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, and the source / drain epitaxial structure Dc are separated from each other. The number of the backside gate tracks 370 is two. One of the back side gate rails 370 is between the source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb and between the source / drain epitaxial structure Da and the source / drain epitaxial structure Db in the top view, and the other of the back side gate rails 370 is between the source / drain epitaxial structure Sb and the source / drain epitaxial structure Sc and between the source / drain epitaxial structure Db and the source / drain epitaxial structure Dc in the top view.

[0139] exist FIG. 19A to FIG. 19BIn the embodiment, each of the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, the source / drain epitaxial structure Sd, the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, the source / drain epitaxial structure Dc, and the source / drain epitaxial structure Dd is connected to two or three stacks of the epitaxial layer 124. The source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, and the source / drain epitaxial structure Sd are separated from each other, and the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, the source / drain epitaxial structure Dc, and the source / drain epitaxial structure Dd are separated from each other. The number of the backside gate tracks 370 is three. The back side gate rail 370 is between the source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb (or the source / drain epitaxial structure Sb and the source / drain epitaxial structure Sc, or the source / drain epitaxial structure Sc and the source / drain epitaxial structure Sd) and between the source / drain epitaxial structure Da and the source / drain epitaxial structure Db (or the source / drain epitaxial structure Db and the source / drain epitaxial structure Dc, or the source / drain epitaxial structure Dc and the source / drain epitaxial structure Dd) in the top view.

[0140] exist FIG. 20A to FIG. 20B , each of the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, the source / drain epitaxial structure Sd, the source / drain epitaxial structure Se, the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, the source / drain epitaxial structure Dc, the source / drain epitaxial structure Dd, and the source / drain epitaxial structure De is connected to two stacks of the epitaxial layer 124. The source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, the source / drain epitaxial structure Sd, and the source / drain epitaxial structure Se are separated from each other, and the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, the source / drain epitaxial structure Dc, the source / drain epitaxial structure Dd, and the source / drain epitaxial structure De are separated from each other. The number of the backside gate rails 370 is four. The back side gate rail 370 is between the source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb (or the source / drain epitaxial structure Sb and the source / drain epitaxial structure Sc, or the source / drain epitaxial structure Sc and the source / drain epitaxial structure Sd, or the source / drain epitaxial structure Sd and the source / drain epitaxial structure Se) and between the source / drain epitaxial structure Da and the source / drain epitaxial structure Db (or the source / drain epitaxial structure Db and the source / drain epitaxial structure Dc, or the source / drain epitaxial structure Dc and the source / drain epitaxial structure Dd, or the source / drain epitaxial structure Dd and the source / drain epitaxial structure De) in the top view.

[0141] exist FIG. 21A to FIG. 21BIn the embodiment, each of the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, the source / drain epitaxial structure Sd, the source / drain epitaxial structure Se, the source / drain epitaxial structure Sf, the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, the source / drain epitaxial structure Dc, the source / drain epitaxial structure Dd, the source / drain epitaxial structure De, and the source / drain epitaxial structure Df is connected to one or two stacks of the epitaxial layer 124. The source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Sc, the source / drain epitaxial structure Sd, the source / drain epitaxial structure Se, and the source / drain epitaxial structure Sf are separated from each other, and the source / drain epitaxial structure Da, the source / drain epitaxial structure Db, the source / drain epitaxial structure Dc, the source / drain epitaxial structure Dd, the source / drain epitaxial structure De, and the source / drain epitaxial structure Df are separated from each other. The number of the backside gate tracks 370 is five. In the top view, the back side gate rail 370 is between the source / drain epitaxial structure Sa and the source / drain epitaxial structure Sb (or the source / drain epitaxial structure Sb and the source / drain epitaxial structure Sc, or the source / drain epitaxial structure Sc and the source / drain epitaxial structure Sd, or the source / drain epitaxial structure Sd and the source / drain epitaxial structure Se, or the source / drain epitaxial structure Se and the source / drain epitaxial structure Sf) and between the source / drain epitaxial structure Da and the source / drain epitaxial structure Db (or the source / drain epitaxial structure Db and the source / drain epitaxial structure Dc, or the source / drain epitaxial structure Dc and the source / drain epitaxial structure Dd, or the source / drain epitaxial structure Dd and the source / drain epitaxial structure De, or the source / drain epitaxial structure De and the source / drain epitaxial structure Df).

[0142] Fig. 22 and Fig.23 is a performance comparison of semiconductor devices including different numbers of backside gate tracks. Fig. 22 and Fig.23 The semiconductor device in the embodiment may be a FinFET or a nanostructure (e.g., GAA FET). Fig. 22 The cutoff frequencies f of semiconductor devices with zero backside gate tracks (#0), one backside gate track (#1), and two backside gate tracks (#2) are compared. T (Current Gain (I out / I in )=1). Fig. 22 As shown in , the semiconductor devices (#0, #1, and #2) have similar cutoff frequencies. Fig.23 The maximum oscillation frequency f of the semiconductor devices (#0, #1 and #2) is compared. MAX (Power gain (P out / Pin )=1). Fig.23 As shown in , semiconductor device (#2) has a maximum oscillation frequency higher than the maximum vibration frequency of semiconductor device (#1), while semiconductor device (#1) has a maximum oscillation frequency much higher than the maximum oscillation frequency of semiconductor device (#0).

[0143] Figures 24 to 25B 1 and 2 illustrate a method of manufacturing a semiconductor device 100' at various stages according to some embodiments of the present disclosure. It should be understood that additional embodiments of the method may be Figures 24 to 25B Additional operations are provided before, during, and after the processes shown in the figure, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. Figures 1 to 15E The same or similar configurations, materials, processes and / or operations may be omitted in detailed description.

[0144] In the formation of FIG. 12A to FIG. 12E After forming the structure shown in FIG. 1 , a third ILD layer 260 is deposited over the substrate 110 . Fig.24 As shown in . Subsequently, a front side gate via 272 and a source / drain via 274 are formed in the third ILD layer 260. Thereafter, Fig.24 Structural experience in FIG. 14A to FIG. 14E The process shown in .

[0145] refer to Fig.25A and Fig.25B , Fig.25B It is along Fig.25A After forming the first gate trace 290 and the first source / drain trace 310 and the first source / drain trace 315, an interconnect structure 320 is formed above the substrate 110. The substrate 110 and the base portion 112 are then removed (see FIG. 14A to FIG. 14E Subsequently, a fifth ILD layer 360 is formed (for clarity, it is Fig.25A The back side of the gate structure 150 is represented by a dotted line in the figure to cover the source / drain epitaxial structure Sa, the source / drain epitaxial structure Sb, the source / drain epitaxial structure Da and the source / drain epitaxial structure Db, the gate structure 220, the isolation structure 140 and the back side gate through hole 150.

[0146] Next, the fifth ILD layer 360, the isolation structure 140, the first ILD layer 210, the second ILD layer 230 and the third ILD layer 260 are patterned to form an opening O3 and a gate trench GT3. Fig.25B Subsequently, a through hole 276 is formed in the opening O3, and a backside gate track 370 is formed in the gate trench GT3.

[0147] Based on the above discussion, it can be seen that some embodiments of the present disclosure provide advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages are necessarily disclosed in some embodiments of the present disclosure, and no particular advantages need to be used for all embodiments. One advantage is that the semiconductor device includes at least one backside gate track to reduce the gate resistance therein and increase the power gain of the semiconductor device. In addition, the source / drain structure (e.g., source / drain epitaxial structure and source / drain contact) is not directly above the backside gate track, thereby reducing the parasitic capacitance between the gate and the source / drain. In addition, the source / drain traces are formed to interconnect the source / drain contacts, thereby reducing the series resistance of the source / drain contacts.

[0148] According to some embodiments, a semiconductor device includes a first transistor, a second transistor, an interlayer dielectric layer, and a backside gate track. The first transistor and the second transistor are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source / drain epitaxial structure connected to the first channel layer, and a second source / drain epitaxial structure. The second transistor includes a second channel layer, a gate structure surrounding the second channel layer, a third source / drain epitaxial structure connected to the second channel layer, and a fourth source / drain epitaxial structure. The interlayer dielectric layer surrounds the first transistor and the second transistor. A portion of the interlayer dielectric layer is sandwiched between the first source / drain epitaxial structure and the third source / drain epitaxial structure. The backside gate track is below the interlayer dielectric layer and electrically connected to the gate structure. The portion of the interlayer dielectric layer sandwiched between the first source / drain epitaxial structure and the third source / drain epitaxial structure is directly above the backside gate track. In some embodiments, the backside gate track extends in a second direction different from the first direction. In some embodiments, the first source / drain epitaxial structure, a portion of the interlayer dielectric layer, and the second source / drain epitaxial structure are arranged along a first direction. In some embodiments, the first transistor further includes a third channel layer between the first channel layer and the second channel layer in the top view, and the distance between the first channel layer and the second channel layer is greater than the distance between the second channel layer and the third channel layer. In some embodiments, the semiconductor device further includes a backside gate via between the gate structure and the backside gate track. In some embodiments, the semiconductor device further includes an isolation structure below the interlayer dielectric layer and surrounding the backside gate via. In some embodiments, the semiconductor device further includes a source / drain trace above the first source / drain epitaxial structure and the third source / drain epitaxial structure and interconnecting the first source / drain epitaxial structure and the third source / drain epitaxial structure.

[0149] According to some embodiments, a semiconductor device includes a transistor array and a backside gate track. The transistor array includes a first portion and a second portion. The first portion includes a plurality of first transistors arranged in a first direction in a top view. The second portion includes a plurality of second transistors arranged in the first direction in a top view. The first portion and the second portion are arranged in a second direction different from the first direction in a top view. The backside gate track is below the transistor array and electrically connected to a plurality of gate structures of the first transistor. The backside gate track extends in the first direction in a top view and between the first portion and the second portion of the transistor array. In some embodiments, the backside gate track is further electrically connected to a plurality of gate structures of the second transistor. In some embodiments, there is no transistor directly above the backside gate track. In some embodiments, the semiconductor device further includes a gate trace above the transistor array. In some embodiments, the semiconductor device further includes a through hole extending from the gate trace to the backside gate track. In some embodiments, the semiconductor device further includes a gate conductive line above the transistor array and interconnecting the gate structures of the first transistor. In some embodiments, the gate conductive line and the backside gate track are on a plurality of opposite sides of the first transistor.

[0150] According to some embodiments, a method for manufacturing a semiconductor device includes forming a first fin structure and a second fin structure above a substrate. An isolation structure is formed above the substrate and around a plurality of bottom portions of the first fin structure and the second fin structure. A backside gate via is formed in the isolation structure and between the first fin structure and the second fin structure. A dummy gate is formed above the first fin structure and the second fin structure. The dummy gate is replaced with a gate structure. The gate structure is electrically connected to the backside gate via. The substrate is removed. A backside gate track is formed below the backside gate via and connected to the backside gate via. In some embodiments, the method for manufacturing a semiconductor device also includes forming an interlayer dielectric layer above the substrate to surround the dummy gate. A through hole is formed in the interlayer dielectric layer, wherein the backside gate track is connected to the through hole. In some embodiments, forming the through hole is performed before removing the substrate. In some embodiments, the method for manufacturing a semiconductor device also includes forming a gate conductive line above the gate structure and connecting the gate conductive line to the gate structure, wherein the gate conductive line and the backside gate track extend in substantially the same direction in a top view. In some embodiments, the method for manufacturing a semiconductor device also includes forming an interconnect structure above the substrate and electrically connecting the interconnect structure to the gate structure. In some embodiments, the substrate is removed such that the backside of the gate structure is exposed.

[0151] According to some embodiments, a semiconductor device includes a first transistor, a second transistor, a backside gate track and a backside gate through hole. The first transistor and the second transistor are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source / drain epitaxial structure connected to the first channel layer, and a second source / drain epitaxial structure. The second transistor includes a second channel layer, a gate structure surrounding the second channel layer, a third source / drain epitaxial structure connected to the second channel layer, and a fourth source / drain epitaxial structure. The backside gate track is below the first transistor and the second transistor and electrically connected to the gate structure, wherein the backside gate track extends in a second direction different from the first direction. The backside gate through hole is between the gate structure and the backside gate track, wherein the backside gate track is electrically connected to the gate structure via the backside gate through hole.

[0152] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they can easily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and / or achieving the same advantages of the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not deviate from the spirit and scope of some embodiments of the present disclosure, and such equivalent constructions can be variously changed, replaced and substituted in some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A first transistor and a second transistor are arranged along a first direction in a top view, wherein the first transistor comprises a first channel layer, a gate structure surrounding the first channel layer, a first source / drain epitaxial structure connected to the first channel layer, and a second source / drain epitaxial structure, and the second transistor comprises a second channel layer, the gate structure surrounding the second channel layer, a third source / drain epitaxial structure connected to the second channel layer, and a fourth source / drain epitaxial structure; an interlayer dielectric layer surrounding the first transistor and the second transistor, wherein a portion of the interlayer dielectric layer is sandwiched between the first source / drain epitaxial structure and the third source / drain epitaxial structure; and A backside gate track is below the interlayer dielectric layer and electrically connected to the gate structure, wherein the portion of the interlayer dielectric layer sandwiched between the first source / drain epitaxial structure and the third source / drain epitaxial structure is directly above the backside gate track.

2. The semiconductor device according to claim 1, wherein The backside gate track extends in a second direction different from the first direction.

3. The semiconductor device according to claim 1, wherein: The first source / drain epitaxial structure, the portion of the interlayer dielectric layer and the second source / drain epitaxial structure are arranged along the first direction.

4. The semiconductor device according to claim 1, wherein In the top view, the first transistor further includes a third channel layer between the first channel layer and the second channel layer, and a distance between the first channel layer and the second channel layer is greater than a distance between the second channel layer and the third channel layer.

5. The semiconductor device according to claim 1, wherein Also includes: A source / drain trace is over the first source / drain epitaxial structure and the third source / drain epitaxial structure and interconnects the first source / drain epitaxial structure and the third source / drain epitaxial structure.

6. A semiconductor device, characterized in that: Include: A transistor array comprising: a first portion comprising a plurality of first transistors arranged in a first direction in a top view; and a second portion, comprising a plurality of second transistors arranged in the first direction in the top view, wherein the first portion and the second portion are arranged in a second direction different from the first direction in the top view; and A backside gate track is below the transistor array and electrically connected to the plurality of gate structures of the plurality of first transistors, wherein the backside gate track extends in the first direction in the top view and between the first portion and the second portion of the transistor array.

7. The semiconductor device according to claim 6, wherein: The backside gate track is further electrically connected to a plurality of gate structures of the plurality of second transistors.

8. The semiconductor device according to claim 6, wherein: There is no transistor directly above the backside gate track.

9. The semiconductor device according to claim 6, wherein: Also includes: A gate conductive line is above the transistor array and interconnects the plurality of gate structures of the plurality of first transistors.

10. A semiconductor device, characterized in that: Include: A first transistor and a second transistor are arranged along a first direction in a top view, wherein the first transistor comprises a first channel layer, a gate structure surrounding the first channel layer, a first source / drain epitaxial structure connected to the first channel layer, and a second source / drain epitaxial structure, and the second transistor comprises a second channel layer, the gate structure surrounding the second channel layer, a third source / drain epitaxial structure connected to the second channel layer, and a fourth source / drain epitaxial structure; a backside gate track under the first transistor and the second transistor and electrically connected to the gate structure, wherein the backside gate track extends in a second direction different from the first direction; as well as A backside gate via is between the gate structure and the backside gate track, wherein the backside gate track is electrically connected to the gate structure via the backside gate via.

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