Semiconductor device

Abstract

A semiconductor device includes a first gate electrode across a first fin over a first type well region of a semiconductor substrate; a second gate electrode across a second fin over a second type well region of the semiconductor substrate, the first type well region and the second type well region having opposite conductivity types; an isolation layer disposed over the semiconductor substrate and on sidewalls of the first fin and the second fin; a gate cutting structure separating the first gate electrode from the second gate electrode, the gate cutting structure extending through the isolation layer; and a dielectric layer disposed on the gate cutting structure and separating the gate cutting structure from the semiconductor substrate, the dielectric layer below the bottom surface of the isolation layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generation after generation of ICs, each with smaller and more complex circuits than the previous generation. In the process of IC development, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometric size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) decreases. This process of scale reduction generally provides benefits by improving production efficiency and reducing associated costs. This scale reduction also increases the complexity of processing and manufacturing ICs. As the semiconductor industry moves towards nanotechnology process nodes in pursuit of higher device density, higher performance, and lower costs, the challenges posed by manufacturing and design issues have led to the development of multi-gate semiconductor devices including fin field effect transistors (FinFETs) and gate-all-around (GAA) devices.

[0004] Although the advantages of FinFET and GAA devices include reduced short channel effects and increased current flow, the associated manufacturing processes continue to become more challenging as feature sizes and pitches continue to decrease. Therefore, while current approaches are satisfactory in many aspects, further improvements in multi-gate semiconductor devices are still needed as transistor dimensions continue to shrink significantly. Utility Model Content

[0005] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first gate electrode across a first fin above a first type well region of a semiconductor substrate; a second gate electrode across a second fin above a second type well region of the semiconductor substrate, the first type well region and the second type well region having opposite conductivity types; an isolation layer disposed above the semiconductor substrate and on the sidewalls of the first fin and the second fin; a gate cutting structure separating the first gate electrode from the second gate electrode, the gate cutting structure extending through the isolation layer; and a dielectric layer disposed on the gate cutting structure and separating the gate cutting structure from the semiconductor substrate, the dielectric layer being below a bottom surface of the isolation layer.

[0006] Some embodiments of the present disclosure provide a semiconductor device, comprising a first gate electrode straddling a first fin above a first-type well region of a semiconductor substrate; a second gate electrode straddling a second fin above a second-type well region of the semiconductor substrate, wherein the first-type well region and the second-type well region have opposite conductivity types; a gate cutting structure separating the first gate electrode from the second gate electrode; and an oxide layer disposed between the gate cutting structure and the semiconductor substrate.

[0007] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first gate electrode across a first fin above a first type well region of a semiconductor substrate; a second gate electrode across a second fin above a second type well region of the semiconductor substrate, wherein the first type well region and the second type well region have opposite conductivity types; an isolation layer disposed above the semiconductor substrate and on multiple sidewalls of the first fin and the second fin; and a gate cutting structure separating the first gate electrode from the second gate electrode, wherein the gate cutting structure has a first portion directly above the isolation layer and a second portion directly above a surface between the first type well region and the second type well region, the first portion having a first height, and the second portion having a second height greater than the first height. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of this disclosure are in the attached Figure 1 The following detailed description is best understood when read together. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 Shows the layout of the semiconductor structure of the SRAM cell according to some embodiments of the present disclosure;

[0010] Figure 2A Graphics Figure 1 An equivalent circuit of a semiconductor-controlled rectifier (SCR) in each SRAM cell;

[0011] Figure 2B FIG. 1 is a diagram illustrating some embodiments of the present disclosure. Figure 3A A cross-sectional view of an SCR;

[0012] Figure 3A , Figure 3B ,and Figure 3C FIG. 1 is a diagram illustrating some embodiments of the present disclosure. Figure 1 A cross-sectional view of a semiconductor structure;

[0013] Figure 4 , Figure 5 , Figure 6 , Figure 7 ,and Fig. 9 According to some embodiments of the present disclosure, Fig.14 a perspective view of a semiconductor structure during a manufacturing process of the method;

[0014] Fig. 8A , Figure 8B ,and Figure 8C According to some embodiments of the present disclosure, Fig.14 a cross-sectional view of a semiconductor structure during a manufacturing process of the method;

[0015] Fig. 10A , Fig. 10B ,and Fig. 10C FIG. 1 shows an alternative embodiment according to some embodiments of the present disclosure. Figure 1 A cross-sectional view of a semiconductor structure;

[0016] Fig.11A , Fig. 11B ,and Fig. 11C FIG. 1 shows an alternative embodiment according to some embodiments of the present disclosure. Figure 1 A cross-sectional view of a semiconductor structure;

[0017] Fig. 12A , Fig. 12B ,and Fig. 12C FIG. 1 is a diagram illustrating another alternative embodiment of some embodiments of the present disclosure. Figure 1 A cross-sectional view of a semiconductor structure;

[0018] Fig.13A , Fig. 13B ,and Fig. 13C FIG. 1 shows another alternative embodiment according to some embodiments of the present disclosure. Figure 1 A cross-sectional view of a semiconductor structure;

[0019] Fig.14 A flow chart is shown of a method for forming a semiconductor structure according to some embodiments of the present disclosure.

[0020]

Explanation of symbols

[0021] 10_1,10_2,10_3,10_4: SRAM cells

[0022] 20: Blocks

[0023] 40:SCR

[0024] 100:Semiconductor structure

[0025] 102:Substrate

[0026] 104,104a,104b: N-type well area / first-type well area

[0027] 106,106a,106b,106c: P-type well area / second-type well area

[0028] 112a,112b,112c,112d,112e,112f,112g: fins

[0029] 114: Isolation Area / Isolation Structure

[0030] 116: Dielectric layer

[0031] 118:ESL

[0032] 122a, 122b, 122c, 122d: dummy gate stack

[0033] 124: Gate dielectric layer

[0034] 126: Gate electrode layer

[0035] 128: Gate spacer

[0036] 130c, 130d: Source / drain structure

[0037] 132:P+ Zone

[0038] 133: P-type well pick-up area

[0039] 135: Source / drain structure / N+ region

[0040] 135a, 135b: Source / drain structure

[0041] 137: N-type well pick-up area

[0042] 140: Interlayer dielectric layer (ILD layer)

[0043] 142a, 142b, 142c, 142d: Metal gate stack

[0044] 144: Gate dielectric layer

[0045] 146: Gate electrode layer

[0046] 148: Gate electrode layer

[0047] 150a, 150b, 150c, 150d, 150e, 150f, 150g, 150h: Gate structure

[0048] 152a, 152b, 152c, 152d, 152e, 152f: gate dielectric layer

[0049] 154a, 154b, 154c, 154d, 154e, 154f: gate electrode layer

[0050] 156a: First etching step

[0051] 156b: Second etching step

[0052] 158: Passivation process

[0053] 160: Opening

[0054] 162: Groove / groove

[0055] 172a, 172b: Gate cutting structure

[0056] 172a-1: first dielectric layer

[0057] 172a-2: Second dielectric layer

[0058] 200: Method

[0059] 202,204,206,208,210,212,214,216,218,220: Operation

[0060] X,Y: axis

[0061] AA,BB,CC: Section lines

[0062] PG-1,PG-2: Pass-gate transistor

[0063] PD-1, PD-2: Pull-down transistor

[0064] PU-1,PU-2: Pull-up transistor

[0065] HH1,HH2,HH3: Depth

[0066] MN:NMOS transistor

[0067] MP:PMOS transistor

[0068] Q1: Parasitic PNP transistor

[0069] Q2: Parasitic NPN transistor

[0070] R_NW: Resistor

[0071] R_PW: Resistor

[0072] W1, W2: opening width DETAILED DESCRIPTION

[0073] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0074] In addition, for ease of description, spatial relative terms such as "below", "under", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature illustrated in the figures to another (multiple) element or feature. Spatially relative terms are intended to encompass different orientations of the device when in use or operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly. Source / drain may refer to a source or drain, individually or collectively depending on the context. Still further, when a number or a range of numbers is described with "about", "approximately", and the like, unless otherwise specified, the term is intended to encompass a number within + / -10% of the described number. For example, the term "about 5nm" encompasses a dimensional range from 4.5nm to 5.5nm.

[0075] The present disclosure generally relates to semiconductor devices and manufacturing methods, and more particularly, to manufacturing multi-gate devices having isolation structures that "cut" the metal gate stack of the multi-gate device into shorter portions (segments). Such isolation structures may also be referred to as cut-metal-gate (CMG) structures or gate cut structures. The metal gate stack in the multi-gate device may be formed as a long gate structure extending across multiple active regions (e.g., fin regions) of multiple field effect transistors (FETs). Once the gate structure is formed, a patterning process may "cut" one or more long gate structures into shorter portions. In other words, the patterning process may remove redundant gate portions of one or more long gate structures to form one or more isolation trenches (also referred to as "CMG trenches") between the FETs and separate the long gate structures into shorter portions. This process is referred to as a CMG process. Subsequently, the isolation trenches formed between the separated portions of the long gate structure may be filled with a dielectric material to form an isolation structure. The isolation structure electrically isolates the separated gate structure portions of adjacent multi-gate devices.

[0076] Fin field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. FinFETs have an elevated channel that is wrapped on one or more sides by a gate structure (for example, the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors may also be referred to as surrounding gate transistors (SGTs) or gate-all-around (GAA) transistors. Presented herein are specific embodiments of FinFETs as an exemplary type of multi-gate transistor. A person of ordinary skill in the art may recognize other examples of semiconductor devices, such as GAA transistors, which may also benefit from many aspects of the present disclosure. In addition, gate cut structures have a wide range of applications in various circuit implementations. The present invention presents a static random access memory (SRAM) circuit as an exemplary circuit for implementing a gate cut structure. A person skilled in the art may recognize other examples of circuits, such as logic circuits, input / output (I / O) circuits, etc., which may also benefit from the various aspects of the present disclosure.

[0077] Figure 1 The diagram shows a layout of an SRAM circuit including SRAM cells 10_1 , 10_2 , 10_3 , and 10_4 (collectively referred to as SRAM cell 10 ) according to some embodiments of the present disclosure. Figure 1 The SRAM circuit shown in the figure may be part of a larger SRAM cell array. In some embodiments, the transistors in the SRAM cell 10 are FinFETs in the N-type well regions 104a and 104b and the P-type well regions 106a to 106c. The N-type well region 104b is positioned between the P-type well regions 106b and 106c, and the N-type well region 104a is positioned between the P-type well regions 106a and 106b.

[0078] Two adjacent SRAM cells 10_1 and 10_3 are arranged in the same row of the SRAM cell array. Two adjacent SRAM cells 10_1 and 10_2 are arranged in the same column of the SRAM cell array. Two adjacent SRAM cells 10_3 and 10_4 are arranged in the same column of the SRAM cell array. In other words, two adjacent SRAM cells 10_2 and 10_4 are arranged in the same row of the SRAM cell array. Figure 1 , each of the SRAM cells 10 has the same rectangular shape / area, with a width and a height, and the height is smaller than the width. It should be noted that Figure 1 The SRAM circuit shown in FIG. 1 is merely an example and is not intended to limit the SRAM cell 10 of the SRAM cell array.

[0079] In an SRAM cell array, the fins may be patterned using any suitable method. For example, one or more optical lithography processes, including double patterning or multiple patterning processes, may be used to pattern the fins. In general, double patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing the generation of patterns having, for example, a smaller pitch than that obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the semiconductor fins.

[0080] In the SRAM cell 10_1, the pass-gate transistor PG-1 is formed at the intersection of the fins 112a and 112b on the P-type well 106a and the gate structure 150c. The pull-down transistor PD-1 is formed at the intersection of the fins 112a and 112b on the P-type well 106a and the gate structure 150d. The pass-gate transistor PG-2 is formed at the intersection of the fins 112g and 112f on the P-type well 106b and the gate structure 150g. The pull-down transistor PD-2 is formed at the intersection of the fins 112g and 112f on the P-type well 106b and the gate structure 150e. The pull-up transistor PU-1 is formed at the intersection of the fin 112c on the N-type well 104a and the gate structure 150d. The pull-up transistor PU-2 is formed at the intersection of the fin 112d on the N-type well 104a and the gate structure 150e. In such embodiments, the pull-down transistors PD- 1 and PD- 2 and the pass-gate transistors PG- 1 and PG- 2 are dual-fin transistors, and the pull-up transistors PU- 1 and PU- 2 are single-fin transistors.

[0081] Various contacts and their corresponding interconnecting vias may be used to couple the components in each SRAM cell 10_1 to 10_4. Through vias and gate contacts, a word line (WL) contact (not shown) may be coupled to the gate of pass gate transistor PG-1 via gate structure 150c, and another word line contact WL is coupled to the gate of pass gate transistor PG-2 via gate structure 150g. Similarly, a bit line (BL) contact (not shown) is coupled to the drain of pass gate transistor PG-1, and a complementary bit line contact BLB is coupled to the drain of pass gate transistor PG-2.

[0082] A power contact (not shown) coupled to the power supply node VDD is coupled to the source of the pull-up transistor PU-1, and another power contact (not shown) coupled to the power supply node VDD is coupled to the source of the pull-up transistor PU-2. A ground contact (not shown) coupled to the ground VSS is coupled to the source of the pull-down transistor PD-1, and another ground contact (not shown) coupled to the ground VSS is coupled to the source of the pull-down transistor PD-2.

[0083] In such an embodiment, SRAM cell 10_2 is a duplicate of SRAM cell 10_1, but flipped on the X axis. Furthermore, SRAM cell 10_3 is a duplicate of SRAM cell 10_1, but flipped on the Y axis. Furthermore, SRAM cell 10_4 is a duplicate of SRAM cell 10_3, but flipped on the X axis. Common contacts (e.g., BL, VDD, and VSS) are combined to save space.

[0084] The gate structure 150d is shared by the pull-up transistor PU-1 and the pull-down transistor PD-1 of the SRAM cell 10_1, and the gate structure 150g is shared by the pass gate transistor PG-2 of the SRAM cells 10_1 and 10_3. The dielectric structure 172b is formed above the boundary (or junction, interface) between the P-type well region 106b and the N-type well region 104a, and the gate structures 150d and 150g are separated by the dielectric structure 172b. That is, the dielectric structure 172b is a gate cutting structure (or called a CMG structure or CMG feature) for the gate structures 150d and 150g. The gate structure 150e is shared by the pull-up transistor PU-2 and the pull-down PD-2 of the SRAM cell 10_1. The dielectric structure 172a is formed above the boundary (or junction, interface) between the P-type well region 106a and the N-type well region 104a, and the gate structures 150c and 150e are separated by the dielectric structure 172a. That is, the dielectric structure 172a is a gate cutting structure for the gate structures 150c and 150e. In some embodiments, the gate cutting structure is formed by a CMG process.

[0085] Figure 2AFIG. 1 is a diagram illustrating some embodiments of the present disclosure. Figure 1 The equivalent circuit of the semiconductor-controlled rectifier (SCR) 40 in each SRAM cell 10 is as follows: Figure 2B Figure 1 is a cross-sectional view, the cross-sectional view shows Figure 2A SCR 40.

[0086] Reference together Figure 2A and Figure 2B , a P-type well region 106 and an N-type well region 104 are formed on a substrate 102. In some embodiments, the substrate 102 is a P-type substrate, such as a Si substrate. The PMOS transistor MP of the SRAM cell 10 is formed on the N-type well region 104, and the NMOS transistor MN of the SRAM cell 10 is formed on the P-type well region 106. In addition, the N-type well pick-up region 137 forms a bulk terminal of the PMOS transistor MP, and the P-type well pick-up region 133 forms a bulk terminal of the NMOS transistor MN.

[0087] For simplicity, the PMOS transistor MP and the NMOS transistor MN are Figure 2A and Figure 2B As shown in the figure, a planar transistor is shown. As described above, the PMOS transistor MP and the NMOS transistor MN may be multi-gate transistors, such as FinFET or GAA transistors. In addition, the PMOS transistor MP may be Figure 1 The pull-up transistor PU-1 or PU-2 of the SRAM cell 10, the NMOS transistor MN may be Figure 1 The pass gate transistor PG-1 or PG-2 or the pull-down transistor PD-1 or PD-2 of the SRAM cell 10.

[0088] The parasitic PNP transistor Q1 is shown to have an emitter formed by the P+ region 132 (i.e., the source of the PMOS transistor MP), a base formed by the N-type well region 104, and a collector formed by the P-type well region 106 and / or the substrate 102. The base of the PNP transistor Q1 is coupled to the N-type well pick-up region 137 via the resistor R_NW. The N-type well pick-up region 137 is an electrical connection made of an N-type region on the N-type well region 104, and the N-type well pick-up region 137 is used to connect to the power supply node VDD. The resistor R_NW is a parasitic component (intrinsic resistance) of the N-type well region 104. The collector of the PNP transistor Q1 is coupled to the P-type well pick-up region 133 via the resistor R_PW. The P-type well pick-up region 133 is an electrical connection made of a P-type region on the P-type well region 106, and the P-type well pick-up region 133 is used to connect to the ground VSS. The resistor R_PW is a parasitic component (intrinsic resistance) of the P-type well region 106. In some embodiments, the collector of the PNP transistor Q1 is coupled to the P-type well pick-up region 133 via the resistor R_PW and a parasitic resistor (not shown) of the substrate 102.

[0089] The parasitic NPN transistor Q2 is shown to have an emitter formed by the N+ region 135 (i.e., the source of the NMOS transistor MN), a base formed by the P-type well region 106 and / or the substrate 102, and a collector formed by the N-type well region 104.

[0090] If either of the PN junctions in the transistors Q1 / Q2 is forward biased, the PNP transistor Q1 or the NPN transistor Q2 turns on, which can cause unwanted latching in the SRAM cell 10 and, in some cases, even permanently damage the SRAM cell 10.

[0091] In Figure 2B the NMOS transistor MN and the PMOS transistor MP are separated by an isolation region 114 (or isolation structure 114, or isolation layer 114), such as a shallow trench isolation (STI). In addition, a gate cut structure 172 (e.g., Figure 1 172a and / or 172b in

[0092] In some embodiments, the gate cut structure 172 forms a barrier between the collector of the parasitic NPN transistor Q2 and the base of the parasitic PNP transistor Q1 and between the collector of the parasitic PNP transistor Q1 and the base of the parasitic NPN transistor Q2. The selection of the refill material of the gate cut structure 172 may be important because the refill material has an impact on the strength of the first leakage current I1 from the N+ region 135 to the N-type well region 104 and / or the second leakage current I2 from the P+ region 132 to the P-type well region 106.

[0093] In some embodiments, the gate cut structure 172 includes a refill material having a positive charge, such as SiN, SiOCN, or SiON. The refill material having a positive charge may induce a negative charge in the N-type well region 104. Due to the increase in the carrier charge density in the N-type well region 104 and the P-type well region 106, the negative charge induced in the N-type well region 104 may increase the first leakage current I1 from the N+ region 135 to the N-type well region 104. The increase in the carrier charge density is associated with the increase in leakage between the N+ region 135 and the N-type well region 104. Therefore, the trigger voltage of the SCR may be reduced due to the increase in the first leakage current I1. If the parasitic PNP transistor Q1 is turned on by the first leakage current I1, the latch of the SRAM cell 10 may be triggered. As will be discussed in further detail below, embodiments of the present disclosure provide a gate cut structure 172 that tends to reduce the carrier charge density in both the N-type well region 104 and the P-type well region 106, thereby suppressing leakage current and improving latch performance.

[0094] Figure 3A , Figure 3B , Figure 3C The following diagrams are respectively shown along the lines of some embodiments of the present disclosure. Figure 1 The cross-sectional view of the SRAM structure of the SRAM cells 10_1 and 10_2 along the cross-sectional lines AA, BB, and CC. Figure 3A , forming a P-type well region 106a and an N-type well region 104a on the substrate 102. In some embodiments, the substrate 102 is a silicon (Si) substrate. An isolation region 114 is formed above the P-type well region 106a and the N-type well region 104a. In some embodiments, the isolation region 114 is a shallow trench isolation (STI) region.

[0095] An inter-layer dielectric (ILD) layer 140 is formed over the isolation region 114. In some embodiments, the inter-layer dielectric layer 140 may be formed of an oxide such as phospho-silicate glass (PSG), borosilicate glass (BSG), boro-phospho-silicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, or the like.

[0096] Gate structures 150a and 150d are formed over the isolation region 114 and are surrounded by the interlayer dielectric layer 140. The gate structure 150a includes a gate electrode layer 154a and a gate dielectric layer 152a, and the gate structure 150d includes a gate electrode layer 154d and a gate dielectric layer 152d. In some embodiments, the gate electrode layers 154a and 154d are made of a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or another suitable material. Gate spacers 128 are formed on the sidewalls of the gate structures 150a and 150d.

[0097] The gate cutting structure 172a may have different heights at different regions of the semiconductor device, such as heights H1 and H2. Figure 3A Depicted in Figure 2B 10. The heights HH1, HH2, and HH3 of the top surface of the reference isolation region 114 are shown in FIG. 10. In some embodiments, a central portion of the gate cut structure 172a that replaces the redundant portions of the gate structures 150b and 150c extends through the isolation region 114 and into the top portion of the substrate (i.e., into the N-type well region 104a and / or the P-type well region 106a). In comparison, other portions of the gate cut structure 172a extend into the isolation region 114 but do not extend into the top portion of the substrate (i.e., above the N-type well region 104a and / or the P-type well region 106a). The different heights H1 and H2 of the individual portions of the gate cut structure 172a are the result of an etching process used in the formation of the gate cut structure 172a. In some embodiments, the isolation region 114 and the gate cut structure 172a are made of different materials.

[0098] refer to Figure 3B , a P-type well region 106a and an N-type well region 104a are formed on the substrate 102. The P-type well region 106a and the N-type well region 104a can also be regarded as the top portion of the substrate 102. Fins 112a and 112b are formed on the P-type well region 106a, and fins 112c and 112d are formed on the N-type well region 104a. An isolation region 114 is formed above the P-type well region 106a and the N-type well region 104a. The fins 112a to 112d are separated by the isolation region 114.

[0099] A gate dielectric layer 152e is formed over the isolation region 114 and the fins 112c and 112d. A gate electrode layer 154e is formed over the gate dielectric layer 152e and is positioned over the top surfaces of the fins 112c and 112d. The gate electrode layer 154e and the gate dielectric layer 152e over the fin 112d form a gate structure for the pull-up transistor PU-2. In addition, a gate dielectric layer 152c is formed over the isolation region 114 and the fins 112a and 112b. The gate electrode layer 154c is formed over the gate dielectric layer 152c and is positioned over the top surfaces of the fins 112b and 112a. The gate electrode layer 154c and the gate dielectric layer 152c over the fins 112a and 112b form a gate structure for the pass gate transistor PG-1. Figure 3B In the embodiment, the gate dielectric layers 152e and 152c are separated by the gate cutting structure 172a, and the gate electrode layers 154e and 154c are separated by the gate cutting structure 172a.

[0100] refer to Figure 3C , a P-type well region 106a and an N-type well region 104a are formed on the substrate 102. Fins 112a and 112b are formed on the P-type well region 106a, and a fin 112d is formed on the N-type well region 104a. An isolation region 114 is formed above the P-type well region 106a and the N-type well region 104a. The fins 112a, 112b, and 112d are separated by the isolation region 114.

[0101] The source / drain structure 130d forms a source / drain region on the fin 112d. In some embodiments, the source / drain structure 130d is a P-type epitaxial structure. The source / drain structure 135b forms a source / drain region on the fin 112b, and the source / drain structure 135a forms a source / drain region on the fin 112a. In some embodiments, the source / drain structures 135a and 135b are N-type epitaxial structures. An interlayer dielectric layer 140 is formed over the isolation region 114, the source / drain structure 130d, and the source / drain structures 135a and 135b.

[0102] In some embodiments, the material of the source / drain structure 130d includes an epitaxial material. The epitaxial material is selected from the group consisting of SiGe, SiGeC, Ge, or a combination thereof. In some embodiments, the material of the source / drain structures 135a and 135b includes an epitaxial material. The epitaxial material is selected from the group consisting of SiP, SiC, SiPC, SiAs, Si, or a combination thereof.

[0103] like Figure 3A and Figure 3BAs shown in , the bottom portion of the gate cut structure 172a extending below the isolation region 114 is separated from the semiconductor material of the top portion of the substrate (i.e., the N-type well region 104a and / or the P-type well region 106a) by the dielectric layer 116. The dielectric layer 116 creates a buffer zone at the interface between the positive charge from the gate cut structure 172a and the semiconductor material of the N-type well region 104a and / or the P-type well region 106a. The buffer zone reduces the attraction to the carrier charge in the well region and suppresses substrate leakage current. In some embodiments, the dielectric layer 116 is an oxide layer such as silicon dioxide formed by passivating the surface of the N-type well region 104a and / or the P-type well region 106a exposed in the CMG trench. The passivation process may be an oxidation process, such as an O2 plasma process, a thermal oxidation process, an in-situ steam generation oxidation process (ISSG), or other oxidation processes. The materials of the dielectric layer 116, the gate cut structure 172a, and the isolation region 114 may be different from each other. Optionally, the dielectric layer 116 and the thin layer below the dielectric layer 116 may be doped with positive charges, such as boron, to neutralize the negative charges close to the gate cut structure 172a. That is, a depletion region is generated at the interface between the dielectric layer 116 and the semiconductor material of the well region. When the distance from the dielectric layer 116 increases, the boron concentration decreases. The depletion region further limits the movement of the negative charges in the well region close to the gate cut structure 172a.

[0104] like Figure 3C As shown in FIG. 1 , in comparison, since the gate cut structure 172 a in the source / drain region does not extend through the isolation region 114, the bottom portion of the gate cut structure 172 a in the source / drain region is not covered by the dielectric layer 116. That is, no dielectric layer 116 is formed at the interface between the gate cut structure 172 a and the isolation region 114 in the source / drain region.

[0105] Figures 4 to 7 and Fig. 9 Illustration of manufacturing according to some embodiments Figure 1 A perspective view of various stages of a semiconductor structure is shown in block 20 . FIG. 8A to FIG. 8C Schematic diagram of a CMG trench during various steps in forming the CMG trench according to some embodiments. Figure 7 A cross-sectional view of the semiconductor structure shown in FIG.

[0106] like Figure 4As shown in , the substrate 102 includes a first type well region 104a and a second type well region 106a. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Additionally or alternatively, the substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0107] The first type well region 104a and the second type well region 106a can be formed by doping different types of dopants in the substrate 102. In some embodiments, the first type well region 104a is an N-type well region doped with an N-type dopant, and the second type well region 106a is a P-type well region doped with a P-type dopant. In some embodiments, the first type well region 104a includes Si, SiGe, SiGeB, Ge, InSb, GaSb, InGaSb, or the like, and the second type well region 106a includes Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.

[0108] After forming the first type well region 104a and the second type well region 106a, fins 112a to 112e are formed over the substrate. More specifically, according to some embodiments, fins 112a and 112b are formed over the second type well region 106a, and fins 112c, 112d, and 112e are formed over the first type well region 104a. The fins 112a to 112e may be formed by patterning the top portion of the substrate 102. For example, the fins 112a and 112b may be formed by patterning the second type well region 106a, and the fins 112c, 112d, and 112e may be formed by patterning the first type well region 104a. In addition, the fins 112c and 112e are aligned with each other but separated from each other. The fins 112c and 112e may be formed by a fin cutting process, which recesses the middle portion of the originally continuous fin and divides it into a first portion corresponding to the fin 112c and a second portion corresponding to the fin 112e. The fin cutting process may also remove two end portions of the fin 112d, so that the end portions of the fin 112d do not extend beyond the outer gate sidewalls of the dummy gate stacks 122a and 122d.

[0109] After forming the fins 112a to 112e, an isolation structure 114 is formed over the substrate 102, and the fins 112a to 112e are surrounded by the isolation structure 114. The isolation structure 114 may be formed by depositing an insulating layer over the substrate 102 and recessing the insulating layer. In some embodiments, the isolation structure 114 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), or other low-K dielectric materials.

[0110] Next, dummy gate stacks 122a to 122d are formed across the fins 112a to 112e and extend onto the isolation structure 114. More specifically, according to some embodiments, dummy gate stacks 122a and 122b are formed across the fins 112a and 112b above the second-type well region 106a and across the fins 112d and 122e above the first-type well region 104a. In addition, dummy gate stacks 122c and 122d are formed across the fins 112a and 112b on the second-type well region 106a and across the fins 112c and 112d on the first-type well region 104a.

[0111] In some embodiments, the dummy gate stacks 122a to 122d include a gate dielectric layer 124 and a gate electrode layer 126 formed on the gate dielectric layer 124. In some embodiments, the gate dielectric layer 124 is made of silicon oxide. In some embodiments, the gate electrode layer 126 is made of polysilicon.

[0112] refer to Figure 5 After forming the dummy gate stacks 122a to 122d, a gate spacer 128 is formed on the sidewalls of the dummy gate stacks 122a to 122d. In some embodiments, the gate spacer 128 is made of silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or other suitable materials.

[0113] Next, source / drain structures are formed in the fins 112a to 112e adjacent to the dummy gate stacks 122a to 122d. More specifically, above the second-type well region 106a, a source / drain structure 135a is formed in the fin 112a at the opposite side of the dummy gate stacks 122a to 122d, and a source / drain structure 135b is formed in the fin 112b at the opposite side of the dummy gate stacks 122a to 122b. In addition, above the first-type well region 104a, a source / drain structure 130c is formed in the fins 112c and 112e at the opposite side of the dummy gate stacks 122a and 122d, and a source / drain structure 130d is formed in the fin 112d at the opposite side of the dummy gate stacks 122b and 122c. Figure 5 Not shown in Figure 3C (displayed in the figure).

[0114] The source / drain structures 135a, 135b, 130c, and 130d may be formed by recessing the fins 112a to 112e and growing a semiconductor material in the recesses by performing an epitaxial process. The semiconductor material may include Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs, In GaAs, SiGe, SiGeB, Ge, InSb, GaSb, InGaSb, or the like.

[0115] After forming the source / drain structures 135a, 135b, 130c, and 130d, an inter-layer dielectric (ILD) layer 140 is formed around the dummy gate stacks 122a to 122d to cover the source / drain structures 135a, 135b, 130c, and 130d and the isolation structure 114. The ILD layer 140 may include multiple layers made of a plurality of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), and / or other suitable low-k dielectric materials. The ILD layer 140 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0116] Still reference Figure 5 After forming the ILD layer 140, the dummy gate stacks 122a to 122d are replaced by metal gate stacks 142a to 142d. In some embodiments, the metal gate stacks 142a to 142d include a gate dielectric layer 144 and a gate electrode layer 146, respectively. In some embodiments, the gate dielectric layer 144 is made of a high-k dielectric material such as a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, or a metal oxynitride. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, or other suitable dielectric materials. In some embodiments, the gate electrode layer 146 is made of a conductive material such as aluminum, copper, tungsten, titanium, tantalum, or other suitable materials. The metal gate stacks 142a to 142d may further include a work function layer (not shown) between the gate dielectric layer 144 and the gate electrode layer 146, so that the metal gate stacks 142a to 142d may have an appropriate work function value.

[0117] refer to Figure 6 , a mask layer 148 is formed to cover the metal gate stacks 142a to 142d and the ILD layer 140. In addition, according to some embodiments, the mask layer 148 includes an opening 160 that exposes portions of the metal gate stacks 142b and 142c that are designed to be cut (e.g., removed) in a subsequent etching process. The opening 160 exposes the metal gate stacks 142b and 142c and portions of the gate spacers 128, as well as portions of the ILD layer 140 between and adjacent to the exposed portions of the metal gate stacks 142b and 142c. In some embodiments, the mask layer 148 is made of silicon nitride, silicon oxynitride, silicon oxide, titanium nitride, silicon carbide, one or more other applicable materials, or a combination thereof. The mask layer 148 can be formed by depositing a dielectric layer using a spin coating process, a CVD process, a PVD process, or other applicable processes and patterning the dielectric layer through an opening in a photoresist layer (not shown) formed above the dielectric layer.

[0118] refer to Figure 7 After forming the mask layer 148, the opening 160 of the mask layer 148 etches through the exposed portion of the metal gate stacks 142b and 142c and the exposed portion of the ILD layer 140 to form a recess 162. The recess 162 is also referred to as a CMG trench. In some embodiments, the portion of the metal gate stacks 142b and 142c, the gate spacer 128, and the ILD layer 140 exposed by the opening 160 of the mask layer 148 are etched in the etching process. The etching process for removing the exposed metal gate stacks 142b and 142c may include a two-step etching process, wherein a first etching step is applied before the recess 162 reaches the isolation region 114, and a second etching step is applied for over-etching into the isolation region 114, thereby ensuring that the redundant portions of the metal gate stacks 142b and 142c are removed.

[0119] Fig. 8A The diagram is along Figure 7 , during a first etching step 156a in a two-step etching process. The first etching step 156a may have a higher etching selectivity to the dielectric material of the ILD layer 140 and the isolation region 114 than to the metal material of the redundant portion of the metal gate stacks 142b and 142c. The first etching step 156a may terminate at a shallow layer close to the top surface of the isolation region 114, or terminate when the top surface of the isolation region 114 is almost not exposed in the recess 162. Figure 8B The diagram is along Figure 7, at the end of the second etching step 156b in the two-step etching process. The second etching step 156b may have a higher etching selectivity to the metal material of the redundant portion of the metal gate stacks 142b and 142c than to the dielectric material of the ILD layer 140 and the isolation region 114. By switching from a relatively strong first etching step to a relatively weak second etching step, the two-step etching process controls the depth of the recess 162 without excessively extending into the underlying well region, which helps to mitigate substrate leakage current and improve latch-up performance.

[0120] In some embodiments, the first etching step 156a includes a cyclic process, wherein each cycle includes a dry etching process and a cleaning process. The dry etching in each cycle can be performed using a process gas selected from (but not limited to) Cl2, BCl3, Ar, and combinations thereof. The cleaning process can be a plasma cleaning process, such as a plasma including nitrogen (N2) and hydrogen (H2). Nitrogen is used to destroy or bombard some bonds in the residue remaining on the sidewalls and bottom of the groove 162. Hydrogen is used to reduce the residue by using hydrogen as a reducing agent. Depending on the depth of the groove 162 required before reaching the isolation region 114, the cycle of the dry etching process and the cleaning process can be repeated two to ten times.

[0121] In some embodiments, the second etching step 156b includes a single etching operation and a single cleaning process. That is, the second etching step 156b does not include a cyclic process. Without using a cyclic process, the second etching step 156b controls the depth of the groove 162 to prevent it from extending too far into the well region below. The single etching operation may be a dry etching process. To further mitigate the second etching step 156b, an appropriate etching gas is used to perform the etching so that during the etching process, a C-type layer such as a C-type layer may be formed on the sidewall of the groove 162. x H y (where X and Y are integers). The polymer protects the exposed sidewalls of the recess 162 from being over-etched. After the dry etching operation, the polymer can then be removed, for example, using oxygen (O2).

[0122] Since the first etching step 156a is a cyclic process and the second etching step 156b includes a single etching operation, the two-step etching process can be referred to as an "N+1" etching process. The number "N" represents the number of repetitions of the cyclic process, such as from two to ten. The number "1" represents a single etching operation after the cyclic process. In some embodiments, the second etching step 156b produces polymers as byproducts on the sidewalls of the groove 162, while the first etching step 156a does not substantially produce polymer byproducts. In some embodiments, the etching operation during the second etching step 156b is generally weaker than the etching operation during the first etching step 156a.

[0123] Still reference Figure 8B , although the sidewalls of the recess 162 are depicted as being substantially straight, due to differences in etching rates of different materials, the resulting sidewalls of the recess 162 may not be straight and may appear tapered. Portions of the isolation structure 114 below the opening 160 and upper portions of the first type well region 104a and the second type well region 106a are also etched, so that the recess 162 further extends through the isolation structure 114 and into the first type well region 104a and the first type well region 106a, as depicted. Alternatively, the "N+1" etching process may control the recess 162 so as not to extend through the isolation structure 114 and expose the first type well region 104a and the second type well region 106a.

[0124] In some embodiments, the recess 162 is formed above the interface between the first type well region 104a and the second type well region 106a, and the interface between the first type well region 104a and the second type well region 106a is exposed through the recess 162. In addition, since the etching rate of the etching process used to form the recess 162 toward the metal gate stacks 142b and 142c is generally greater than the etching rate toward the ILD layer 140 and the isolation region 114, the bottom of the recess 162 initially under the metal gate stacks 142b and 142c is lower than the bottom of the recess 162 initially under the gate spacer 128 and the ILD layer 140, so that the bottom portion of the isolation region 114 remains in the recess 162. However, although the portion of the recess 162 initially under the metal gate stacks 142b and 142c is relatively deep, the recess 162 does not penetrate the first type well region 104a and the second type well region 106a. That is, according to some embodiments, the bottom of the groove 162 is higher than the bottom surfaces of the first-type well region 104 a and the second-type well region 106 a .

[0125] refer to Figure 8C After forming the groove 162, a dielectric layer 116 is selectively formed on the exposed surfaces of the first-type well region 104a and the second-type well region 106a through a passivation process 158. The dielectric layer 116 is formed on the gate cutting structure 172a (eg, Fig. 9A buffer region is generated at the interface between the positive charge (as shown) and the semiconductor material of the first-type well region 104a and the second-type well region 106a. The buffer region reduces the attraction to the carrier charges in the well regions and suppresses substrate leakage current. In some embodiments, the dielectric layer 116 is formed by oxidizing the surface of the semiconductor substrate in the groove 162 such that the surface layers of the exposed first-type well region 104a and second-type well region 106a become oxide layers, such as an oxide layer of silicon dioxide. Thus, the passivation process 158 is an oxidation process. In some embodiments, the passivation process 158 can be an O2 plasma process, a thermal oxidation process, an in-situ steam generation oxidation process (ISSG), or other oxidation processes. In an embodiment, the O2 plasma treatment is performed at a temperature from ambient temperature to 300 °C. In an embodiment, a low-temperature annealing is performed at a temperature of 500 - 800 °C under high pressure. The O2 / N2 can be tuned from pure O2 to an O2 / N2 partial pressure ratio of approximately 1%. The formation of the dielectric layer 116 can reduce the opening of the bottom portion of the groove 162 below the isolation region 114 from the opening width W1 to a reduced opening width W2, i.e., W2 < W1, as Figure 8C depicted in.

[0126] In some embodiments, the plasma treatment includes applying a dopant into the dielectric layer 116. In some embodiments, the dopant can include fluorine, boron, nitrogen, phosphor, or the like. The dopant implantation process can be used to modify the properties of the dielectric layer 116, thereby correspondingly adjusting the junction profile in the substrate 102. The dopant implantation process also generates a thin layer of depletion region below the dielectric layer 116. In some embodiments, the dopant implantation process neutralizes the carrier charges adjacent to the gate cut structure 172a to be formed. That is, a depletion region is generated at the interface between the dielectric layer 116 and the semiconductor material of the well region. The depletion region further restricts the movement of the carrier charges in the well region adjacent to the gate cut structure 172a to be formed. In one embodiment, the dopant is boron, and the boron concentration decreases further away from the dielectric layer 116.

[0127] After that, according to some embodiments, a gate cut structure 172a is formed in the groove 162, and the mask layer 148 is removed to form the semiconductor structure 100, as Fig. 9 shown in. The above FIG. 3A to FIG. 3C is also respectively along Fig. 91 is a cross-sectional view of the semiconductor structure 100 along the section lines AA, BB, and CC. In some embodiments, the gate cutting structure 172a is formed by depositing a dielectric material to fill the groove 162, and grinding the dielectric material until the top surface of the ILD layer 140 is exposed. In some embodiments, the gate cutting structure 172a (and the gate cutting structure 172b) is made of a nitrogen-containing material such as SiN, SiOCN, and SiON. In some alternative embodiments, the gate cutting structure 172a (and the gate cutting structure 172b) is a multi-layer structure such as FIG. 10A to FIG. 10C As shown in FIG. 10A to FIG. 10C The alternative embodiment shown in FIG. 3A to FIG. 3C One difference is that FIG. 10A to FIG. 10C The gate cutting structure 172a in the embodiment includes a blanket deposited first dielectric layer 172a-1 (e.g., a SiN layer having a uniform thickness) as a liner layer and a second dielectric layer 172a-2 (e.g., a SiO2 layer) as a main dielectric layer over the first layer 172a-1. In addition, according to various other embodiments of the present disclosure, as follows FIG. 11A to FIG. 13C The gate cut structure 172a depicted in FIG. 1 may similarly be a single-layer or multi-layer structure.

[0128] As before Figure 1 As shown in FIG. 1 , gate cutting structures (eg, gate cutting structures 172 a and 172 b ) may be formed to separate the metal gate stacks 142 a to 142 d into various gate structures. FIG. 3A to FIG. 9 Only the gate cut structure 172a is shown. More specifically, the metal gate stack 142b is cut to form gate structures 150b and 150f separated by the gate cut structure 172a, and the metal gate stack 142c is cut to form gate structures 150c and 150e separated by the gate cut structure 172a. In addition, according to some embodiments, the metal gate stacks 142a and 142d are also cut ( FIG. 3A to FIG. 9 Not shown in Figure 1 144) to form gate structures 150a and 150d. In some embodiments, the gate structures 150a, 150b, 150c, 150d, 150e, and 150f include gate dielectric layers 152a, 152b, 152c, 152d, 152e, and 152f (i.e., gate dielectric layer 144) and gate electrode layers 154a, 154b, 154c, 154d, 154e, and 154f (i.e., gate electrode layer 146), respectively.

[0129] refer to FIG. 3A to FIG. 3C and Fig. 9, the gate cutting structure 172a penetrates the isolation region 114 and extends into the first type well region 104a and the second type well region 106a at the position where the redundant portions of the metal gate stacks 142b and 142c are removed. Alternatively, FIG. 11A to FIG. 11C An alternative embodiment is shown in which the "N+1" etching process controls the depth of the recess 162 so that the gate cutting structure 172a does not penetrate the isolation region 114. Since the first type well region 104a and the second type well region 106a are not exposed, the formation of the dielectric layer 116 and the dopant implantation can be selectively skipped. The etching of the recess 162 can be controlled by time to control the depth of the recess 162.

[0130] FIG. 12A to FIG. 12C Another embodiment is shown, in which an etch stop layer (ESL) 118 is formed under the isolation region 114 to prevent the recess 162 from extending into the first type well region 104a and the second type well region 106a. In some embodiments, after the top portion of the substrate 102 is patterned to form the fins 112, the ESL 118 is formed by depositing a dielectric material in the trenches between the fins 112 and then recessing the dielectric material to expose the top portions of the fins 112. Then, the isolation region 114 is formed over the ESL 118. In an embodiment, ESL 118 may include SiN, SiCN, SiON, the like, or a combination thereof, and may be formed by atomic layer deposition (ALD), molecular layer deposition (MLD), a furnace process, CVD, plasma-enhanced CVD (PECVD), plasma-enhanced silicon nitride (PESiN), the like, or a combination thereof. In an embodiment, ESL 118 may be formed to have a thickness of about 3 nm to about 10 nm. ESL 118 includes a different material composition than isolation region 114. The etchant applied in the second etching step in the "N+1" etching process is selected so that ESL 118 remains substantially intact after etching of isolation region 114. FIG. 12A to FIG. 12C As shown in FIG. 1 , ESL 118 allows over-etching of isolation region 114 and the resulting recess 162 has substantially the same thickness at different portions (ie, H1=H2). Since the first-type well region 104a and the second-type well region 106a are not exposed, the formation of dielectric layer 116 and dopant implantation can be selectively skipped.

[0131] FIG. 13A to FIG. 13CAnother embodiment is shown in which a trench 120 is formed at the interface of the first type well region 104a and the second type well region 106a before forming the isolation region 114. In some embodiments, after the top portion of the substrate 102 is patterned to form the fin 112, the trench 120 is formed by further patterning the substrate 102 at the interface of the first type well region 104a and the second type well region 106a in a separate lithography and etching process. Subsequently, the isolation region 114 is formed. The trench 120 allows individual portions of the isolation region 114 to be thicker. Therefore, even though the two-step etching process may extend the recess 162 below the bottom surface of the isolation region 114 in the region outside the trench 120, the recess 162 still does not penetrate the isolation region 114 at the location of the trench 120. Therefore, the gate cut structure 172a does not have physical contact with the underlying well region. Since the first type well region 104a and the second type well region 106a are not exposed, the formation of the dielectric layer 116 and the implantation of dopants can be selectively skipped. The etching of the recess 162 can be controlled by time to control the depth of the recess 162.

[0132] Fig.14 According to some embodiments, a method for manufacturing FIG. 3A to FIG. 13C 1. The method 200 of the embodiment of the present invention is a flowchart of an example method 200 of a semiconductor structure (or semiconductor device) 100 shown in FIG. The operations may be performed in a different order, or not performed at all, depending on the specific application. It should be noted that the method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after the method 200, and some other processes may only be briefly described herein.

[0133] At operation 202, method 200 patterns a top portion of substrate 102 to form fins 112. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing for the production of patterns having, for example, a smaller pitch than that obtainable using a single direct optical lithography process. For example, in an embodiment, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. At operation 204, method 200 may optionally further recess the top portion of substrate 102 to form a trench 120 ( Fig. 13B and Fig. 13C At operation 206, isolation regions 114 are formed between the fins 112. Optionally, an ESL 118 may be formed below the isolation regions 114. FIG. 12A to FIG. 12C ). At operation 208, a dummy gate stack 122 is formed across the fin 112. At operation 210, source / drain structures 130 and 135 are formed in the fin 112 in the source / drain region. At operation 212, an ILD layer 140 is formed between the dummy gate stacks 122. At operation 214, the dummy gate stack 122 is replaced by a metal gate stack 142. At operation 216, a two-step etching process is performed to remove redundant portions of the metal gate stack to form a CMG trench 162. Depending on whether the trench 120 and / or the ESL 118 are optionally formed, the CMG trench 162 may or may not penetrate the isolation region 114 in various embodiments. At operation 218, if the N-type well region and / or the P-type well region are exposed in the CMG trench 162, a dielectric layer 116 is selectively formed on the exposed surface of the respective well region. Optionally, a dopant implantation process may be performed to create a depletion region under the dielectric layer 116. At operation 220, a dielectric material is deposited in the CMG trench 162 to form a gate cut structure 172.

[0134] A plurality of embodiments for a semiconductor structure are provided. A PMOS transistor formed in an N-type well region is separated from an NMOS transistor formed in a P-type well region by an isolation region (e.g., STI). A dielectric structure is formed at a boundary (or junction, interface) between the P-type well region and the N-type well region as a gate cut structure. Various exemplary configurations of the gate cut structure disclosed herein tend to suppress substrate leakage current between the P-type well region and the N-type well region, thereby improving the latch performance of the semiconductor structure.

[0135] In an exemplary embodiment, the present disclosure relates to a method for forming a semiconductor structure. The method includes forming a fin above a semiconductor substrate, forming an isolation region on the sidewall of the fin, forming a metal gate above the fin and the isolation region, etching the metal gate to form a groove passing through the isolation region, the groove exposing the top portion of the semiconductor substrate, passivating the top portion of the semiconductor substrate to form a dielectric layer at the bottom of the groove, and depositing a dielectric material in the groove to form a dielectric structure, the dielectric structure dividing the metal gate into two parts. In some embodiments, passivating the top portion of the semiconductor substrate is an oxidation process, and the dielectric layer is an oxide layer. In some embodiments, the oxidation process is an O2 plasma process. In some embodiments, the groove is directly above the interface between the N-type well region and the P-type well region of the semiconductor substrate. In some embodiments, the method also includes, after etching the metal gate to form the groove, implanting a dopant into the top portion of the semiconductor substrate through the groove. In some embodiments, the dopant is boron. In some embodiments, the implantation of the dopant produces a depletion region below the dielectric layer. In some embodiments, the etching of the metal gate includes a first etching step and a second etching step different from the first etching step. In some embodiments, the first etching step comprises a cyclic etching operation and the second etching step comprises a single etching operation. In some embodiments, the second etching step produces polymer byproducts and the first etching step does not produce polymer byproducts.

[0136] In another exemplary embodiment, the present disclosure relates to a method for forming a semiconductor structure. The method includes patterning a top portion of a substrate to form a first fin and a second fin, recessing a region of the substrate between the first fin and the second fin to form a trench, the trench exposing an interface between a first-type well region and a second-type well region of the substrate, the first-type well region and the second-type well region having opposite conductivity types, depositing an isolation layer between the first fin and the second fin and filling the trench, forming a metal gate over the first fin and the second fin, etching the metal gate to form a groove passing through the metal gate and extending into the trench, and depositing a dielectric material in the groove to form a dielectric structure, the dielectric structure dividing the metal gate into a first portion over the first fin and a second portion over the second fin. In some embodiments, the bottommost portion of the dielectric structure is separated from the first-type well region and the second-type well region by a portion of the isolation layer in the trench. In some embodiments, the method also includes forming a first epitaxial structure on the first fin and forming a second epitaxial structure on the second fin. The first portion of the dielectric structure laterally located between the first portion and the second portion of the metal gate has a first height, the second portion of the dielectric structure laterally located between the first epitaxial structure and the second epitaxial structure has a second height, and the first height is greater than the second height. In some embodiments, the etching of the metal gate includes a first etching step and a second etching step that is weaker than the first etching step. In some embodiments, the first etching step includes a cyclic etching operation and the second etching step includes a single etching operation. In some embodiments, the first portion of the metal gate and the first fin form a pass gate transistor of the memory cell, and the second portion of the metal gate and the second fin form a pull-up transistor of the memory cell.

[0137] In yet another exemplary embodiment, the present disclosure relates to a semiconductor device. The semiconductor device includes a first gate electrode of a first fin across a first type well region of a semiconductor substrate; a second gate electrode of a second fin across a second type well region of the semiconductor substrate, the first type well region and the second type well region having opposite conductivity types; an isolation layer disposed above the semiconductor substrate and on the sidewalls of the first fin and the second fin; a gate cut structure separating the first gate electrode from the second gate electrode, the gate cut structure extending through the isolation layer; and a dielectric layer disposed on the gate cut structure and separating the gate cut structure from the semiconductor substrate, the dielectric layer being below the bottom surface of the isolation layer. In some embodiments, the semiconductor device also includes a depletion region stacked between the dielectric layer and the semiconductor substrate. In some embodiments, the dielectric layer and the depletion region are implanted with boron. In some embodiments, the gate cut structure has a first portion directly above the isolation layer and a second portion directly above the interface between the first type well region and the second type well region, the first portion having a first height, and the second portion having a second height greater than the first height.

[0138] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first gate electrode across a first fin above a first type well region of a semiconductor substrate; a second gate electrode across a second fin above a second type well region of the semiconductor substrate, wherein the first type well region and the second type well region have opposite conductivity types; a gate cut structure separating the first gate electrode from the second gate electrode; and an oxide layer disposed between the gate cut structure and the semiconductor substrate. In some embodiments, the semiconductor substrate has a recess, and the gate cut structure extends into the recess. In some embodiments, the semiconductor device further includes an isolation layer disposed above the semiconductor substrate and between the first fin and the second fin, and the oxide layer is below the bottom surface of the isolation layer.

[0139] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first gate electrode of a first fin across a first type well region of a semiconductor substrate; a second gate electrode of a second fin across a second type well region of the semiconductor substrate, wherein the first type well region and the second type well region have opposite conductivity types; an isolation layer disposed above the semiconductor substrate and on multiple sidewalls of the first fin and the second fin; a gate cut structure separating the first gate electrode from the second gate electrode, wherein the gate cut structure has a first portion directly above the isolation layer and a second portion directly above a surface between the first type well region and the second type well region, the first portion having a first height, and the second portion having a second height greater than the first height. In some embodiments, the second portion extends through the isolation layer and into the semiconductor substrate. In some embodiments, the semiconductor device further includes a dielectric layer disposed between the second portion and the semiconductor substrate.

[0140] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A first gate electrode straddling a first fin above a first type well region of a semiconductor substrate; A second gate electrode straddling a second fin above a second type well region of the semiconductor substrate, wherein the first type well region and the second type well region have opposite conductivity types; An isolation layer disposed above the semiconductor substrate and on a plurality of sidewalls of the first fin and the second fin; a gate cutting structure separating the first gate electrode from the second gate electrode, wherein the gate cutting structure extends through the isolation layer; and A dielectric layer is disposed on the gate cutting structure and separates the gate cutting structure from the semiconductor substrate, wherein the dielectric layer is below a bottom surface of the isolation layer.

2. The semiconductor device according to claim 1, wherein Further including: A depletion region is stacked between the dielectric layer and the semiconductor substrate.

3. The semiconductor device according to claim 2, wherein: The dielectric layer and the depletion region are implanted with boron.

4. The semiconductor device according to claim 1, wherein: The gate cutting structure has a first portion directly on the isolation layer and a second portion directly on an interface between the first type well region and the second type well region, the first portion has a first height, and the second portion has a second height greater than the first height.

5. A semiconductor device, characterized in that: Include: A first gate electrode straddling a first fin above a first type well region of a semiconductor substrate; A second gate electrode straddling a second fin above a second type well region of the semiconductor substrate, wherein the first type well region and the second type well region have opposite conductivity types; A gate cutting structure separating the first gate electrode from the second gate electrode; and An oxide layer is disposed between the gate cutting structure and the semiconductor substrate.

6. The semiconductor device according to claim 5, wherein: The semiconductor substrate has a recess, and the gate cutting structure extends into the recess.

7. The semiconductor device according to claim 5, wherein: The invention also comprises an isolation layer which is arranged above the semiconductor substrate and between the first fin and the second fin, and the oxide layer is below a bottom surface of the isolation layer.

8. A semiconductor device, characterized in that: Include: A first gate electrode straddling a first fin above a first type well region of a semiconductor substrate; A second gate electrode straddling a second fin above a second type well region of the semiconductor substrate, wherein the first type well region and the second type well region have opposite conductivity types; An isolation layer disposed above the semiconductor substrate and on a plurality of sidewalls of the first fin and the second fin; A gate cutting structure is provided for separating the first gate electrode from the second gate electrode, wherein the gate cutting structure has a first portion directly on the isolation layer and a second portion directly on an interface between the first type well region and the second type well region, the first portion has a first height, and the second portion has a second height greater than the first height.

9. The semiconductor device according to claim 8, wherein: The second portion extends through the isolation layer and into the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein: The device also comprises a dielectric layer disposed between the second portion and the semiconductor substrate.

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