M.2 signal integrity test fixture supporting PCIe5.0

Abstract

The utility model provides an M.2 signal integrity test fixture supporting PCIe5.0, and relates to the technical field of test fixtures. The M.2 signal integrity test fixture supporting PCIe5.0 comprises a fixture body, the fixture body is provided with a plug-in structure, an MMPX connector and an RX signal connector, the plug-in structure is used for connecting an M.2 interface, the MMPX connector is used for leading out a signal to be tested and is connected with a high-speed oscilloscope, and the RX signal connector is used for being connected with a PCIe trigger clock switching device. According to the PCIe 5.0 standard test fixture, the plugging structure used for being connected with the M.2 interface is arranged, connection with the M.2 interface can be achieved, in addition, the MMPX connector is adopted, the signal frequency as high as 67 G is supported, the stability and accuracy of high-speed data transmission are guaranteed, the signal test requirement of the PCIe 5.0 standard is met, and therefore the requirements of the test fixture for the PCIe 5.0 standard and the M.2 interface at the same time are met.

Description

Technical Field

[0001] The utility model relates to the technical field of test fixtures, in particular to an M.2 signal integrity test fixture supporting PCIe5.0. Background Art

[0002] In the rapid development of the communications field, PCIe bus, as a mainstream data interface, has evolved and upgraded from version 1.0 to version 5.0, and its transmission rate has increased from the initial 2.5G / s to the current 32G / s, and the bandwidth demand has continued to increase. As the rate of the PCIe bus increases, the testing and verification of signal integrity becomes critical to ensure the high quality and stable performance of the product.

[0003] The current mainstream PCIe test fixtures in the market mainly support the testing requirements of standard slot forms, but the demand for test fixtures that support the PCIe 5.0 standard and PCIe 5.0 test fixtures for the M.2 interface form is far from being fully met. As the PCIe bus rate continues to increase, the challenges faced by traditional PCIe test fixtures include the increase in signal frequency, the expansion of bandwidth, and the stability and reliability of high-speed data transmission.

[0004] In the prior art, most test fixtures for high-speed signal transmission are designed to support lower versions of the PCIe standard, and there is no perfect solution for the requirements of the PCIe 5.0 standard and the M.2 interface. The limitations of the prior art are mainly reflected in the inability to fully meet the high-speed data transmission requirements under the PCIe 5.0 standard and the inability to provide support for the test requirements of the M.2 interface. Utility Model Content

[0005] The purpose of the utility model is to provide an M.2 signal integrity test fixture supporting PCIe5.0, so as to solve the problem raised in the above background technology: in the prior art, test fixtures for high-speed signal transmission are mostly designed to support low-version PCIe standards, and there is no perfect solution for the requirements of PCIe 5.0 standard and M.2 interface. The limitations of the prior art are mainly manifested in the inability to fully meet the high-speed data transmission requirements under the PCIe5.0 standard, and the inability to provide support for the test requirements of the M.2 interface form.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present disclosure, there is provided an M.2 signal integrity test fixture supporting PCIe5.0, characterized in that it includes: a fixture body, on which a plug-in structure, an MMPX connector and an RX signal connector are provided, the plug-in structure is used to connect the M.2 interface, the MMPX connector is used to lead out the signal to be tested and connect to a high-speed oscilloscope, and the RX signal connector is used to connect to a PCIe trigger clock switching device.

[0007] In a possible implementation, the fixture body uses an ultra-low loss plate.

[0008] In a possible implementation, the MMPX connector provided on the fixture body is a female MMPX connector.

[0009] In a possible implementation, the MMPX connector female head is connected to the PCIe trigger clock switching device via a cable with an MMPX connector male head.

[0010] In a possible implementation, the size of the fixture body is 22 mm x 80 mm.

[0011] In a possible implementation, the fixture body includes two fixture boards, wherein the 100M reference clock on the M.2 interface is given to the two fixture boards, and the PCIe x4 signals lane0~1 and lane2~3 on the M.2 interface are respectively given to the two fixture boards.

[0012] The above one or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:

[0013] An M.2 signal integrity test fixture supporting PCIe5.0 provided in an embodiment of the utility model can achieve connection with the M.2 interface by providing a plug-in structure for connecting the M.2 interface. In addition, by adopting an MMPX connector, it supports a signal frequency of up to 67G, ensures the stability and accuracy of high-speed data transmission, and meets the signal testing requirements of the PCIe 5.0 standard, thereby realizing the test fixture's requirements for both the PCIe 5.0 standard and the M.2 interface.

[0014] The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the module structure of an M.2 signal integrity test fixture supporting PCIe5.0 provided in an embodiment of the present application.

[0016] Description of the accompanying drawings: 100, fixture body; 110, plug-in structure; 120, MMPX connector; 130, RX signal connector; 200, high-speed oscilloscope; 300, PCIe trigger clock switching device; 400, device under test. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0018] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of structures and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0019] See also Figure 1 The M.2 signal integrity test fixture supporting PCIe5.0 includes:

[0020] A fixture body 100 is provided with a plug-in structure 110, an MMPX connector 120 and an RX signal connector 130. The plug-in structure 110 is used to connect to the M.2 interface, the MMPX connector 120 is used to lead out the signal to be tested and connect to the high-speed oscilloscope 200, and the RX signal connector 130 is used to connect to the PCIe trigger clock switching device 300.

[0021] Specifically, by providing a plug-in structure 110 for connecting the M.2 interface, connection with the M.2 interface can be achieved. In addition, by adopting the MMPX connector 120, it supports a signal frequency of up to 67G, ensures the stability and accuracy of high-speed data transmission, and meets the signal testing requirements of the PCIe 5.0 standard, thereby realizing the test fixture's requirements for both the PCIe 5.0 standard and the M.2 interface.

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the utility model clearer, the technical solution in the embodiments of the utility model will be described clearly and completely in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] The fixture body 100 refers to the main body or main part of the test fixture, and plays an important role in connecting and supporting other test components.

[0024] Furthermore, the fixture body 100 uses ultra-low loss plates. Specifically, due to the excellent material properties and manufacturing process of ultra-low loss plates, the impedance consistency is very high, with a deviation within 5%, which means that during the signal transmission process, the impedance of each component remains stable and the impedance matching is high, ensuring the accuracy and reliability of signal transmission. At the same time, ultra-low loss plates have extremely low insertion loss, which can minimize the energy loss in signal transmission and ensure high-quality signal transmission.

[0025] Furthermore, the size of the fixture body 100 is 22 mm x 80 mm. Specifically, the fixture body 100 of this size is small and convenient, suitable for a variety of application environments, and is not prone to structural interference.

[0026] Furthermore, the fixture body 100 includes two fixture boards, wherein the 100M reference clock on the M.2 interface is given to the two fixture boards, and the PCIe x4 signal lanes 0-1 and lanes 2-3 on the M.2 interface are given to the two fixture boards respectively. Specifically, the 100M reference clock on the M.2 interface is transmitted to the two fixture boards respectively, ensuring the accuracy and synchronization of this key reference clock signal in the entire test system. At the same time, lanes 0-1 and lanes 2-3 of the PCI Express x4 (PCIe x4) signal on the M.2 interface are also transmitted to the two fixture boards respectively. This distribution method can effectively manage and separate different signal channels, improving the efficiency and reliability of signal transmission.

[0027] The plug-in structure 110 plays an important role in connecting the M.2 interface of the device under test 400. Through the plug-in structure 110, the fixture body 100 can be accurately connected to the M.2 interface to achieve signal transmission and data acquisition. The design of the plug-in structure 110 must match the M.2 interface standard.

[0028] MMPX connector 120 refers to a connector with the model number MMPX, which is used to connect high-speed signal transmission and test equipment. MMPX connector 120 generally has the characteristics of high-frequency transmission and strong anti-interference. MMPX connector 120 supports signal frequencies up to 67G and is suitable for high-speed data transmission and test environments. Through MMPX connector 120, the high-speed oscilloscope 200 can be accurately connected to the signal source to be tested, to achieve accurate acquisition and analysis of signal waveforms and characteristics, and meet the signal test requirements of the PCIe 5.0 standard.

[0029] Furthermore, the MMPX connector 120 provided on the fixture body 100 is a female MMPX connector.

[0030] Furthermore, the MMPX connector female head is connected to the PCIe trigger clock switching device 300 via a cable with an MMPX connector male head.

[0031] The RX signal connector 130 is a connector for connecting and receiving RX signals. In the M.2 interface signal integrity test fixture supporting PCIe 5.0, the RX signal connector 130 plays an important role in connecting the test equipment and receiving the signal.

[0032] High-speed oscilloscope 200 refers to an instrument or device used for collecting, displaying and analyzing high-speed signals. It can be understood that high-speed oscilloscopes are usually used to measure and analyze the waveform, frequency, amplitude and other characteristics of electrical signals, and are particularly suitable for testing and diagnosing high-frequency and high-speed data transmission signals. In the M.2 interface signal integrity test fixture that supports PCIe5.0, the high-speed oscilloscope 200 plays a key role in collecting the signal to be tested, analyzing the waveform and detecting the signal integrity. Through the high-speed oscilloscope 200, the tester can accurately observe and evaluate the characteristics of the signal to be tested to ensure the stability and accuracy of signal transmission.

[0033] The PCIe trigger clock switching device 300 is used to trigger and switch the clock signal in the PCIe (PCI Express) interface test. The device generally includes a clock signal source and a switching controller, which are used to generate an accurate clock pulse signal and switch different clock frequencies and timings according to requirements. By outputting a pulse signal through the PCIe trigger clock switching device 300, it is possible to switch the code types of different PCIe rates. During the test process, the pulse signal can be used as a trigger signal to control the timing and rate of data transmission. By adjusting the frequency and timing of the pulse signal, the PCIe trigger clock switching device 300 can switch the code types of different rates to adapt to different PCIe signal standards and rate requirements. For example, when it is necessary to test a PCIe signal supporting different rates, the pulse signal output by the PCIe trigger clock switching device 300 can switch between different code types to adapt to data transmission at different rates. This flexible switching function can ensure that the test equipment adapts to a variety of PCIe signal transmission standards, such as PCIe 1.0, 2.0, 3.0, 4.0 or 5.0, thereby achieving accurate testing and analysis at different rates.

[0034] The matters not described in detail in the present invention are all known technologies to those skilled in the art.

[0035] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

Claims

1. A M.2 signal integrity test fixture supporting PCIe5.0, characterized in that: include: A fixture body is provided with a plug-in structure, an MMPX connector and an RX signal connector, the plug-in structure is used to connect the M.2 interface, the MMPX connector is used to lead out the signal to be tested and connect to a high-speed oscilloscope, and the RX signal connector is used to connect to a PCIe trigger clock switching device.

2. The M.2 signal integrity test fixture supporting PCIe5.0 according to claim 1, characterized in that: The fixture body is made of ultra-low loss plate.

3. The M.2 signal integrity test fixture supporting PCIe5.0 according to claim 1, characterized in that: The MMPX connector provided on the fixture body is a female MMPX connector.

4. The M.2 signal integrity test fixture supporting PCIe5.0 according to claim 3, characterized in that: The MMPX connector female head is connected to the PCIe trigger clock switching device via a cable with an MMPX connector male head.

5. The M.2 signal integrity test fixture supporting PCIe5.0 according to claim 1, characterized in that: The size of the fixture body is 22mmx80mm.

6. The M.2 signal integrity test fixture supporting PCIe5.0 according to claim 1, characterized in that: The fixture body includes two fixture boards, wherein the 100M reference clock on the M.2 interface is given to the two fixture boards, and the PCIe x4 signals lane0~1 and lane2~3 on the M.2 interface are respectively given to the two fixture boards.

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