Hot-pluggable memory box
By designing a hot-swap DRAM box that meets the standard SSD dimensions, the problems of hot-swap and on-site maintenance of DRAM modules in the prior art are solved, and the memory capacity expansion and equipment maintenance are achieved.
Patent Information
- Application Number
- CN202420569767.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-28
- Filing Date
- 2024-03-22
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-03-22
AI Technical Summary
The prior art is difficult to implement hot plugging and on-site maintenance of dynamic random access memory (DRAM) modules, which limits the expansion of memory capacity and the maintenance of equipment.
A hot-swap DRAM box that meets the standard SSD form factor is designed, with access panels and integrated edge connectors, supporting PCIe signaling standards, allowing DRAM modules to be removably plugged in and unplugged, and equipment testing and fault identification through field testing units.
It realizes hot-swap and on-site repair of DRAM modules, expands the scalability of memory capacity, and improves the maintainability and reliability of equipment.
Smart Images
Figure CN222883254U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to non-persistent storage systems, and more particularly to dynamic random access memory (DRAM) systems. Background Art
[0002] Dynamic random access memory (DRAM) is a commonly used non-persistent memory device that uses a capacitive storage device to retain data for a short period of time. Utility Model Content
[0003] According to one aspect of the present disclosure, a hot-swappable memory box is provided, comprising: a printed circuit board having an integral edge connector compliant with the Peripheral Component Interconnect Express (PCIe) signaling standard; one or more memory module slots, the one or more memory module slots being fixed to the printed circuit board, each memory module slot having an electrical connector for accommodating a corresponding edge connector of a corresponding dynamic random access memory (DRAM) module, so that one or more DRAM modules can be removably inserted into the one or more memory module slots; and a box housing, the box housing conforming to the solid-state drive (SSD) form factor specified by the standard and having: an opening through which the integral edge connector of the printed circuit board extends so that the hot-swappable memory box can be inserted into the backplane of a rack-mounted computing housing; and an inspection panel, the inspection panel being movable from a closed position to expose the one or more memory module slots. BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Various embodiments disclosed herein are illustrated by way of example and not limitation in the accompanying drawings and in which like reference numerals refer to similar elements and in which:
[0005] Figure 1 An embodiment of a field-serviceable DRAM cartridge having an industry-standard solid-state drive (SSD) form factor and an industry-standard signal / pin-out / connector interface to enable the DRAM cartridge to be removed from or inserted into a continuously powered data center server-computer rack;
[0006] Figure 2 illustrates a replaceable field-repairable DRAM cartridge conforming to an SSD form factor showing additional details regarding components mounted to a cartridge substrate; and
[0007] Figure 3 An exemplary hot unplugging (ie, removal from a server-computer rack while powered on) of a DRAM cartridge and the insertion of an edge connector of the DRAM cartridge into a connector socket of a field test unit are illustrated. DETAILED DESCRIPTION
[0008] In various embodiments herein, a hot-swappable DRAM cassette implemented in a standard SSD form factor has an access panel that opens to enable removal and insertion of plug-in DRAM memory modules. In multiple embodiments, the DRAM cassette is implemented to conform to the form factor, protocol, connector, and pin-out / signal specifications set forth in one or more Enterprise and Datacenter Standard Form Factor (EDSFF) specifications promulgated by the Storage Networking Industry Association (SNIA), including, for example, but not limited to, the form factor specifications set forth in EDSFF standards E3.S, E3.S2T, E3.L, and E3.L 2T. In these and other embodiments, the DRAM cassette houses a memory-buffer integrated circuit along with the plug-in DRAM memory module that communicates with a host computing device via a cache coherent / memory semantic signaling protocol built on a PCIe-compliant physical signaling layer (compliant with one or more Peripheral Component Interconnect Express standard specifications). With this arrangement, the DRAM cartridge appears from the perspective of a host device (e.g., coupled to a root complex of a PCIe link) as a JEDEC memory standard compliant DRAM mount (i.e., compliant with Joint Electron Device Engineering Council SDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc.), and also has (i) hot-swappable connection and disconnection of the cartridge to a backplane or other connector within the host computing device (i.e., the cartridge can be installed or removed without shutting down the host computing device), (ii) expandable memory capacity through post-deployment DRAM module insertion (via an access panel), and (iii) field serviceability (removal / insertion via an access panel). In yet other embodiments, a field tester unit (FTU) can be coupled to the slot connector of a hot-plugged DRAM cartridge (e.g., unplugged from a powered backplane of a data center server rack) to enable device testing - confirming device operability, or otherwise identifying one or more failed components on the DRAM cartridge, including identifying one or more failed DRAM memory modules that can be replaced in the field.
[0009] Figure 1An embodiment of a field-serviceable DRAM cartridge 101 is illustrated having a form factor conforming to the EDSFF E3.S or E3.L SSD standard and a PCIe-compliant signal / pin-out interface (terminated at an edge connector 103) to enable the DRAM cartridge to be removed from or inserted into a continuously powered data center server-computer rack 105 (i.e., the DRAM cartridge 101 can be inserted into or removed from a backplane connector of a server rack while the backplane is powered, and is therefore "hot-swappable"). The edge connector 103 is coupled to a buffer integrated circuit (e.g., a Figure 1The DRAM box 101 is composed of terminals of signal traces of a buffer integrated circuit (implemented by an application-specific integrated circuit (ASIC) not specifically shown in the figure), the buffer integrated circuit having a PCIe-compliant physical signaling interface (PHY) and circuits compliant with one or more cache coherence / memory semantic communication protocols (i.e., receiving and responding to standardized memory read and write requests), the one or more cache coherence / memory semantic communication protocols being layered on the PCIe PHY, including, for example, but not limited to, Compute Express Link (CXL), Gen-Z, and / or OpenCAPI protocols. With this arrangement, the DRAM box 101 appears to one or more processors installed in and / or electrically connected to a server rack (e.g., via an intra-data center network, the Internet, or other wide or local area network) as a conventional DRAM memory controller having one or more JEDEC-compliant DRAM DIMMs (dual in-line memory modules) coupled thereto. Thus, the DRAM box form factor and memory semantic protocol enable virtually unlimited DRAM capacity expansion (e.g., server racks within a data center and other similar server racks can be populated with any number of DRAM boxes 101, up to and including all of each rack instance), while the PCIe PHY enables DRAM boxes to be installed and removed while powered on. In addition, as illustrated in the rack extraction example at 109 (the DRAM box housing includes a dimensional profile that enables the box housing to be secured within an SSD carrier having a standard-compliant form factor, for example, the E3.S / E3.L form factor of the DRAM box enables installation within a server rack via an E3-compliant carrier 111), the DRAM box 101 includes a service panel 115 that opens (e.g., mechanically swings open or lifts off / completely removed) to expose one or more JEDEC-compliant DIMM slots 117 and thereby enables field servicing of the DRAM-carrying DIMMs—replenishing box storage capacity (i.e., by adding additional DRAM DIMMs to unpopulated slots and / or replacing resident DIMMs with higher capacity DIMMs) and / or replacing one or more failed DIMMs as discussed below. In the particular example shown, the DIMM sockets are mounted to a printed circuit board (PCB) - the box "baseboard" - which is primarily disposed within the box housing (i.e., such that the carrier of the plug-in DIMMs is parallel to the box baseboard), and are therefore in a low-profile orientation that enables DIMM population within a housing that complies with the ES.3 or ES.3 2T (or E3.L or E3.L 2T) EDSFF standard. Figure 1In the embodiment of the present invention, two small form factor DIMM sockets 117 (i.e., "SO-DIMM" sockets) are accessible via a maintenance aperture (i.e., an opening achieved by removing panel 115), but in alternative embodiments, more or fewer DIMM sockets may be deployed within DRAM cassette 101, with any number of socket form factors and electrical pinouts (including a variety of different DIMM connectors and / or proprietary form factors / electrical specifications). In one embodiment, the access panel pivots about one or more hinges disposed at the edge of the aperture when moved from the closed position to expose one or more memory module sockets. In another embodiment, the aperture is formed in a first surface of the cassette housing and is covered by the access panel in the closed position, and the access panel slides in a direction parallel to the first surface when moved from the closed position.
[0010] Figure 2 A field-repairable replaceable DRAM cartridge 131 (e.g., having a Figure 1One or more memory module sockets are shown with those sockets rotated 90° - as shown in the alternative cartridge substrate embodiment of exemplary detail views 133 and 135 - so that the DIMM connector is parallel to the DRAM cartridge connector 103 rather than orthogonal), in which example additional details are shown regarding the components mounted to the cartridge substrate 133 / 135. In the depicted example, the substrate mounted CXL buffer IC 141 includes a PCIe interface coupled to the PCB backplane connector 103 (i.e., cartridge connector or substrate connector) and one or more JEDEC compliant memory channels coupled to the one or more memory module sockets and thus to any plug-in DIMMs. The CXL buffer IC 141 (named so herein because of the buffer IC's support for CXL-compliant signaling on a PCIe link, but in alternative embodiments the buffer IC may also support standardized and / or proprietary memory semantics / cache coherence communication protocols other than or in addition to CXL (e.g., Gen-Z, OpenCAPI, etc.)) is coupled to various supporting components via one or more internal signaling paths 145 (only one of which is shown), including, for example, but not limited to, a timing signal IC 146 (e.g., a crystal oscillator or MEMS oscillator and supporting circuits), a digital power management IC 147, a field replacement unit 148, a non-volatile storage device 149 (in the depicted example, such as a flash memory with a quad serial programmable interface (QSPI)), etc. In other embodiments, various additional / alternative components may be mounted to the box substrate and interconnected to the buffer IC 141 and / or other box resident components, including, for example, but not limited to, one or more retimer ICs, signal repeater (re-driver) ICs, clock buffers, FPGAs, CPLDs, volatile and / or non-volatile memory components (e.g., static random access memory, dynamic random access memory, flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM)), and / or any other integrated circuits and / or discrete components that may be deployed to support / supplement DRAM box operations. In an alternative embodiment, the CXL buffer IC and / or other components can be disposed on a face / surface of the box substrate opposite the DRAM slots, thereby providing space for additional DRAM DIMM slots - for example, two additional SO-DIMM slots disposed back-to-back with those shown (i.e., so that two pairs of SO-DIMMs can be installed, with one pair of slots being inserted in an opposite direction to the other pair of slots) - wherein all of the DIMM slots are accessible via a single removable / openable service panel (enlarged relative to the panel shown), via corresponding service panels for each DIMM pair, etc.
[0011] As described above, the various DRAM cartridge embodiments presented herein can support DRAM-bearing memory modules having standardized or proprietary form factors (and electrical interfaces) other than the standardized or proprietary form factors (and electrical interfaces) of JEDEC-compliant DIMMs. Figure 2 An example of one such DRAM module, indicated at 150, is illustrated, in this case having a two-dimensional array of DRAM memory components arranged around a central registered clock driver (RCD) and removably inserted into a two-dimensional memory module (2DMM) socket on substrate 135. The 2DMM socket (e.g., soldered to traces on the DRAM box substrate) is coupled to a buffer IC 141 via one or more JEDEC-compliant or proprietary memory channels. In alternative embodiments, the buffer IC 141 and / or supporting components may be disposed on the back side of the box substrate 135, thereby making room for an additional 2DMM socket. Furthermore, while a single 2DMM socket (and a single 2D memory module) is depicted, in alternative embodiments, a stacked and laterally staggered pair (or more than two) of these sockets may be implemented on one or both sides of the box substrate to enable installation of two or more 2D memory modules within a host DRAM box. More generally, in all embodiments herein, where space permits (e.g., in a housing having double thickness and conforming to EDSFF (e.g., E3.S2T or E3.L 2T)), the memory module slot (or two or more memory module slot groups in the memory module slot) may be disposed on both surfaces of the case substrate. In addition, although not specifically shown, the JEDEC-compliant memory module and / or the proprietary memory module may include one or more data buffer ICs coupled between the data interface of each memory device (or memory device group) and the corresponding one or more data interfaces of the CXL buffer IC 141 (i.e., located within the data path of each or any memory channel).
[0012] Figure 3An exemplary hot unplugging (i.e., removal from the rack 105 while powered on) of a DRAM cartridge is illustrated, along with the insertion of the edge connector (103) of the DRAM cartridge into the connector-slot 161 of a field test unit 163. In the depicted example, the test unit 163 includes a packaged control ASIC 165 (i.e., having a housing 167) having a PCIe interface to issue DRAM read / write commands (as well as any host-level maintenance and / or configuration commands—e.g., the latter for setting page open / page close operation policies, enabling / disabling data encryption, etc.) to the DRAM cartridge 109—in this example via the cable 169 and connector 161—to confirm the proper operation of any and all DRAM modules plugged into the DRAM cartridge 109 and the DIMM interface circuitry (i.e., the CXL buffer IC and / or supporting IC components as discussed above), as needed. The tester unit 163 also includes a wireless interface (e.g., compliant with Bluetooth, near field communication (NFC), WIFI, or other wireless communication standards) that enables wireless communication with a corresponding wireless interface within a handheld or portable computing device, in this example a smartphone 175 executing a tester readout application (“app”), to present status / health information related to the DRAM cartridge on the smartphone display. With this arrangement, a service technician can hot-unplug a DRAM cartridge from a host server rack 105 (e.g., within a data center), insert the DRAM cartridge into the tester 13, and then initiate an operational / memory test (e.g., by executing an application within a smartphone, laptop, dedicated tester device, etc.) to generate readings indicating the pass / fail status of the DRAM cartridge as a whole and the individual DRAM modules plugged into the DRAM cartridge. In the depicted example, the field test application determines (and displays information to the service technician to indicate) that the control circuitry within the DRAM cartridge (i.e., the “control” includes, for example, the CXL buffer IC and other components hard-soldered to the cartridge substrate) and the DRAM DIMM installed in slot 0 are operating normally, and determines that a fault has been detected within the DRAM DIMM installed in slot 1. The tester app can communicate via the Internet or other communications network (conceptually shown as 177) with a remote data center management device / infrastructure 179 that collects statistics and / or other information about the failed DIMMs (e.g., nature of the failure, manufacturer, suspected component type, etc.) and / or provides return material authorization (RMA) information to field repair technicians.More specifically, with respect to the DIMM 1 failure scenario, the service technician may open / remove the service panel on the DRAM cartridge to expose the DIMM arrangement, remove the suspect / failed DIMM reported by the field test app (i.e., failed DIMM 1 in this example), insert a replacement DIMM into the now empty DIMM slot, retest the DRAM cartridge via the field test app to confirm normal operation, and upon receiving such confirmation, reinstall / close the service panel (to reseal the chamber in which the DRAM module is inserted), and finally hot-insert the DRAM cartridge 109 into the server rack 105. The RMA information returned from the data center management infrastructure may optionally be printed onto a shipping label (i.e., via transmission from the tester app or other computing application to a printing device) in the form of a barcode, quick response (QR) code, etc. (optionally along with a human-readable character sequence), and the label affixed to a shipping package to facilitate delivery of the failed DRAM module to a remote service center. In some failure modes, the field test app may (either on its own or with the aid of instructions / communications from the supporting computing infrastructure) instruct the failed DRAM module to be discarded rather than shipped for evaluation / repair. Additionally, in alternative embodiments, the DRAM cartridge itself may be implemented using wireless communications (or have a physical service port accessible when the DRAM cartridge is installed within the server rack 105), and instructed to perform various tests without removal from the server rack - instructions issued by an authenticated service device (e.g., an authenticated app executed within a handheld computing device), with test results returned wirelessly to the same device for presentation to a user. In still other embodiments, the tests may be initiated in response to instructions issued by a host computer via a PCIe port of the DRAM cartridge, with results returned to one or more local or remote computing devices operated by a data center manager (e.g., to a user via the Internet, an intranet, or other digital communications network). One or more light emitting elements (e.g., light emitting diodes) and / or speaker elements may be provided to signal device status, including detected errors / operational failures with respect to one or more plug-in DRAM modules.
[0013] Overall reference Figures 1 to 3 , the various DRAM cartridges disclosed herein may be implemented according to alternative form factors and / or electrical interconnect standards (e.g., the E1.S and E1.L EDSFF standards promulgated by SNIA), and the various plug-in memory modules may likewise be implemented according to various standards (e.g., high bandwidth memory modules implemented as die stacks with or without base layer dies). Furthermore, in addition to reference to Figure 2Memory subsystem architectures other than those shown and described may be implemented on a substrate of a given DRAM cassette, and however implemented, two or more such cassette substrates and associated memory subsystems may be implemented within a DRAM cassette (e.g., particularly within an E3.S2T or E3.L 2T form factor cassette). The individual memory components mounted to or within a given memory module may include a single memory die or multiple stacked and / or laterally arranged memory dies. Additionally, the hardware-level implementation of any or all of the various DRAM cassettes (and / or supporting circuitry therein) may be described using computer-aided design tools and expressed (or represented) as data and / or instructions embodied in various computer-readable media in terms of their physical, behavioral, register transfer, logic components, transistors, layout geometry, and / or other characteristics. The formats of files and other objects in which such circuit representations may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL, formats supporting register-level description languages such as RTL, and formats supporting geometric description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. Computer-readable media in which such formatted data and / or instructions may be embodied include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media).
[0014] Such data and / or instruction-based representations of the circuits described above, when received within a computer system via one or more computer-readable media, may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs to generate a representation or image of the physical manifestation of such circuits, the one or more other computer programs including, but not limited to, netlist generation programs, placement and routing programs, etc. Such representations or images may thereafter be used in device fabrication, for example, by causing the generation of one or more masks used to form various components of the circuits during device fabrication.
[0015] In the foregoing description and in the accompanying drawings, specific terms and reference numerals have been set forth to provide a comprehensive understanding of the disclosed embodiments. In some instances, the terms and reference numerals may imply specific details that are not required for practicing these embodiments. For example, various interconnections between internal circuit elements or blocks may be displayed as buses or single signal lines. Alternatively, each bus may be a single signal line (e.g., with a digital or analog signal that is time-division multiplexed thereon), and each single signal line may alternatively be a bus. No matter how it is displayed or described, signals and signaling links may be single-ended or differential. In alternative embodiments, a logic signal displayed as having an effective high level assertion or a "true" state may have an opposite assertion state. When a signal driver circuit asserts (or cancels assertion, if the context clearly states or indicates) a signal on a signal line coupled between the signal driver circuit and the signal receiving circuit, it is considered that the signal driver circuit "outputs" a signal to the signal receiving circuit. The term "coupling" is used herein to express direct connections and connections made through one or more intermediate circuits or structures. Integrated circuit device or register "programming" may include, for example, but not limited to, loading control values into configuration registers or other storage circuits within the integrated circuit device in response to host instructions (and thereby controlling operational aspects of the device and / or establishing a device configuration) or through a one-time programming operation (e.g., blowing fuses within the configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also known as strapping) to establish a particular device configuration or operational aspect of the device. The terms "exemplary" and "embodiment" are used to express examples, not preferences or requirements. In addition, the terms "may" and "can" are used interchangeably to indicate optional (permitted) subject matter. The absence of either term should not be interpreted as meaning that a given feature or technique is required.
[0016] Various modifications and changes may be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. For example, the features or aspects of any embodiment may be applied in combination with any other embodiment, or in place of its corresponding features or aspects. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.
Claims
1. A hot-swappable memory box, characterized in that: The hot-swappable memory cartridge comprises: A printed circuit board having an integral edge connector compliant with the Peripheral Component Interconnect Express (PCIe) signaling standard; one or more memory module sockets secured to the printed circuit board, each memory module socket having an electrical connector for receiving a corresponding edge connector of a corresponding dynamic random access memory (DRAM) module, such that one or more DRAM modules can be removably inserted into the one or more memory module sockets; and A box housing, the box housing conforming to the solid-state drive SSD form factor specified by the standard and having: an opening through which the integral edge connector of the printed circuit board extends to enable the hot-swappable memory cartridge to be inserted into a backplane of a rack-mount computing enclosure; An access panel is movable from a closed position to expose the one or more memory module slots.
2. The hot-swappable memory cartridge according to claim 1, wherein: The hot-swappable memory cartridge further includes an application specific integrated circuit (ASIC) disposed on the printed circuit board and electrically coupled between the PCIe-compliant integrated edge connector and the one or more memory module slots.
3. The hot-swappable memory cartridge according to claim 2, wherein: in, The ASIC includes circuitry for implementing a cache coherent signaling protocol supporting memory read and write semantics over a PCIe signaling interface.
4. The hot-swappable memory cartridge according to claim 3, wherein: in, The ASIC for implementing the cache coherent signaling protocol includes circuitry for implementing a cache coherent signaling protocol compliant with one or more Compute Express Link (CXL) standard specifications.
5. The hot-swappable memory cartridge according to claim 1, wherein: in, The respective DRAM module includes a dual in-line memory module (DIMM) carrier having DRAM components disposed thereon and coupled to the corresponding edge connector of the respective DRAM module via a respective set of data lines.
6. The hot-swappable memory cartridge according to claim 1, wherein: in, The respective DRAM modules include a signaling interface in accordance with one or more memory interface standards promulgated by the Joint Electron Devices Engineering Council (JEDEC).
7. The hot-swappable memory cartridge according to claim 1, wherein: in, The access panel is completely separated from the cartridge housing to expose the one or more memory module slots.
8. The hot-swappable memory cartridge according to claim 1, wherein: in, The access panel, when moved from the closed position, reveals an aperture through which the one or more DRAM modules can be inserted into the one or more memory module slots.
9. The hot-swappable memory cartridge according to claim 8, wherein: in, The access panel pivots about one or more hinges disposed at an edge of the aperture to expose the one or more memory module slots when moved from the closed position.
10. The hot-swappable memory cartridge according to claim 8, wherein: in, The aperture and the access panel are large enough to allow a standard small outline dual in-line memory module, ie, a standard SO-DIMM, to enter the cartridge housing for insertion into any one of the one or more memory module slots.
11. The hot-swappable memory cartridge according to claim 8, wherein: in, The aperture is formed in a first surface of the cassette housing and is covered by the access panel in the closed position, and wherein the access panel slides in a direction parallel to the first surface when moved from the closed position.
12. The hot-swappable memory cartridge according to claim 1, wherein: in, The one or more memory module sockets physically and electrically conform to the Small Outline DIMM (SO-DIMM) standard specification.
13. The hot-swappable memory cartridge according to claim 1, wherein: in, The box housing complies with the Enterprise and Data Center Standard Form Factor EDSFF specification promulgated by the Storage Networking Industry Association SNIA.
14. The hot-swappable memory cartridge according to claim 13, wherein: in, The cartridge housing complies with at least one of the following EDSFF specifications: E3.S; E3.S2T; E3.L; or E3.L 2T.
15. The hot-swappable memory cartridge of claim 1, wherein: The box housing includes a dimensional profile that enables the box housing to be secured within an SSD carrier having a standard form factor and facilitates insertion and removal of the hot-swappable storage box into and from the backplane of the rack-mounted computing housing.