Substrate for semiconductor package and semiconductor package

Abstract

A package substrate including a stress cushion is provided. Each stress buffer pad may be vertically spaced and at least partially overlapped with a corresponding bond pad of the package substrate. The stress cushion may provide structural reinforcement to distribute tensile stress across the package substrate and suppress warpage and fracture formation in the package substrate. Therefore, the reliability and yield of the semiconductor package can be improved.

Description

Technical Field

[0001] The present disclosure relates to a substrate for semiconductor packaging, and more particularly to a substrate having a stress buffer pad. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers on a semiconductor substrate, and patterning the various material layers using lithography techniques to form circuit components and elements thereon. Typically, dozens or hundreds of integrated circuits can be manufactured on a single semiconductor wafer, and the individual die on the wafer are singulated by sawing along dicing lines between the integrated circuits. The individual dies are typically packaged separately, such as in multi-chip modules, or in other types of packaging. As packages become larger and more complex, it becomes more difficult to ensure the mechanical integrity of the package. Utility Model Content

[0003] An embodiment of the present disclosure provides a semiconductor device, comprising: a substrate core; and a plurality of redistribution structures located above the surface of the substrate core, wherein the redistribution structures comprise: a plurality of conductive interconnect structures located within a dielectric material; a bonding pad; and a stress buffer pad vertically separated from the bonding pad, wherein the stress buffer pad is closer to the bonding pad than to the surface of the substrate core.

[0004] In some embodiments, a ratio of a minimum width dimension of the stress buffer to a minimum width dimension of the bonding pad is at least 0.7.

[0005] In some embodiments, a vertical separation distance between the bonding pad and the stress buffer pad is between 20 μm and 40 μm, and the dielectric material of the redistribution structure is located between the bonding pad and the stress buffer pad.

[0006] In some embodiments, a ratio of a minimum width dimension of the stress buffer pad to a minimum width dimension of the bonding pad is less than 1.5.

[0007] In some embodiments, the stress buffer is electrically isolated from the conductive interconnect structure of the redistribution structure and the bonding pad.

[0008] In some embodiments, the Young's modulus of the material constituting the stress buffer is higher than the Young's modulus of the material constituting the bonding pad.

[0009] In some embodiments, the stress buffer includes a multi-layer stress buffer, the multi-layer stress buffer includes a lower structure and an upper structure, the lower structure and the upper structure extend in different horizontal planes that are vertically offset from each other.

[0010] The presently disclosed embodiment provides a semiconductor package, comprising: a semiconductor package structure, comprising one or more semiconductor integrated circuit chips; a package substrate, comprising a plurality of bonding pads and a plurality of stress buffer pads, wherein each stress buffer pad is vertically separated from and at least partially overlaps with a corresponding bonding pad among the bonding pads; and a supporting substrate, wherein the semiconductor package structure is mounted on a first side of the package substrate, and a second side of the package substrate is mounted on the supporting substrate.

[0011] In some embodiments, the packaging substrate includes a substrate core, which is located between the first side and the second side of the packaging substrate, and the stress buffer pad is closer to the bonding pad than to the substrate core, and wherein the ratio of the minimum width dimension of each of the stress buffer pads to the minimum width dimension of the corresponding bonding pad is at least 0.7.

[0012] In some embodiments, the semiconductor packaging structure includes: an interposer; and a plurality of semiconductor integrated circuit dies mounted on an upper surface of the interposer, and the semiconductor packaging structure is mounted on the first side of the packaging substrate through a plurality of solder connectors, the solder connectors extending between a lower surface of the interposer and the first side of the packaging substrate, and the supporting substrate includes a printed circuit board, and the packaging substrate is mounted on the printed circuit board through a plurality of solder connections, the solder connectors extending between the bonding pads located on the second side of the packaging substrate and an upper surface of the printed circuit board.

[0013] The presently disclosed embodiment provides a method for manufacturing a packaging substrate, comprising: forming a conductive interconnect structure within a dielectric material, the dielectric material being located above a surface of a substrate core; forming a stress buffer pad above the conductive interconnect structure; forming a bonding pad above the stress buffer pad, wherein the stress buffer pad is vertically separated from the bonding pad, and the stress buffer pad and the bonding pad at least partially overlap; and forming a passivation layer, the passivation layer covering a portion of the bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0015] Figure 1 is a vertical cross-sectional view of an exemplary intermediate structure during a process of forming a package substrate including a substrate core according to various embodiments of the present disclosure, the substrate core including a first surface and a second surface opposite the first surface.

[0016] Figure 2is a vertical cross-sectional view of an exemplary intermediate structure during a process of manufacturing a package substrate according to various embodiments of the present disclosure, illustrating core metal features located above a first surface and a second surface of a substrate core and a plurality of vias extending through the substrate core.

[0017] Figure 3 is a vertical cross-sectional view of an exemplary intermediate structure during a process of fabricating a package substrate according to various embodiments of the present disclosure, illustrating a first redistribution structure formed over a first surface of a substrate core.

[0018] Figure 4 is a vertical cross-sectional view of a package substrate including a second redistribution structure according to various embodiments of the present disclosure, the second redistribution structure including a stress buffer formed over a second surface of a substrate core.

[0019] Figure 5A According to an embodiment of the present disclosure Figure 4 FIG. 1 is an enlarged vertical cross-sectional view of region A of the package substrate shown.

[0020] Figure 5B For along Figure 5A A horizontal cross-sectional view of the package substrate taken along the section line BB' in FIG.

[0021] Figure 5C For along Figure 5A A horizontal cross-sectional view of the packaging substrate taken along the section line CC' in FIG.

[0022] Fig. 6A According to another embodiment of the present disclosure Figure 4 FIG. 1 is an enlarged vertical cross-sectional view of region A of the package substrate shown.

[0023] Figure 6B For along Fig. 6A A horizontal cross-sectional view of the package substrate taken along the section line BB' in FIG.

[0024] Figure 6C For along Fig. 6A A horizontal cross-sectional view of the packaging substrate taken along the section line CC' in FIG.

[0025] Fig. 7A is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0026] Figure 7B For along Fig. 7A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0027] Figure 7C For along Fig. 7A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0028] Fig. 8A is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0029] Figure 8B For along Fig. 8A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0030] Figure 8C For along Fig. 8A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0031] Fig. 9A FIG. 4 is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0032] Fig. 9B For along Fig. 9A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0033] Fig. 9C For along Fig. 9A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0034] Fig. 10A is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0035] Figure 10B shows the Fig. 10A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0036] Fig. 10C For along Fig. 10A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0037] Fig.11A is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0038] Fig. 11B For along Fig.11A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0039] Fig. 11C For along Fig.11A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0040] Fig. 12A is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0041] Fig. 12B For along Fig. 12A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0042] Fig. 12C For along Fig. 12A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0043] Fig.12D For along Fig. 12A A horizontal cross-sectional view of a portion of the package substrate taken along the section line DD' in FIG.

[0044] Fig.13A is a vertical cross-sectional view of a portion of a package substrate according to yet another embodiment of the present disclosure.

[0045] Fig. 13B For along Fig.13A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0046] Fig. 13C For along Fig.13A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0047] Fig.14 1 is a vertical cross-sectional view of a semiconductor package according to various embodiments of the present disclosure. The semiconductor package includes a package structure disposed above a first outer surface of a package substrate. The package substrate includes a plurality of stress buffer pads.

[0048] Fig.15 1 is a vertical cross-sectional view of a semiconductor package according to various embodiments of the present disclosure, the semiconductor package including a second underfill material portion between a first outer surface of a package substrate and a lower surface of an interposer.

[0049] Fig.16 FIG. 4 is a vertical cross-sectional view of a semiconductor package mounted on a support substrate according to various embodiments of the present disclosure.

[0050] Fig.17 1 is a vertical cross-sectional view of a semiconductor package mounted on a support substrate according to various embodiments of the present disclosure, wherein the support substrate includes a third underfill material portion.

[0051] Fig.18 A flow chart of a method for manufacturing a package substrate is depicted according to various embodiments of the present disclosure.

[0052] The reference numerals are described as follows:

[0053] 101: Baseboard Core

[0054] 103: Stress buffer

[0055] 103a: Segment / First Segment

[0056] 103b: Segment / Second Segment

[0057] 104: Core metal parts

[0058] 105: First surface

[0059] 106: Second Surface

[0060] 107: Guide hole

[0061] 108: Dielectric Materials

[0062] 109: Conductive interconnect structures

[0063] 110: Redistribution layer

[0064] 110a: First redistribution structure

[0065] 110b: Second redistribution structure

[0066] 111: Passivation layer / solder mask / solder resist / outer coating

[0067] 112: First bonding pad / bonding pad

[0068] 113: Second bonding pad / bonding pad

[0069] 113a: Bonding pad area

[0070] 113b: Guide hole contact area

[0071] 114: First outer surface / first side

[0072] 115: second outer surface / second surface / second side

[0073] 116: Metal wire

[0074] 117: Guide hole / first guide hole / second guide hole

[0075] 118: Dashed Line

[0076] 120: Package substrate / substrate

[0077] 121: Connecting vias

[0078] 122: Dashed line

[0079] 123: Substructure

[0080] 125: Superstructure

[0081] 127: Connecting vias

[0082] 130: Packaging structure

[0083] 131: Semiconductor IC Die

[0084] 133: Intermediary

[0085] 134: Interconnection Structure

[0086] 135: Joint structure

[0087] 136: Welding materials / solder connections

[0088] 137: Bonding pad

[0089] 138: First bottom filling material

[0090] 139: Molding Department

[0091] 140: Semiconductor packaging / semiconductor packaging structure

[0092] 141: Second bottom filling material portion

[0093] 142: Strengthen the structure

[0094] 150: Support substrate

[0095] 151: Upper surface

[0096] 153: Bonding pad

[0097] 154: Welding material department / solder connection parts

[0098] 160: Third bottom filling material part

[0099] 200: Methods

[0100] 201, 203, 205, 207: Steps

[0101] A: District

[0102] Da, Db: minimum width size

[0103] hd1: first horizontal direction

[0104] hd2: second horizontal direction DETAILED DESCRIPTION

[0105] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0106] Furthermore, spatially relative terms such as "under", "below", "lower", "above", "higher" and the like may be used to facilitate the description of the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0107] Various embodiments of the present disclosure may relate to semiconductor devices, and more particularly, to substrates for semiconductor packages and methods of manufacturing the same, the substrates including stress buffers.

[0108] Typically, in a semiconductor package, a plurality of semiconductor integrated circuit (IC) dies (i.e., "chips") may be mounted on a general substrate, which may also be referred to as a "package substrate". In some packages, such as fan-out wafer level package (FOWLP) and / or fan-out panel level package (FOPLP), a plurality of semiconductor IC dies may be mounted on an interposer, such as an organic interposer or a semiconductor (e.g., silicon) interposer, which may include interconnect structures extending therethrough. The resulting package structure may then be mounted on a surface of a package substrate using a solder connection to form a semiconductor package, the package structure including an interposer and semiconductor IC dies mounted on the interposer. The semiconductor package may then be mounted on a supporting substrate, such as a printed circuit board (PCB), the semiconductor package including a package substrate and a package structure mounted on the package substrate.

[0109] As semiconductor packages become larger and more complex by integrating more semiconductor IC dies, it becomes more important to ensure the mechanical stability of semiconductor packages. In many semiconductor packages, mechanical stress on various components of the semiconductor package (e.g., the package substrate) may cause warpage and cracking in the components. This may lead to an increase in the failure rate and a decrease in the reliability of the semiconductor package.

[0110] Various embodiments of the present disclosure include a package substrate and a method for manufacturing a package substrate including a stress buffer pad. In various embodiments, the package substrate may include a substrate core having a first surface and a second surface opposite to the first surface. A redistribution structure including a conductive interconnect structure embedded in a dielectric material may be located above the first surface and above the second surface of the substrate core. The redistribution structure may also include a plurality of first bonding pads located on a first side of the package substrate, a plurality of second bonding pads located on a second side of the package substrate, and a protective coating (e.g., a solder resist layer) defining the first outer surface and the second outer surface of the package substrate. A plurality of first bonding pads may be configured to bond the first side of the package substrate to a semiconductor package structure including one or more semiconductor IC dies, and a plurality of second bonding pads may be configured to bond the second side of the package substrate to a supporting substrate, such as a PCB. At least one stress buffer pad may be located within the redistribution structure proximate to the second side of the package substrate, and the stress buffer pad may be vertically separated from and at least partially overlapped with a corresponding bonding pad among the plurality of second bonding pads. The stress buffer can provide structural reinforcement, which can distribute tensile stress on the package substrate and thereby inhibit the formation of warpage and cracks in the package substrate. Therefore, the reliability and yield of the semiconductor package can be improved.

[0111] Figure 1-Figure 4 1 is a series of vertical cross-sectional views of exemplary intermediate structures formed during a process of manufacturing a package substrate according to various embodiments of the present disclosure. Figure 1 , depicting a substrate core 101. The substrate core 101 includes a first surface 105 and a second surface 106 opposite to the first surface 105. In some embodiments, the substrate core 101 may be formed of a laminate reinforced resin sheet. The laminate reinforced resin sheet may include a reinforcing material (e.g., fiberglass or cloth) impregnated with a resin system, such as an epoxy-based resin system, and cured under heat and pressure to form a laminate reinforced resin sheet. In some embodiments, a layer of conductive material (e.g., copper foil) may be provided on the upper surface and the lower surface of the stack during the lamination process to provide a film layer (not shown) containing a conductive material. Figure 1The substrate core 101 is a substrate core 101 having a conductive material layer disposed above a first surface 105 and above a second surface 106 of the substrate core 101. Other suitable materials and configurations for the substrate core 101 are within the contemplation of the present disclosure. In various embodiments, the thickness of the substrate core 101 between the first surface 105 and the second surface 106 may be between about 0.4 mm and about 1.5 mm, although thicker or thinner dimensions may be used.

[0112] Figure 2 FIG. 1 is a vertical cross-sectional view of an exemplary intermediate structure during a process of manufacturing a package substrate according to various embodiments of the present disclosure, which depicts a core metal feature 104 located above a first surface 105 and a second surface 106 of a substrate core 101 and a plurality of vias 107 extending through the substrate core 101. Figure 2 , a plurality of through holes can be formed through the substrate core 101, and these through holes extend between the first surface 105 and the second surface 106 of the substrate core 101. Any suitable process can be used to form the through holes, such as mechanical drilling, laser drilling, or etching process by optical lithography-patterned mask. Other processes suitable for forming the through holes are within the scope of the present disclosure.

[0113] Refer again Figure 2 , a plurality of vias 107 may be formed within each through hole so that the vias 107 extend between the first surface 105 and the second surface 106 of the substrate core 101. The vias 107 may be formed of a suitable conductive material, such as copper, nickel, tungsten, aluminum, cobalt, molybdenum, ruthenium, and the like, including combinations thereof and alloys thereof. Other materials suitable for the vias 107 are within the contemplation of the present disclosure. A suitable deposition process may be used to form the plurality of vias 107, such as an electrochemical deposition process (e.g., electroplating). Other suitable deposition processes are within the contemplation of the present disclosure.

[0114] Refer again Figure 2 , the core metal component 104 can be formed on the first surface 105 and the second surface 106 of the substrate core 101. In some embodiments, the core metal component 104 can be formed by providing a film layer of conductive material (e.g., copper clad laminate) on the first surface 105 and the second surface 106 of the substrate core 101. In some embodiments, as described above with reference to Figure 1As described, the film layer of conductive material may be formed during the lamination process used to form the substrate core 101. Alternatively or additionally, a suitable deposition process, such as an electroplating process, may be used to form all or part of the film layer of conductive material over the first surface 105 and over the second surface 106 of the substrate core 101. The film layer of conductive material may be patterned by an etching process performed through a mask patterned by optical lithography to form separate core metal components 104 over the first surface 105 and over the second surface 106 of the substrate core 101. The core metal component 104 may be electrically coupled to one or more vias 107.

[0115] Figure 3 is a vertical cross-sectional view of an exemplary intermediate structure during a process of manufacturing a package substrate according to various embodiments of the present disclosure, which depicts a first redistribution structure 110a formed above the first surface 105 of the substrate core 101. The first redistribution structure 110a may include a plurality of conductive interconnect structures 109 (e.g., metal lines 116 and vias 117) embedded in a dielectric material 108. The first redistribution structure 110a may further include a plurality of first bonding pads 112 and a passivation layer 111 formed above the dielectric material 108 and above the conductive structures 109. In various embodiments, the first redistribution structure 110a may be located between the first surface 105 of the substrate core 101 and a semiconductor package structure including one or more semiconductor IC dies (or "chips") in an assembled semiconductor package. Therefore, the first redistribution structure 110a may also be referred to as a "chip-side" redistribution structure 110a.

[0116] Reference Figure 3 The first redistribution structure 110a may be formed by providing a first film layer of a dielectric material 108 over the first surface 105 of the substrate core 101 and over the core metal component 104. The first film layer of the dielectric material 108 may include a polymer-based dielectric material, such as Ajinomoto Buildup Film (Ajinomoto Buildup Film; A ... ). Other suitable dielectric materials are within the contemplation of the present disclosure. In some embodiments, a first film layer of dielectric material 108 may be applied as a film over the first surface 105 of the substrate core 101 and over the core metal component 104. The film may be vacuum laminated over the first surface 105 of the substrate core 101 and over the core metal component 104, and the film may be partially cured (e.g., by a hot-pressing process). A suitable process, such as mechanical drilling, laser drilling, and / or etching processes, may be used to form a plurality of through holes through the first film layer of dielectric material 108. The core metal component 104 and / or the guide hole 107 may be exposed at the bottom of each through hole.

[0117] A metallization process may be used to form a plurality of first vias 117 within the plurality of through holes through the first layer of dielectric material 108. The plurality of first vias 117 may be formed using a suitable deposition, such as electroplating. The deposition process may also form a second layer of conductive material over the first layer of dielectric material 108. Alternatively, a separate deposition process may be used to form the second layer of conductive material over the first layer of dielectric material 108. The second layer of conductive material may be patterned by an etching process performed using a mask patterned by photolithography to form a plurality of metal lines 116 (e.g., copper traces) over the surface of the first layer of dielectric material 108. As described above, the second layer of dielectric material 108 may be formed over the plurality of metal lines 116 and a plurality of through holes may be formed through the second layer of dielectric material 108. An additional metallization process may be used to form a plurality of second vias 117 within the through holes formed through the second layer of dielectric material 108. These processes may optionally be repeated several times to form a first redistribution structure 110a, which includes a plurality of conductive interconnects 109 (e.g., metal lines 116 and vias 117) embedded in a dielectric material 108. The film layer of dielectric material 108 may optionally be subjected to a curing process at an elevated temperature (e.g., 170-200° C.) to form a solid dielectric material 108 surrounding the conductive interconnect structure 109. A plurality of first bonding pads 112 may be formed above the topmost film layer of dielectric material 108. A passivation layer 111 may also be formed above the topmost film layer of dielectric material 108. The plurality of first bonding pads 112 may be exposed through openings in the passivation layer 111. The passivation layer 111 may define a first outer surface 114 of the package substrate. The passivation layer 111 may provide a protective coating for the package substrate. The passivation layer 111 may also inhibit solder material from adhering to the first outer surface 114 of the package substrate during a subsequent solder reflow process.

[0118] In various embodiments, the passivation layer 111 may include a solder resist material. The passivation layer 111 formed by the solder resist material may also be referred to as a "solder mask". The solder resist material of the passivation layer 111 may include a suitable resin material that is resistant to moisture and high temperature and does not adhere firmly to the solder resist material. The solder resist material of the passivation layer 111 may be formed using a suitable deposition process, such as screen printing, spraying and / or vacuum lamination. Other suitable deposition processes are within the scope of consideration of the present disclosure.

[0119] Figure 4 FIG. 1 is a vertical cross-sectional view of a package substrate 120 according to various embodiments of the present disclosure, wherein the package substrate 120 includes a second redistribution structure 110 b formed on the second surface 106 of the substrate core 101 . Figure 4 , the second redistribution structure 110b located above the second surface 106 of the substrate core 101 may include a plurality of conductive interconnect structures 109 (e.g., metal lines 116 and vias 117) embedded in the dielectric material 108, a plurality of second bonding pads 113 formed above the dielectric material 108 and the conductive interconnect structures 109, and a passivation layer 111 formed above the dielectric material 108 and the conductive interconnect structures 109. The passivation layer 111 of the second redistribution structure 110b may define a second outer surface 115 of the package substrate 120, the second outer surface 115 being opposite to the first outer surface 114. The second redistribution structure 110b located above the second surface 106 of the substrate core 101 may include the same as described above with reference to Figure 3 The first redistribution structure 110a formed on the first surface 105 of the substrate core 101 is similar in structure and can be formed using similar or identical processes. Therefore, for the sake of brevity, repeated discussion of similar components is omitted. In addition, although Figure 3 as well as Figure 4 An embodiment is depicted in which a first redistribution structure 110a is formed above the first surface 105 of the substrate core 101 before a second redistribution structure 110b is formed above the second surface 106 of the substrate core 101. It should be understood that the second redistribution structure 110b may be formed above the second surface 106 of the substrate core 101 before the first redistribution structure 110a is formed above the first surface 105 of the substrate core 101, or the first redistribution structure 110a and the second redistribution structure 110b (collectively referred to as the redistribution layer 110) may be formed simultaneously above the first surface 105 and the second surface 106 of the substrate core 101.

[0120] Refer again Figure 4, the second redistribution structure 110b may be located between the second surface 106 of the substrate core 101 and a supporting substrate (e.g., PCB) in the assembled semiconductor package. Therefore, the second redistribution structure 110b may also be referred to as a "board-side" redistribution structure 110b. The first redistribution structure 110a may have a plurality of first bonding pads 112 configured to electrically connect the package substrate 120 to a semiconductor package structure including at least one semiconductor IC die, and the second redistribution structure 110b may have a plurality of second bonding pads 113 configured to electrically connect the package substrate 120 to a supporting substrate, such as a PCB.

[0121] As described above, mechanical stress on various components of the semiconductor package (including the package substrate 120) may cause warping and cracking within the package substrate 120. This may increase the failure rate and reduce the reliability and / or yield of the semiconductor package. Figure 4 In the case of the package substrate 120 shown, for example, the difference in the amount of shrinkage between the passivation layer 111 (e.g., solder mask layer, polymer layer, dielectric layer, oxide layer, nitride layer, or combination thereof) and the dielectric material 108 (e.g., build-up film, organic material layer, polymer film, oxide layer, nitride layer, or combination thereof) may impose tensile stresses on the package substrate 120. These stresses are often concentrated in specific areas of the package substrate 120, such as areas of the "board side" of the package substrate 120 where the conductive interconnect structures 109 between the bonding pads 113 and the core metal features 104 above the second surface 106 of the substrate core 101 are minimal (if any). Therefore, these areas where tensile stresses are concentrated may cause warping of the package substrate 120 and cracks that penetrate through the passivation layer 111 around the bonding pads 113 and into the dielectric material 108 of the second redistribution structure 110b. This may negatively affect the integrity and performance of the package substrate 120.

[0122] The package substrate 120 according to various embodiments of the present disclosure may include at least one stress buffer 103 located in the second (ie, “board-side”) redistribution structure 110 b of the package substrate 120 . Figure 4 A plurality of stress buffer pads 103 are shown within the second redistribution structure 110b of the package substrate 120. Each stress buffer pad 103 may be separated from one of the plurality of second bonding pads 113 and may at least partially cover (ie overlap) one of the plurality of second bonding pads 113. Figure 4An embodiment is shown in which the stress buffer 103 is located above a first subset of the bonding pads 113 of the plurality of second bonding pads 113, and the stress buffer 103 is not present above the second subset of the bonding pads 113. However, it should be understood that in other embodiments, the stress buffer 103 may be present above all of the bonding pads 113 of the plurality of second bonding pads 113. In various embodiments, at least one stress buffer 103 may relieve stress on the passivation layer 111, and may also help isolate the stress on the passivation layer 111 from the overlying dielectric material 108 of the second redistribution structure 110b. Therefore, the risk of cracks being formed in the second redistribution structure 110b may be reduced, and the reliability and yield of the semiconductor package may be improved.

[0123] In some embodiments, the stress buffer 103 may be formed of a suitable conductive material, such as copper, nickel, tungsten, aluminum, cobalt, molybdenum, ruthenium and the like, including combinations thereof and alloys thereof. In some embodiments, the stress buffer 103 may be formed of the same material as the conductive interconnect structure 109 (e.g., metal line 116 and via 117) and / or the bonding pad 112, bonding pad 113 of the second redistribution structure 110b. The stress buffer 103 may be formed during the process for forming the second redistribution structure 110b as described above. In particular, the stress buffer 103 may be formed by depositing a film layer of a conductive material over a film layer of a dielectric material 108 using a suitable deposition process, and the stress buffer 103 may be patterned by an etching process performed by a mask patterned by optical lithography to form a plurality of separate stress buffers 103. One or more additional layers of dielectric material 108 may then be deposited over the stress buffer 103, and a bonding pad 113 may be formed over the one or more additional layers of dielectric material 108. The stress buffer 103 may be electrically coupled to the conductive interconnect structure 109 and / or the bonding pad 113 of the second redistribution structure 110b, or may be electrically isolated from the conductive interconnect structure 109 and / or the bonding pad 113 of the second redistribution structure 110b, as described in more detail below.

[0124] In some embodiments, the Young's modulus of the material constituting the whole or part of the stress buffer 103 is higher than the Young's modulus of the material of the conductive interconnect structure 109 and / or the bonding pad 113 of the second redistribution structure 110b. For example, when the conductive interconnect structure 109 and the bonding pad 113 of the second redistribution structure 110b are made of copper (Young's modulus = 130 GPa), the stress buffer 103 can be made of a material with a Young's modulus greater than 130 GPa, such as greater than 200 GPa, including greater than 300 GPa. In some embodiments, the stress buffer 103 can be made of a ceramic material, such as aluminum oxide (Al2O3). 2 O 3), aluminum nitride, etc. and / or semiconductor materials, such as silicon. Other materials suitable for the stress buffer pad 103 are all within the scope of consideration of the present disclosure.

[0125] Figure 5A According to various embodiments of the present disclosure Figure 4 An enlarged vertical cross-sectional view of region A of the package substrate shown in FIG. Figure 5B For along Figure 5A A horizontal cross-sectional view of the package substrate taken along the section line BB' in FIG. Figure 5C For along Figure 5A A horizontal cross-sectional view of the package substrate taken along the section line CC' in FIG. Figure 5A , the stress buffer 103 is shown extending substantially parallel to the bonding pad 113 of the packaging substrate 120 and vertically separated from the bonding pad 113 of the packaging substrate 120. The stress buffer 103 may be located between the bonding pad 113 of the packaging substrate 120 and the substrate core 101 of the packaging substrate and at least partially cover the bonding pad 113. In various embodiments, the stress buffer 103 may be closer to the bonding pad 113 than to the second surface 106 of the substrate core 101. In a non-limiting embodiment, the vertical separation distance between the bonding pad 113 and the stress buffer 103 may be between about 20 μm and about 40 μm, although a larger or smaller vertical separation distance may be used, but the vertical separation distance is less than the thickness of the second redistribution structure 110b. In some embodiments, the total vertical separation distance between the bonding pad 113 and the substrate core 101 may be between about 90 μm and about 450 μm, but the total vertical separation distance is less than the thickness of the second redistribution structure 110b. The dielectric material 108 of the second redistribution structure 110b may be located between the bonding pad 113 and the overlying stress buffer 103. Therefore, the bonding pad 113 and the stress buffer 103 may form a structure similar to a parallel-plate capacitor, wherein the bonding pad 113 and the stress buffer 103 are vertically spaced apart from each other and at least partially overlap.

[0126] exist Figure 5A-5C In the illustrated embodiment, the bonding pad 113 may include a bonding pad region 113a and a via contact region 113b. At least a portion of the bonding pad region 113a may be exposed through an opening in the passivation layer 111 (e.g., solder mask) so that the bonding pad 113 can be mechanically and electrically coupled to a supporting substrate (e.g., PCB) through a bonding material (e.g., solder ball). Figure 5A-5CThe bonding pad area 113a in the embodiment has a circular shape, but it should be understood that the bonding pad area 113a may have different shapes, such as polygonal, elliptical or irregular shapes. The guide hole contact area 113b may extend laterally from one side of the bonding pad area 113a. The size and shape of the guide hole contact area 113b can be set to contact the guide hole 117 of the conductive interconnect structure 109 of the second redistribution structure 110b of the packaging substrate 120. The bonding pad 113a may have a minimum width dimension Da, which is equal to the shortest distance between the peripheral edges (peripheral edges) of the bonding pad 113 through the center of the bonding pad area 113a. Therefore, as Figure 5A and Figure 5B As shown, the bonding pad area 113a has a circular shape, and the minimum width dimension Da of the bonding pad 113 may be equal to the diameter of the bonding pad area 113a. In some embodiments, the minimum width dimension Da of the bonding pad 113 may be between about 450 μm and about 900 μm, but it should be understood that a larger or smaller minimum width dimension Da of the bonding pad 113 may be used.

[0127] Reference Figure 5A as well as Figure 5C In this embodiment, the stress buffer 103 has a dish shape, and the horizontal cross-section of the dish shape is circular, but it should be understood that the stress buffer 103 may have different shapes, such as polygonal, elliptical or irregular shapes. Figure 5A-5C As shown, the stress buffer pad 103 may have the same horizontal cross-sectional shape as the bonding pad 113, but in other embodiments, the stress buffer pad 103 may have a horizontal cross-sectional shape different from the bonding pad 113. In this embodiment, the stress buffer pad 103 contacts the conductive interconnect structure 109 of the second redistribution structure 110b. In particular, as Figure 5C , the via 117 may contact the stress buffer 103. In an embodiment where the stress buffer 103 is formed of a conductive material, the first via 117 may contact the upper surface of the stress buffer 103, and the second via 117 may contact the lower surface of the stress buffer 103 and extend between the stress buffer 103 and the via contact region 113b of the bonding pad 113. The first via 117 and the second via 117 may be aligned with each other or may be laterally offset from each other. In other embodiments, a single via 117 may extend continuously through the thickness of the stress buffer 103 to the via contact region 113b of the stress buffer 103, such as when the stress buffer 103 is formed of a non-conductive material.

[0128] The stress buffer 103 may have a minimum width dimension Db, which is equal to the shortest distance between the peripheral edges of the stress buffer 103 through the geometric center of the stress buffer 103. Figure 5A and Figure 5C As shown, the stress buffer 103 has a circular shape, and the minimum width dimension Db of the stress buffer 103 may be equal to the diameter of the stress buffer 103. In various embodiments, the ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, such as at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5. In various embodiments, providing a stress buffer 103 having a minimum width dimension Db that is at least about 70% of the minimum width dimension Da of the underlying bonding pad 113 may provide structural reinforcement that may distribute tensile stress over the passivation layer 111 so that stress is not concentrated around the bonding pad 113. This may help to smooth out any deformation of the passivation layer 111 and inhibit cracks from occurring in the packaging substrate 120.

[0129] Fig. 6A According to another embodiment of the present disclosure Figure 4 An enlarged vertical cross-sectional view of region A of the package substrate 120 is shown in FIG. Figure 6B For along Fig. 6A A horizontal cross-sectional view of the package substrate taken along the section line BB' in FIG. Figure 6C For along Fig. 6A A horizontal cross-sectional view of the packaging substrate taken along the section line CC' in FIG.

[0130] Figure 6A-6C The packaging substrate 120 is similar to the above-mentioned reference Figure 5A-5C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 6A-6C Examples and Figure 5A-5C The embodiment of the present invention is different in that the bonding pad 113 does not include a separate bonding pad area 113a extending laterally from the bonding pad area 113a. Therefore, the bonding pad area 113a can extend over the entire area of ​​the bonding pad 113. The via 117 of the conductive interconnect structure 109 can directly contact the bonding pad 113. Figure 6B The bonding pad area 113a is indicated by the dotted line 118. The via 117 of the conductive interconnect structure 109 can directly contact the stress buffer pad 103, such as Figure 6C Indicated by the dashed line 118. Figure 5A-5C In an embodiment of the present invention, the minimum width dimension Da of the bonding pad 103 may be equal to the shortest distance between the peripheral edges of the bonding pad 113 through the center of the bonding pad area 113a. The stress buffer 103 may at least partially cover the bonding pad 113. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, such as at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5.

[0131] Fig. 7A is a vertical cross-sectional view of a portion of a packaging substrate 120 according to yet another embodiment of the present disclosure. Figure 7B For along Fig. 7A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG. Figure 7C For along Fig. 7A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG. Figure 7A-7C The packaging substrate 120 is similar to the above-mentioned reference Figure 4-5C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 7A-7C The packaging substrate 120 and Figure 4-6C The difference between the package substrate 120 of the present invention is that the stress buffer 103 is electrically isolated from the conductive interconnect structure 109 of the second redistribution structure 110b of the package substrate 120. In other words, the dielectric material 108 of the second redistribution structure 110b can surround each side of the stress buffer. The stress buffer 103 can be laterally offset from the conductive interconnect structure 109 (e.g., the via 117), and the conductive interconnect structure 109 contacts the bonding pad 113 below. As in the previous embodiments, the ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 can be at least 0.7, for example, at least about 1.0. In some embodiments, Db / Da can be between 0.7 and about 1.5.

[0132] Fig. 8A is a vertical cross-sectional view of a portion of a packaging substrate 120 according to yet another embodiment of the present disclosure. Figure 8B For along Fig. 8A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG. Figure 8C For along Fig. 8A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG. Figure 8A-8C The packaging substrate 120 is similar to the above-mentioned reference Figure 4-7C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 8A-8C The packaging substrate 120 and Figure 4-7CThe difference between the packaging substrate 120 is that the stress buffer 103 has an annular shape with an open interior region. The open interior region can be filled with the dielectric material 108 of the second redistribution structure 110b. As in the previous embodiment, the minimum width dimension Db of the stress buffer 103 is equal to the shortest distance between the peripheral edges of the stress buffer 103 through the geometric center of the stress buffer 103. The stress buffer 103 may at least partially cover the bonding pad 113. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, for example at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5. Figure 8A-8C In the embodiment of FIG. 1 , the annular stress buffer 103 contacts the conductive interconnect 109 of the second redistribution structure 110 b. The via 117 of the conductive interconnect 109 may directly contact the region of the stress buffer 103, such as Figure 8C In other embodiments, the annular stress buffer 103 may be electrically isolated from the conductive interconnect structure 109, such as Figure 7A-7C The embodiment shown.

[0133] Fig. 9A is a vertical cross-sectional view of a portion of a packaging substrate 120 according to yet another embodiment of the present disclosure. Fig. 9B For along Fig. 9A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG. Fig. 9C For along Fig. 9A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG. Figure 9A-9C The packaging substrate 120 is similar to the above-mentioned reference Figure 4-8C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 9A-9C The packaging substrate 120 and Figure 4-8C The packaging substrate 120 is different in that the stress buffer 103 has a polygonal shape. As in the previous embodiment, the minimum width dimension Db of the stress buffer 103 is equal to the shortest distance between the peripheral edges of the stress buffer 103 passing through the geometric center of the stress buffer 103. The stress buffer 103 may at least partially cover the bonding pad 113. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, for example at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5. In the embodiments of 9A-9C, the polygonal stress buffer 103 contacts the conductive interconnect structure 109 of the second redistribution structure 110b. The guide hole 117 of the conductive interconnect structure 109 may directly contact the area of ​​the stress buffer 103, such as Fig. 9C In other embodiments, the polygonal stress buffer 103 may be electrically isolated from the conductive interconnect structure 109, such as Figure 7A-7C The embodiment shown.

[0134] Fig. 10A FIG. 10B is a vertical cross-sectional view of a portion of a package substrate 120 according to another embodiment of the present disclosure. Fig. 10A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0135] Fig. 10C For along Fig. 10A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0136] Figure 10A-10C The packaging substrate 120 is similar to the above-mentioned reference Figure 4-9C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 10A-10C The packaging substrate 120 and Figure 4-6C The packaging substrate 120 is different in that the stress buffer 103 has an irregular shape. As in the previous embodiment, the minimum width dimension Db of the stress buffer 103 is equal to the shortest distance between the peripheral edges of the stress buffer 103 passing through the geometric center of the stress buffer 103. In this embodiment, the stress buffer 103 has a non-uniform width dimension. The minimum width dimension Db of the stress buffer 103 is along the first horizontal direction hd1. The maximum width dimension of the stress buffer 103 extends along the second horizontal direction hd2. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, for example at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5. In the embodiments of 10A-10C, the irregularly shaped stress buffer 103 contacts the conductive interconnect structure 109 of the second redistribution structure 110b. The guide hole 117 of the conductive interconnect structure 109 may directly contact the area of ​​the stress buffer 103, such as Fig. 10C In other embodiments, the polygonal stress buffer 103 may be electrically isolated from the conductive interconnect structure 109, such as Figure 7A-7C The embodiment shown.

[0137] Fig.11A is a vertical cross-sectional view of a portion of a packaging substrate 120 according to yet another embodiment of the present disclosure.

[0138] Fig. 11B For along Fig.11A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0139] Fig. 11C For along Fig.11A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0140] Figure 11A-11C The packaging substrate 120 is similar to the above-mentioned reference Figure 4-10C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 11A-11C The packaging substrate 120 and Figure 4-6C The difference between the package substrate 120 and the package substrate 120 is that the guide hole 117 of the conductive interconnect structure 109 of the second redistribution structure 110b is located at a position laterally offset from the bonding pad 113 (by Fig. 11C The plurality of connecting vias 121 contact the lower surface of the stress buffer pad 103 (indicated by the dotted line 118 in FIG. 1 ). Fig. 11C The conductive via 117 of the conductive interconnect structure 109 may directly contact the stress buffer 103, as indicated by the dotted line 122 in FIG. Fig. 11C As indicated by the dashed line 118 in FIG. 1 . As in the previous embodiments, the minimum width dimension Db of the stress buffer 103 is equal to the shortest distance between the peripheral edges of the stress buffer 103 through the geometric center of the stress buffer 103. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, such as at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5.

[0141] Fig. 12A is a vertical cross-sectional view of a portion of a packaging substrate 120 according to yet another embodiment of the present disclosure.

[0142] Fig. 12B For along Fig. 12A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0143] Fig. 12C For along Fig. 12A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0144] Fig.12D For along Fig. 12A A horizontal cross-sectional view of a portion of the package substrate taken along the section line DD' in FIG.

[0145] Figures 12A-12D The packaging substrate 120 is similar to the above-mentioned reference Figure 4-11C Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figures 12A-12D The packaging substrate 120 and Figure 4-11C The difference between the package substrate 120 and the embodiment of the present invention is that the stress buffer pad 103 includes a multi-layer structure, and the multi-layer structure includes a lower structure 123 , an upper structure 125 and a connecting via 127 . Fig. 12B A horizontal cross-sectional view including a lower structure 123 is included, with an upper structure 125 indicated by a dashed line. Fig. 12C A horizontal cross-sectional view including an upper structure 125, wherein the lower structure 123 is indicated by a dotted line. The lower structure 123 and the upper structure 125 of the stress buffer 103 extend in different horizontal planes that are vertically offset from each other. The connecting via 127 can connect the lower structure 123 and the upper structure 125. Although Figures 12A-12D The illustrated stress buffer 103 includes two layers, but it should be understood that in various embodiments, the multi-level stress buffer 103 may include more than two layers.

[0146] exist Figures 12A-12D In the illustrated embodiment, the lower structure 123 of the stress buffer 103 has an annular structure, and the upper structure 125 of the stress buffer 103 has a disc-shaped structure, but it should be understood that other shapes suitable for the lower structure 123 and / or the upper structure 125 may be used. As in the previous embodiment, the minimum width dimension Db of the stress buffer 103 is equal to the shortest distance between the peripheral edges of the stress buffer 103 through the geometric center of the stress buffer 103. In this embodiment, the minimum width dimension Db is along the second horizontal direction hd2 between the outer peripheral edges of the lower structure 123 of the stress buffer 103. The maximum width dimension of the stress buffer 103 is along the first horizontal direction hd1 between the peripheral edges of the upper structure 125 and the peripheral edges of the lower structure 123. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, for example at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5. Figure 12A-12C In the embodiment of the present invention, the lower structure 123 of the multi-layer stress buffer 103 contacts the conductive interconnect structure 109 of the second redistribution structure 110b. The via 117 of the conductive interconnect structure 109 may directly contact the region of the stress buffer 103, such as Fig. 12C In other embodiments, the upper structure 125 of the multi-layer stress buffer 103 may contact the conductive interconnect structure 109 of the second redistribution structure 110 b , or the multi-layer stress buffer 103 may be electrically isolated from the conductive interconnect structure 109 .

[0147] Fig.13A is a vertical cross-sectional view of a portion of a packaging substrate 120 according to yet another embodiment of the present disclosure.

[0148] Fig. 13B For along Fig.13A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line BB' in FIG.

[0149] Fig. 13C For along Fig.13A A horizontal cross-sectional view of a portion of the packaging substrate taken along the section line CC' in FIG.

[0150] Figure 13A-13C The packaging substrate 120 is similar to the above-mentioned reference Figure 4-12D Therefore, for the sake of brevity, repeated discussion of repeated components is omitted. Figure 13A-13C The packaging substrate 120 and Figure 4-10C The difference between the package substrate 120 and the embodiment of the present invention is that the stress buffer pad 103 is composed of a plurality of separated sections 103 a and 103 b , and each separated section at least partially covers the bonding pad 113 . Figure 13A-13C The segmented stress buffer 103 shown in the embodiment includes two semicircular segments 103a and 103b, but it should be understood that the segmented stress buffer 103 may include more than two separated segments 103a and 103b, and each segment 103a and 103b may have a different shape. Figure 13A-13C The separated sections 103a and 103b are located on the same horizontal plane in the embodiment shown in FIG. 1 . In other embodiments, the sections 103a and 103b may be located on different horizontal planes vertically separated from each other, as shown in the above reference. Figures 12A-12D As in the previous embodiment, the minimum width dimension Db of the stress buffer 103 is equal to the shortest distance between the peripheral edges of the stress buffer 103 through the geometric center of the stress buffer 103. Figure 13A-13C In some embodiments, the minimum width dimension Db extends between the outer periphery of the first section 103a and the outer periphery of the second section 103b. The ratio of the minimum width dimension Db of the stress buffer 103 to the minimum width dimension Da of the bonding pad 113 may be at least 0.7, such as at least about 1.0. In some embodiments, Db / Da may be between 0.7 and about 1.5. Figure 13A-13C In the embodiment of FIG. 1 , the section 103 b of the stress buffer 103 contacts the conductive interconnect structure 109 of the second redistribution structure 110 b. The via 117 of the conductive interconnect structure 109 may directly contact the region of the stress buffer 103 , such as Fig. 13C In other embodiments, the stress buffer 103 may be electrically isolated from the conductive interconnect structure 109, such as Figure 7A-7C shown.

[0151] Fig.14 FIG. 1 is a vertical cross-sectional view of a semiconductor package 140 according to various embodiments of the present disclosure. The semiconductor package 140 includes a package structure 130 disposed above a first outer surface 114 of a package substrate 120 , wherein the package substrate 120 includes a plurality of stress buffer pads 103 . Fig.14 The package structure 130 may include one or more semiconductor IC dies 131. Fig.14 In the illustrated embodiment, the package structure 130 includes two semiconductor IC dies 131, but it should be understood that in other embodiments, the package structure 130 may include more than two semiconductor IC dies 131 or may include a single semiconductor IC die 131. One or more semiconductor IC dies 131 of the package structure 130 may include at least one system-on-chip (SoC) die. For example, the SoC die may include an application processor die, a central processing unit die, and / or a graphics processing unit die. In some embodiments, the one or more semiconductor IC dies 131 may include at least one memory die. The at least one memory die may include a high bandwidth memory (HBM) die. In some embodiments, the HBM die may include a vertical stack of interconnected memory dies. Alternatively or additionally, the at least one memory die may include a dynamic random access memory (DRAM) die. In some embodiments, the package structure 130 may include a plurality of homogenous semiconductor IC dies 131, which means that all semiconductor IC dies 131 may be of the same type (e.g., all SoC dies, all HBM dies, all DRAM dies, etc.). Alternatively, the package structure 130 may include a plurality of heterogenous semiconductor IC dies 131, which means that the plurality of semiconductor IC dies 131 may include semiconductor IC dies 131 of different types (e.g., at least one SoC die and at least one memory die).

[0152] In various embodiments, one or more semiconductor IC dies 131 of the package structure 130 may be mounted on an interposer 133, such as an organic interposer or a semiconductor (e.g., silicon) interposer. The interposer 133 may be mounted on the first outer surface 114 of the package substrate 120 to form a semiconductor package 140. The interposer 133 may include a plurality of interconnect structures 134 (e.g., metal lines and vias) within an insulating material. The one or more semiconductor IC dies 131 may be mounted on the interposer 133 via a plurality of bonding structures 135, the bonding structures 135 including microbump (e.g., chip connection (C2)) bonding structures. A first underfill material portion 138 may be disposed between the one or more semiconductor IC dies 131 and the interposer 133, and may surround the bonding structures 135. For example, the molding portion 139 may include an epoxy mold compound (EMC), and the molding portion 139 may laterally surround the one or more semiconductor IC dies 131.

[0153] Refer again Fig.14 , the pattern of the bonding pads 112 exposed in the first outer surface 114 of the package substrate 120 may correspond to the pattern of the bonding pads 137 located on the lower surface of the interposer 133. The package structure 130 may be aligned above the first outer surface 114 of the package substrate 120 so that the array of solder material portions 136 are located between the plurality of first bonding pads 112 of the package substrate 120 and the corresponding bonding pads 137 on the lower surface of the interposer 133. A reflow soldering process may be performed to reflow the solder material portions 136, thereby causing bonding between the interposer 133 of the package structure 130 and the package substrate 120. Each solder material portion 136 may be bonded to a corresponding one of the plurality of first bonding pads 112 of the package substrate 120 and to a corresponding one of the bonding pads 137 on the lower surface of the interposer 133. In some embodiments, the solder material portion 136 may include a controlled collapse chip connection (C4) solder ball, and the package structure 130 may be bonded to the package substrate 120 through the array of C4 solder balls.

[0154] In an alternative embodiment, the interposer 133 may be omitted, and one or more semiconductor IC dies may be directly mounted on the first outer surface 114 of the package substrate 120 , such as by a plurality of micro-bump (eg, C2 ) bonding structures.

[0155] Fig.15 FIG. 1 is a vertical cross-sectional view of a semiconductor package 140 according to various embodiments of the present disclosure, wherein the semiconductor package 140 includes a second underfill material portion 141 located between the first outer surface 114 of the package substrate 120 and the lower surface of the interposer 133 . Fig.15 The second bottom filling material portion 141 may be applied to the space between the first outer surface 114 of the package substrate 120 and the lower surface of the interposer 133. The second bottom filling material portion 141 may laterally surround and contact each solder material portion 136 that bonds the interposer 133 to the package substrate 120. A stiffening structure 142, such as a ring structure and / or a cap structure, may be mounted on the first outer surface 114 of the package substrate 120 and laterally surround the package structure 130.

[0156] Fig.16 FIG. 1 is a vertical cross-sectional view of a semiconductor package 140 mounted on a support substrate 150 according to various embodiments of the present disclosure. Fig.16 , the support substrate 150 may be a PCB including an array of bonding pads 153 exposed through an upper surface 151 of the support substrate 150. The pattern of the bonding pads 113 on the second outer surface 115 of the package substrate 120 may correspond to the pattern of the bonding pads 153 on the upper surface 151 of the support substrate 150. The semiconductor package 140 may be aligned above the upper surface 151 of the support substrate 150 so that the soldering material portion 154 is located between the bonding pads 113 on the second outer surface 115 of the package substrate 120 and the corresponding bonding pads 153 on the upper surface 151 of the support substrate 150. A reflow soldering process may be performed to reflow the soldering material portion 154, thereby causing bonding between the package substrate 120 and the support substrate 150 of the semiconductor package 140. Each soldering material portion 154 may be bonded to a corresponding one of the bonding pads 113 on the second outer surface 115 of the package substrate 120 and to a corresponding one of the bonding pads 153 on the upper surface 151 of the support substrate 150. As described above, the stress buffer pad 103 may cover at least some of the bonding pads 113 on the second outer surface 115 of the package substrate 120 .

[0157] Fig.17 FIG. 1 is a vertical cross-sectional view of a semiconductor package 140 mounted on a support substrate 150 according to various embodiments of the present disclosure, wherein the support substrate 150 includes a third bottom filling material portion 160. In some embodiments, the optional third bottom filling material portion 160 may be applied within the space between the second side 115 of the package substrate 120 and the upper surface 151 of the support substrate 150. The third bottom filling material portion 160 may laterally surround and contact each solder material portion 154 that bonds the package substrate 120 to the support substrate 150.

[0158] Refer again Fig.16 as well as Fig.17According to various embodiments, a semiconductor package 140 includes a package structure 130, which includes one or more semiconductor IC dies mounted on a first outer surface 114 of a package substrate 120. A second surface 115 of the package substrate 120 is mounted on an upper surface 151 of a support substrate 150 (e.g., a PCB) through a welding material portion 154, and the welding material portion 151 extends between a bonding pad 113 on the second surface 115 of the package substrate 120 and a bonding pad 153 on the upper surface 115 of the support substrate 150. A stress buffer 103 is located above at least some of the bonding pads 113 on the second surface 115 of the package substrate 120. The stress buffer 103 can relieve stress on the package substrate 120 and inhibit warping or cracking in the package substrate 120.

[0159] Fig.18 According to various embodiments of the present disclosure, a flow chart of a method 200 for manufacturing a package substrate 120 is shown. Figure 1 as well as Fig.18 In step 201 of the embodiment method 200, a substrate core 101 may be formed, the substrate core 101 including a first surface 105 and a second surface 106 opposite to the first surface 105. Figure 2 as well as Fig.18 In step 203 of the embodiment method 200 , a plurality of guide holes 107 and a core metal component 104 may be formed, wherein the core metal component 104 is located above the first surface 105 and above the second surface 106 of the substrate core 101 , and the plurality of guide holes 107 extend through the substrate core 101 and contact the core metal component 104 .

[0160] Reference Figure 3 as well as Fig.18 In step 205 of the embodiment method 200, a first redistribution structure 110a may be formed above the first surface 105 of the substrate core 101, wherein the first redistribution structure 110a includes a conductive interconnect structure 109 located within a dielectric material 108, a plurality of first bonding pads 112, and a passivation layer 111 defining a first outer surface 114 of the packaging substrate 120.

[0161] Reference Figure 4-13C as well as Fig.18In step 207 of the embodiment method 200, a second redistribution structure 110b may be formed above the second surface 106 of the substrate core 101, wherein the second redistribution structure 110b includes a conductive interconnect structure 109 located within the dielectric material 108, a plurality of second bonding pads 113, a passivation layer 111 defining a second outer surface 115 of the packaging substrate 120, and a stress buffer pad 103, wherein the stress buffer pad 103 is vertically separated from and at least partially overlaps with a bonding pad 113 of the plurality of second bonding pads 113, wherein a ratio of a minimum width dimension Db of the stress buffer pad 103 to a minimum width dimension Da of the bonding pad 113 is at least 0.7.

[0162] Referring to all the drawings and according to various embodiments of the present disclosure, a substrate 120 for a semiconductor package 140 may include a substrate core 101 and a redistribution structure 110b above a surface 106 of the substrate core 101, wherein the redistribution structure 110b includes a conductive interconnect structure 109 located within a dielectric material 108, a bonding pad 113, and a stress buffer pad 103 vertically separated from the bonding pad 113, wherein the stress buffer pad 103 is closer to the bonding pad 113 than to the surface of the substrate core 101.

[0163] In one embodiment, the ratio of the minimum width dimension Db of the stress buffer pad 103 to the minimum width dimension Da of the bonding pad is at least 0.7.

[0164] In another embodiment, the vertical separation distance between the bonding pad 113 and the stress buffer 103 is between 20 μm and 40 μm, and the dielectric material 108 included in the redistribution structure 110 b is located between the bonding pad 103 and the stress buffer 113 .

[0165] In another embodiment, the ratio of the minimum width dimension Db of the stress buffer pad 113 to the minimum width dimension Da of the bonding pad 113 is less than 1.5.

[0166] In another embodiment, the ratio of the minimum width dimension Db of the stress buffer pad 103 to the minimum width dimension Da of the bonding pad 113 is at least 1.0.

[0167] In another embodiment, the stress buffer pad 103 is electrically coupled to the conductive interconnect structure 109 and the bonding pad 113 of the redistribution structure 110 b .

[0168] In another embodiment, the substrate 120 further includes a solder resist layer, and the solder resist layer 111 covers a portion of the bonding pad 113 .

[0169] In another embodiment, the stress buffer pad 103 is electrically isolated from the conductive interconnect structure 109 and the bonding pad 113 of the redistribution structure 110 b .

[0170] In another embodiment, the stress buffer pad 103 and the bonding pad 113 are made of the same material.

[0171] In another embodiment, the Young's modulus of the material constituting the stress buffer 103 is higher than the Young's modulus of the material constituting the bonding pad 113 .

[0172] In another embodiment, the bonding pad 113 is made of metal material, and the stress buffer pad 103 is made of ceramic and / or semiconductor material.

[0173] In another embodiment, the stress buffer 103 includes a disk, a ring, a polygon or an irregular shape.

[0174] In another embodiment, the stress buffer 103 includes a multi-layer stress buffer 103 , and the multi-layer stress buffer 103 includes a lower structure 123 and an upper structure 125 , and the lower structure 123 and the upper structure 125 extend in different horizontal planes that are vertically offset from each other.

[0175] In another embodiment, the stress buffer 103 includes a plurality of separate sections, each of which at least partially overlaps with the bonding pad 113 .

[0176] An additional embodiment relates to a semiconductor package 140, which includes a semiconductor package structure 130 having one or more semiconductor IC chips 131, a package substrate 120 including a plurality of bonding pads 113 and a plurality of stress buffer pads 103, wherein each stress buffer pad 103 is vertically separated from and at least partially overlaps with a corresponding bonding pad 113 among the plurality of bonding pads 113, and a supporting substrate 150, wherein the semiconductor package structure 130 is mounted on a first side 114 of the package substrate 120, and a second side 115 of the package substrate 120 is mounted on the supporting substrate 150.

[0177] In one embodiment, the packaging substrate 120 includes a substrate core 101, which is located between a first side 114 and a second side 115 of the packaging substrate 120, and the stress buffer pads 103 are closer to the bonding pads 113 than to the substrate core 101, and wherein the ratio of the minimum width dimension of each stress buffer pad 103 to the minimum width dimension of the corresponding bonding pad is at least 0.7.

[0178] In another embodiment, the semiconductor package 140 further includes a solder resist layer 111 disposed on the second side 115 of the package substrate 120 , wherein the bonding pads 113 are exposed through a plurality of openings disposed in the solder resist layer 111 .

[0179] In another embodiment, the semiconductor package structure 130 includes an interposer 133 and a plurality of semiconductor IC dies 131, which are mounted on the upper surface of the interposer 133. The semiconductor package structure 130 is mounted on the first side 114 of the package substrate 120 through a plurality of solder connectors 136. The solder connectors 136 extend between the lower surface of the interposer 133 and the first side 114 of the package substrate 120. The support substrate 150 includes a PCB, and the package substrate 120 is mounted on a printed circuit board through a plurality of solder connectors 154. The solder connectors 154 extend between the bonding pads 113 located on the second side 115 of the package substrate 120 and the upper surface 151 of the printed circuit board.

[0180] An additional embodiment relates to a method for manufacturing a packaging substrate, which includes forming a conductive interconnect structure 109 within a dielectric material 108, wherein the dielectric material 108 is located above the surface of a substrate core 101, forming a stress buffer pad 103 above the conductive interconnect structure 109, and forming a bonding pad 113 above the stress buffer pad 103, wherein the stress buffer pad 103 is vertically separated from the bonding pad 113, and the stress buffer pad 103 and the bonding pad 103 at least partially overlap and form a passivation layer 111, and the passivation layer 111 covers a portion of the bonding pad 113.

[0181] In another embodiment, the ratio of the minimum width dimension Db of the stress buffer pad 103 to the minimum width dimension Da of the bonding pad 113 is at least 0.7.

[0182] The above summarizes the components of several embodiments so that those with ordinary knowledge in the art to which the present invention belongs can more easily understand the concepts of the embodiments of the present invention. Those with ordinary knowledge in the art to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art to which the present invention belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A substrate for semiconductor packaging, characterized in that: include: a substrate core; and A plurality of redistribution structures are disposed above a surface of the substrate core, wherein the redistribution structures include: a plurality of conductive interconnect structures disposed within a dielectric material; a bonding pad; and A stress buffer pad is vertically spaced apart from the bonding pad, wherein the stress buffer pad is closer to the bonding pad than to the surface of the substrate core.

2. The substrate for semiconductor packaging according to claim 1, wherein A ratio of a minimum width dimension of the stress buffer pad to a minimum width dimension of the bonding pad is at least 0.

7.

3. The substrate for semiconductor packaging according to claim 1, wherein A vertical separation distance between the bonding pad and the stress buffer pad is between 20 μm and 40 μm, and the dielectric material of the redistribution structure is located between the bonding pad and the stress buffer pad.

4. The substrate for semiconductor packaging according to claim 1, wherein: A ratio of a minimum width dimension of the stress buffer pad to a minimum width dimension of the bonding pad is less than 1.

5.

5. The substrate for semiconductor packaging according to claim 1 or 2, characterized in that: The stress buffer pad is electrically isolated from the conductive interconnect structure of the redistribution structure and the bonding pad.

6. The substrate for semiconductor packaging according to claim 1, wherein: The Young's modulus of the material constituting the stress buffer pad is higher than the Young's modulus of the material constituting the bonding pad.

7. The substrate for semiconductor packaging according to claim 1, wherein: The stress buffer pad includes a multi-layer stress buffer pad, which includes a lower structure and an upper structure. The lower structure and the upper structure extend in different horizontal planes that are vertically offset from each other.

8. A semiconductor package, characterized in that: include: A semiconductor package structure includes one or more semiconductor integrated circuit dies; A packaging substrate comprising a plurality of bonding pads and a plurality of stress buffer pads, wherein each of the stress buffer pads is vertically separated from and at least partially overlaps with a corresponding one of the bonding pads; and A supporting substrate, wherein the semiconductor package structure is mounted on a first side of the package substrate, and a second side of the package substrate is mounted on the supporting substrate.

9. The semiconductor package according to claim 8, wherein: The packaging substrate includes a substrate core, which is located between the first side and the second side of the packaging substrate, and the stress buffer pad is closer to the bonding pad than to the substrate core, and the ratio of the minimum width dimension of each stress buffer pad to the minimum width dimension of the corresponding bonding pad is at least 0.

7.

10. The semiconductor package according to claim 9, wherein: The semiconductor package structure comprises: an intermediary; and A plurality of semiconductor integrated circuit dies are mounted on an upper surface of the interposer, and the semiconductor package structure is mounted on the first side of the package substrate through a plurality of solder connectors, wherein the solder connectors extend between a lower surface of the interposer and the first side of the package substrate, and The supporting substrate includes a printed circuit board, and the packaging substrate is connected to the printed circuit board through a plurality of solder parts, and the solder connection parts extend between the bonding pad located on the second side of the packaging substrate and an upper surface of the printed circuit board.

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