Semiconductor structure

Abstract

The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a plurality of semiconductor devices, an interconnect structure, and a redistribution layout structure. A plurality of semiconductor devices are formed on a semiconductor substrate. An interconnect structure is disposed on the plurality of semiconductor devices. A redistribution layout structure is disposed over a semiconductor substrate, where the redistribution layout structure includes a plurality of redistribution layout metal features buried in a passivation layer, the plurality of redistribution layout metal features including a plurality of first conductive features longitudinally oriented along a first direction X and a plurality of second conductive features longitudinally oriented along a second direction X, the plurality of second conductive parts are longitudinally oriented along a second direction Y perpendicular to the first direction X; the XY ratio difference is defined as a difference between a first duty cycle of the plurality of first conductive members and a second duty cycle of the plurality of second conductive members, and the XY ratio difference is less than 1.

Description

Technical Field

[0001] The embodiments of the utility model relate to semiconductor technology, and in particular to semiconductor structure. Background Art

[0002] In the semiconductor industry, integrated circuits (ICs) are formed on semiconductor substrates and cut into IC chips. Each IC chip is further attached (such as by bonding) to a circuit board, such as a printed circuit board in an electronic product. In the prior art, the bonding pads of the chip are connected to the circuit board by wire bonding. In advanced technology, the circuit chip is flipped and directly bonded to the circuit board to reduce costs. In this technology, a redistribution layer of conductive metal wires is formed on the chip to reroute the bonding connection from the edge of the chip to the center. The existing structure of the redistribution layer and the corresponding method introduce various problems, such as substrate warpage due to stress, which further leads to passivation defects, circuit reliability concerns and other problems. Therefore, the present disclosure provides a redistribution layer structure and a method for making it to solve the above-mentioned problems. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0004] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor devices, an interconnect structure, and a redistribution layout structure. A plurality of semiconductor devices are formed on a semiconductor substrate. The interconnect structure is disposed on a plurality of semiconductor devices. The redistribution layout structure is disposed on a semiconductor substrate, wherein the redistribution layout structure includes a plurality of redistribution layout metal components embedded in a passivation layer, the plurality of redistribution layout metal components include a plurality of first conductive components and a plurality of second conductive components, the plurality of first conductive components are longitudinally oriented along a first direction X, and the plurality of second conductive components are longitudinally oriented along a second direction Y perpendicular to the first direction X; the XY ratio difference is defined as the difference between a first operating period of the plurality of first conductive components and a second operating period of the plurality of second conductive components, and the XY ratio difference is less than 1.

[0005] According to one embodiment of the present invention, an average spacing between the plurality of redistribution layout metal components is less than 3 μm; and the plurality of redistribution layout metal components include a plurality of dummy metal components, and each of the plurality of dummy metal components is isolated from other conductive components.

[0006] According to one embodiment of the present invention, the XY ratio difference is less than 30%.

[0007] According to one embodiment of the present invention, the passivation layer includes a first passivation layer and a second passivation layer, and the plurality of redistribution layout metal components are located between the first passivation layer and the second passivation layer.

[0008] According to one embodiment of the present invention, the first passivation layer includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, and a plurality of the redistribution layout metal components pass through the first dielectric material layer and the second dielectric material through a redistribution via and are in direct contact with a top metal line.

[0009] According to one embodiment of the present invention, the size of the redistribution via is between 5 μm and 20 μm.

[0010] According to one embodiment of the present invention, the first dielectric material layer is a silicon nitride layer with a thickness of to wherein the second dielectric material layer is an undoped quartz glass layer having a thickness of to between.

[0011] According to one embodiment of the present invention, the second passivation layer includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, and a plurality of the redistribution layout metal components are exposed from an opening in the first dielectric material layer and the second dielectric material layer.

[0012] According to one embodiment of the present invention, the size of the opening is between 10 μm and 30 μm.

[0013] According to one embodiment of the present invention, the first dielectric material layer is an undoped quartz glass layer with a thickness of to wherein the second dielectric material layer is a silicon nitride layer having a thickness of to between. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0015] Figure 1A The cross-sectional view of a semiconductor device structure having a redistribution layer (RDL) structure constructed in various ways according to the present disclosure is shown according to some embodiments.

[0016] Figure 1B The cross-sectional view shows a semiconductor device structure having an RDL structure and a fin active region constructed in various ways according to some other embodiments of the present disclosure.

[0017] Figure 1C The cross-sectional view shows a semiconductor device structure having an RDL structure and a multi-channel field effect transistor vertically stacked on a substrate constructed in various ways according to some other embodiments of the present disclosure.

[0018] Figure 2A The diagram is a perspective view showing a semiconductor structure constructed in various ways according to some other embodiments.

[0019] Figure 2B FIG. 1 is a top view showing a semiconductor structure constructed in various ways according to some other embodiments of the present disclosure.

[0020] Figure 2C , Figure 2D , Figure 2E and Figure 2F The cross-sectional view shows a semiconductor structure constructed in various ways according to some other embodiments of the present disclosure.

[0021] Figure 3A , Figure 3B , Figure 3C and Figure 3D The cross-sectional views of semiconductor structures constructed in various ways according to some other embodiments of the present disclosure are shown.

[0022] Figure 4 FIG. 1 is a flow chart showing a method for manufacturing the integrated circuit (IC) structure of FIG. 1 according to some embodiments.

[0023] Figure 5A , Figure 5B and Figure 5C FIG. 4 is a flow chart showing a method of manufacturing an integrated circuit (IC) structure according to some embodiments.

[0024] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 3 is a cross-sectional view showing an integrated circuit structure constructed during different manufacturing stages of the manufacturing method of FIG. 3 according to some embodiments.

[0025] Fig.12 , Fig.13 and Fig.14 FIG. 1 is a cross-sectional view showing RDL metal layers formed during different manufacturing stages according to some embodiments.

[0026] Fig.15 FIG. 4 is a cross-sectional view showing an integrated circuit structure having an RDL structure according to some embodiments.

[0027] The reference numerals are as follows:

[0028] 100:Semiconductor structure

[0029] 102:Substrate

[0030] 104: Isolation components

[0031] 106: Active area

[0032] 110: Integrated circuit device

[0033] 1102: Barrier layer

[0034] 120: Interconnection structure

[0035] 1202: Diffusion layer

[0036] 122: Interlayer dielectric layer

[0037] 124: Contact

[0038] 126: Metal wire

[0039] 128: Guide hole

[0040] 130: Top metal wire

[0041] 1302: Metal layer

[0042] 140: Redistribution layer structure

[0043] 142: Redistribution layer metal parts

[0044] 142X: first conductive component

[0045] 142Y: second conductive component

[0046] 144: first passivation layer

[0047] 144A: first dielectric material layer

[0048] 144B: second dielectric material layer

[0049] 146: Second passivation layer

[0050] 146A: first dielectric material layer

[0051] 146B: second dielectric material layer

[0052] 148: Redistribution vias

[0053] 150:Joint gasket

[0054] 152: Opening

[0055] 160: Channel

[0056] 162: Source

[0057] 164: Gate stack

[0058] 166: Gate spacer

[0059] 168:Internal spacer

[0060] 172: Gate dielectric layer

[0061] 174: Gate electrode

[0062] 180:Dummy component

[0063] 200: Method

[0064] 202~222,252~258,302~312,402~418: Operation

[0065] 602: Redistribution vias DETAILED DESCRIPTION

[0066] The following disclosure provides different embodiments or examples for implementing different components of the subject matter provided. Component symbols and / or characters may be repeated in various examples herein. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed. In addition, specific examples of each component and its configuration are described below to simplify the description of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, if the first component is formed on the second component in the description, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which an additional component is formed between the first and second components so that they are not in direct contact. In addition, the steps of forming a component on another component, forming a component to be connected to and / or coupled to another component in the present disclosure may include an example of forming the above-mentioned components that are directly connected, and may include forming an additional component and inserting it between the above-mentioned components so that the above-mentioned components are not in direct contact.

[0067] Furthermore, the present invention may repeat component symbols and / or characters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not used to represent the relationship between the different embodiments and / or configurations discussed. In addition, the steps of forming a component on another component, forming a component to be connected to and / or coupled to another component in the present disclosure may include examples of forming directly connected components, and may include examples of forming additional components and inserting them between the components so that the components are not in direct contact. In addition, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "up", "down", "top", and "bottom" and the like (e.g., "horizontally", "downwardly", and "upwardly", etc.) may be used to facilitate description of the relationship between one component and another component in the drawings. Spatially relative terms are used to include different orientations of the device. Furthermore, when "approximately", "substantially", and the like are used to describe a numerical value or a numerical range, the terms are intended to cover a reasonable range of the described numerical value, such as between 10% of the described numerical value, or other values ​​recognized by a person skilled in the art. For example, the term "about 5 nm" covers a size range between 4.5 nm and 5.5 nm.

[0068] Figure 1A In one embodiment, a cross-sectional view of an integrated circuit (IC) structure (or semiconductor structure, or workpiece) 100 constructed according to various aspects of the present disclosure is shown. Figure 1B is a cross-sectional view of a semiconductor structure 100 having a fin active region according to other embodiments. Figure 1C FIG. 2 is a flow chart of a method 200 for manufacturing the semiconductor structure 100 according to some embodiments. The semiconductor structure 100 and the method 200 for manufacturing the semiconductor structure 100 will be described with reference to FIG. Figure 1A , Figure 1B , Figure 1C In some embodiments, the semiconductor structure 100 includes a planar active region on which various IC devices are formed, such as planar field-effect transistors (FETs), such as Figure 1AIn some embodiments, the semiconductor structure 100 includes a fin-shaped active region on which various IC devices are formed, such as Figure 1B In some embodiments, the semiconductor structure 100 includes a field effect transistor structure having a plurality of channels stacked vertically, such as Figure 1C shown.

[0069] The semiconductor structure 100 includes a substrate 102. The substrate 102 includes a bulk silicon substrate. Alternatively, the substrate 102 may include: an elemental semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or a combination thereof. Possible substrates 102 also include silicon-on-insulator (SOI) substrates. SOI substrates are manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0070] The substrate 102 also includes various isolation features, such as isolation features 104 formed on the substrate 102 and defining various active regions, such as active region 106, on the substrate 102. The isolation features 104 utilize isolation technology, such as shallow trench isolation (STI), to define and electrically isolate the various active regions. The isolation features 104 include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation features 104 are formed by any suitable process. As an example, the steps of forming the STI features include: a photolithography process to expose a portion of the substrate; etching a trench in the exposed portion of the substrate (e.g., by using dry etching and / or wet etching); filling the trench with one or more dielectric materials (e.g., by using a chemical vapor deposition process); and planarizing the substrate and removing excess portions of the dielectric material by a polishing process, such as a chemical mechanical polishing (CMP) process. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner and a filling layer of silicon nitride or silicon oxide.

[0071] The active region 106 is a region having a semiconductor surface in which various doped components are formed and configured into one or more devices, such as diodes, transistors, and / or other suitable devices. The active region may include a bulk semiconductor material similar to the substrate 102 (such as silicon) or a different semiconductor material, such as silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (such as alternative silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth for performance enhancement, such as strain effects to increase carrier mobility.

[0072] exist Figure 1B In some embodiments shown, the active region 106 is three-dimensional, such as a fin active region extending above the isolation feature 104. The fin active region is extruded from the substrate 102 and has a three-dimensional profile to more effectively couple the channel region (or simply referred to as a channel) with the gate electrode of the field effect transistor (FET). The fin active region 106 can be formed by selectively etching to recess the isolation feature 104, selective epitaxial growth to grow an active region with the same or different semiconductor from the substrate 102, or a combination thereof.

[0073] The semiconductor substrate 102 also includes various doped components, such as n-type doped wells, p-type doped wells, sources and drains, other doped components, or combinations thereof, which are configured to form various devices or components of devices. The semiconductor structure 100 includes various IC devices 110 formed on the semiconductor substrate 102. The IC devices include fin field-effect transistors (FinFETs), diodes, bipolar transistors, image sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. Figure 1A (or Figure 1B ) the FETs are provided for illustration only.

[0074] exist Figure 1C In some embodiments shown, the semiconductor structure 100 includes one or more FETs with multi-bridge-channel (MBC). The MBC transistor has a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the MBC transistor can also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor with multiple channels stacked vertically. Figure 1COnly a portion of the semiconductor structure 100 is shown, particularly the substrate 102 and the MBC device formed thereon. The interconnect structure 120 including the bonding pad structure and the redistribution layer (RDL) structure 140 and Figure 1A and Figure 1B , which will be described in detail below. In particular, the semiconductor structure 100 includes a FET having a plurality of channels 160 stacked vertically on a substrate 102. The FET also includes a source / drain (S / D) component 162 disposed on opposite edges of the channel 160 and connected to the channel 160. The FET also includes a gate stack 164 inserted between the S / D components 162 and extending to wrap around each of the plurality of vertically stacked channels 160. The FET may further include a gate spacer 166 disposed on the sidewalls of the gate stack 164 and an inner spacer 168 disposed between the gate stack 164 and the S / D components 162 to provide isolation. The gate spacer 166 and the inner spacer may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate stack 164 includes a gate dielectric layer 172 and a gate electrode 174 on the gate dielectric layer 172.

[0075] In some other embodiments, the semiconductor structure 100 includes one or more complementary FETs (CFETs), wherein each pair of a p-type FET and an n-type FET are vertically stacked.

[0076] Continue to refer to Figure 1A , the semiconductor structure 100 also includes an interconnect structure formed on the semiconductor substrate 102. The interconnect structure includes various conductive components to couple various IC devices into an integrated circuit. The interconnect structure also includes an interlayer dielectric (ILD) layer 122 to separate and isolate various conductive components. For example, the interconnect structure includes contacts 124, metal lines 126, and vias 128. The metal lines 126 are distributed in multiple metal layers, such as a first metal layer, a second metal layer above the first metal layer, ... and a top metal layer. Figure 1A, four metal layers are shown. The top metal line is individually labeled with element symbol 130. The contact 124 provides vertical circuit routing from the semiconductor substrate 102 to the metal line. The guide hole 128 provides vertical circuit routing between adjacent metal layers. Various conductive components are formed by one or more conductive materials, such as metals, metal alloys or silicides. For example, the metal line 126 may include copper, aluminum copper alloy, other suitable conductive materials or combinations thereof. The guide hole 128 may include copper, aluminum copper alloy, other suitable conductive materials or combinations thereof. The contact 124 may include tungsten, silicide, nickel, cobalt, copper, ruthenium, other suitable conductive materials or combinations thereof. In some examples, the various conductive components may also include barrier layers, such as tantalum and tantalum nitride, titanium and titanium nitride. In the present embodiment, the top metal line 130 includes copper.

[0077] The ILD layer 122 includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive components (such as metal lines, contacts, and vias). The ILD layer 122 includes dielectric materials such as silicon oxide, low dielectric constant (low-k) dielectric materials, other suitable dielectric materials, or combinations thereof. In some examples, the low-k dielectric material includes fluorinated silica glass (FSG), carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polyimide, and / or other suitable dielectric materials having a dielectric constant substantially lower than that of thermal silicon oxide. The steps of forming the ILD layer 122 include, for example, deposition and CMP. Deposition may include spin-on coating, CVD, other suitable deposition techniques, or combinations thereof. The ILD layer 122 may include multiple film layers and be formed together with various conductive features in a suitable process such as a damascene process.

[0078] In some embodiments, the interconnect structure or a portion thereof is formed by deposition and patterning. For example, a metal (or metal alloy) such as aluminum copper is deposited by physical vapor deposition (PVD) and then patterned by photolithography and etching. An ILD layer is then disposed thereon by deposition (and CMP). In some embodiments, the interconnect structure 120 uses a damascene process to form metal lines. In a damascene process, an ILD layer is deposited; it may be further planarized by CMP; and then patterned by photolithography and etching to form trenches. One or more conductive materials are deposited to fill the trenches, and another CMP process is applied to remove excess conductive material and planarize the top surface to form conductive components. A damascene process can be used to form metal lines, vias, and contacts. A dual damascene process can be applied to form a layer of metal lines and vias adjacent to the metal lines. In this case, the ILD layer is deposited and patterned twice to form trenches and vias, respectively. Metal is then deposited to fill the trenches and vias to form metal lines and vias.

[0079] The semiconductor structure 100 also includes a redistribution layer (RDL) structure 140 disposed on the interconnect structure to redistribute the bonding pads, such as from the edge to the center of the IC chip and integrate the IC chip into a substrate (e.g., a printed circuit board) using flip chip bonding or other suitable packaging technology.

[0080] The RDL structure 140 includes a passivation layer and an RDL metal component 142 buried in the passivation layer. In particular, the RDL metal component includes a portion extending in an opening 152 of the passivation layer, and these portions serve as bonding pads 150, and are therefore also referred to as bonding pads 150. In various embodiments, the RDL conductive component (or RDL metal component) 142 of the RDL structure 140 is a metal line distributed in one or more metal layers. The RDL metal component is different from the metal line in the interconnect structure 120. For example, the RDL metal component 142 is buried in the passivation layer and serves as a redistribution and bonding pad.

[0081] In the present embodiment, the passivation layer includes a first passivation layer 144 and a second passivation layer 146 disposed on the first passivation layer 144. The first passivation layer 144 includes a redistribution via (RV) aligned with the top metal line 130, so that a portion 148 of the RDL metal component 142 is formed in the RV and directly contacts the top metal line 130. The portion 148 of the RDL metal component 142 in the redistribution via is also referred to as the RV 148. The RDL metal component 142 extends vertically from the first passivation layer 144 to the second passivation layer 146, and extends horizontally from the RV 148 to the opening 152 for redistribution of the bonding pad. The portion of the RDL metal component 142 exposed from the opening 152 is also referred to as the bonding pad 150.

[0082] In the present embodiment, the first passivation layer 144 includes a silicon nitride (SiN) layer and an undoped silica glass (USG) layer on the SiN layer, and the second passivation layer 146 includes a USG layer and a SiN layer disposed on the USG layer. In the present embodiment, the RDL metal component 142 includes a barrier layer, a diffusion layer disposed on the barrier layer, and an aluminum-copper alloy layer disposed on the diffusion layer. The barrier layer may also include a tantalum film and a tantalum nitride film disposed on the tantalum film. The diffusion layer is a metal oxide. In the present embodiment, the diffusion layer includes tantalum, oxygen, aluminum, and nitrogen. The RDL structure 140, and in particular the RDL metal component 142, will be further described below.

[0083] The RDL metal features 142 of the RDL structure 140 are designed with an appropriate layout to achieve the intended purpose, including redistributing the bonding pads 150. However, the RDL metal features 142 have relatively large sizes relative to the metal lines in the interconnect structure 120. In some examples, the RDL metal features 142 are lines with a width ranging between 1.5 μm and 30 μm. The RDL metal features 142 have a thermal expansion coefficient that is different from that of the passivation layer material. This may introduce thermal stress and cause deformation of the substrate, such as warping. In the described embodiment, the semiconductor structure is a chip of appropriate size. The semiconductor structure is formed on a semiconductor wafer and then cut into chips.

[0084] Figure 2A is a perspective view of a portion of a semiconductor structure 100 constructed according to some examples. In particular, Figure 2AOnly the RDL metal part 142 is shown. When the RDL metal part 142 on the substrate is mainly oriented along one direction such as the X direction, the stress from the RDL metal part 142 may cause the substrate to bend along the Y direction, thereby causing quality and reliability issues. The present disclosure provides a structure of the RDL metal part 142 and a method for manufacturing the same. In particular, the structure of the RDL metal part 142 includes a layout of the RDL metal part 142, wherein the layout is configured to reduce stress-reduced deformation.

[0085] like Figure 2B As shown, the surface of the substrate spans two orthogonal directions (X and Y directions), and the normal direction of the surface is the Z direction, where the X, Y and Z directions constitute a Cartesian coordinate system. Through experimental and theoretical analysis, it is found that warping depends not only on the magnitude of stress, but also on the distribution of stress, especially the direction of stress. More specifically, it is found that the layout of the RDL structure 140 is the main factor contributing to the deformation of the substrate, and the layout includes the duty ratio and the spacing of the RDL metal parts 142. According to the present disclosure, the RDL metal parts 142 of the RDL structure 140 are modified in various ways, including dummy insertion and adjusting the RDL metal parts, so as to achieve a layout of the RDL structure 140 with minimized or eliminated deformation. The method is described in detail.

[0086] Figure 4 2 is a flow chart of a method 200 constructed according to some embodiments. The method 200 begins at operation 202, which receives an IC layout defining a semiconductor structure, such as Figure 1A , Figure 1B or Figure 1C1. In the semiconductor structure 100 of FIG. 1 . In particular, the IC layout of the semiconductor structure includes a layout of an RDL structure 140 having a plurality of RDL metal parts 142. According to some embodiments, the RDL metal part 142 is a wire with a width ranging between 1.5 μm and 30 μm. The RDL metal part 142 includes a first conductive part 142X longitudinally oriented along the X direction and a second conductive part 142Y longitudinally oriented along the Y direction. In the disclosed example of the IC layout, the first conductive part 142X and the second conductive part 142Y are unbalanced. This can be evaluated by an XY ratio gap. The XY ratio gap is defined as the relative difference between the X duty cycle and the Y duty cycle. In addition, the X duty cycle is defined as the total area of ​​the first conductive part 142X in the entire substrate area of ​​the substrate, and the Y duty cycle is defined as the total area of ​​the second conductive part 142Y in the entire substrate area. When the XY ratio gap is large, the RDL metal part 142 is unbalanced and there is a risk of deformation, such as warping. The XY ratio difference may be negative or positive. Generally speaking, the XY ratio difference is usually greater than -1 and less than 1, or between -1 and 1.

[0087] Method 200 proceeds to operation 204, which determines the standard of the RDL metal part based on the manufacturing data (or production data). The standard of the RDL metal part 142 is one or more values ​​used to evaluate whether the RDL structure 140 has stress-induced deformation. When the RDL metal part 142 of the RDL structure 140 exceeds the standard, the RDL structure 140 needs to be modified to eliminate or minimize the deformation. The standard should be determined based on manufacturing data collected from IC manufacturers (or IC factories for short). The manufacturing data is related to similar products because different products may have different standards. In the disclosed embodiment based on experimental and theoretical analysis, two rules are used as standards. Specifically, the standard includes a first standard related to the XY ratio difference and a second standard related to the spacing, which will be further described. The XY ratio difference is defined as above. The spacing is defined as the spacing dimension between parallel RDL metal parts 142. In some embodiments, the spacing is defined as the average spacing S between the first conductive parts 142X. x , if they dominate. In some embodiments, the spacing is defined as the average spacing S between the second conductive components 142Y y , if they dominate. In some embodiments, the spacing is defined as S x and S y The average value of .

[0088] The first criterion is a positive value related to the XY ratio difference and is less than 1. In some embodiments, the first criterion is 30%. If the absolute value of the XY ratio difference is greater than 30%, the RDL structure 140 needs to be modified. In particular, the XY ratio difference can be positive or negative. If the X duty cycle is greater than the Y duty cycle, the XY ratio difference is positive. If the X duty cycle is less than the Y duty cycle, the XY ratio difference is negative. When the XY ratio difference is positive, the semiconductor structure has a Y direction. Figure 2D The significant warping shown in FIG. 1 is shown in FIG. 1 , but along the X direction there is a Figure 2C When the XY ratio difference is negative, the semiconductor structure has a substantially smaller warpage along the X direction. Figure 2E The significant warping shown in FIG. 1 is shown in FIG. 1 , but along the Y direction there is a Figure 2F Significantly less warpage is shown.

[0089] In some embodiments, the second standard is a pitch of 3 μm. If the pitch is greater than 3 μm, there is a warpage problem and the RDL structure 140 needs to be modified. In some embodiments, the standard may be different, depending on the product and manufacturing data.

[0090] The method 200 proceeds to operation 206, which evaluates the RDL structure 140, and in particular the RDL metal features 142 of the RDL structure 140, according to the determined criteria. In the disclosed embodiment, if the first criterion, the second criterion, or either criterion is not met, the RDL structure does not meet the criterion. If both criteria are met, the RDL structure 140 passes the criterion. If the RDL structure passes the criterion, the method 200 proceeds to operation 218. If the RDL structure does not pass the criterion, the method 200 proceeds to operation 208 or operation 210. Furthermore, operations 208 and 210 may be performed in parallel, in series, or alternatively in one of the two. In the example shown in FIG. Figure 3A In some embodiments shown, the RDL metal features 142 are primarily oriented along the X direction. The X duty cycle is approximately 50%, and the Y duty cycle is approximately 4.8%. Therefore, the XY ratio difference is estimated to be approximately 45.2%, which is greater than 30%.

[0091] Operation 208 includes inserting dummy components into the RDL structure 140. The dummy components are similar to the RDL metal components 142 in terms of composition and formation, but are not intended for connection for circuit routing, but are added to adjust the duty cycle so that the XY ratio difference is reduced. Specifically, each dummy component is isolated from other conductive components. Figure 3A In some embodiments shown, the XY ratio difference of the RDL metal feature 142 is greater than 30% (as described above) and is mainly oriented along the X direction, and dummy features are added to increase the Y duty cycle to produce Figure 3BThe modified RDL structure 140 is shown. In a further embodiment, the dummy component 180 is longitudinally oriented along the Y direction. After inserting the dummy component 180, the XY ratio difference is less than 30%, such as about 27.2%.

[0092] In particular, the XY ratio difference can be positive or negative, such as Figure 2C to Figure 2F If the XY ratio difference is a positive value, which indicates that the X duty cycle is greater than the Y duty cycle, the dummy component 180 is longitudinally oriented along the Y direction to increase the Y duty cycle and reduce the absolute value of the XY ratio difference. If the XY ratio difference is a negative value, which indicates that the X duty cycle is less than the Y duty cycle, the dummy component 180 is longitudinally oriented along the X direction to increase the X duty cycle and reduce the absolute value of the XY ratio difference.

[0093] Operation 208 for dummy insertion can be rule-based or alternatively model-based. For example, a rule-based approach includes inserting dummy components with predetermined sizes and appropriate positions. In another example, a model-based approach includes inserting dummy components with positions, shapes, and sizes according to a simulation model such that the XY ratio difference is effectively reduced.

[0094] Operation 210 is different from operation 208, and it includes adjustment rather than addition. Adjusting the RDL metal parts 142 of the RDL structure 140 in operation 210 can be achieved in various ways, including: sub-operation 212, which repositions the RDL metal parts 142; sub-operation 214, which resizes the RDL metal parts 142; and other suitable sub-operations, such as reshaping the RDL metal parts 142. In sub-operation 212, the step of repositioning the RDL metal parts 142 includes changing the position of one or more RDL metal parts 142 to adjust the spacing. In sub-operation 214, the step of resizing the RDL metal parts 142 includes changing the size of one or more RDL metal parts 142 to adjust the spacing. For example, the size of the first conductive part 142X or a subset thereof oriented longitudinally along the X direction is resized so that the corresponding width is reduced, thereby increasing the spacing.

[0095] Operation 208 and operation 210 are not independent but interrelated. For example, inserting dummy features through operation 208 may also affect the pitch, such as reducing the pitch. In another example, adjusting the RDL metal features 142 through operation 210 may also affect the XY ratio difference.

[0096] As described above, adjusting the RDL metal features 142 in operation 210 may include one or more sub-operations, which may be performed sequentially, in parallel, or alternatively using only one or a subset of the sub-operations. In some embodiments, the pitch of the RDL metal features 142 is greater than a predetermined value, such as 3 μm. In particular, the second conductive features 142Y have an average pitch greater than 3 μm, such as Figure 3C The RDL structure shown in Figure 3C In the illustrated embodiment, the second conductive component 142Y is resized to increase the width, and the second conductive component 142Y is additionally repositioned to produce the following Figure 3D The modified RDL structure 140 is shown. Therefore, the pitch of the RDL structure 140 is reduced to below a predetermined value, such as 3 μm.

[0097] After operations 208 and 210 or a subset thereof, the method 200 proceeds to operation 216, which evaluates the modified RDL structure 140 according to predetermined criteria. If the modified RDL structure 140 does not meet the predetermined criteria, such as the first criteria and the second criteria, the method 200 returns to operations 208 and 210. Operations 208 and 210 may be implemented in multiple loops until the modified RDL structure 140 passes the predetermined criteria. If the modified RDL structure 140 passes the predetermined criteria, such as the first criteria and the second criteria, the method 200 proceeds to operation 218.

[0098] Operation 218 generates a tape-out for mask fabrication based on this modified IC design layout, which includes a modified RDL structure 140, which also includes an RDL metal component 142, a modified RDL metal component (such as 182Y) and a dummy component 180 or a subset thereof. The tape-out defines a modified IC design, which will be formed on a photoresist mask for wafer fabrication or directly transferred to a semiconductor wafer by a direct writing technique such as electron-beam direct writing. The tape-out of the modified IC design includes various patterned layers (such as film layers of active areas, film layers of gate stacks, etc.) and the spatial relationships between these patterned layers, in particular, the various shapes and sizes of each patterned component. In the present disclosure, the modified IC layout defined in the tape-out includes a modified RDL structure 140 of the semiconductor structure 100.

[0099] In some embodiments, the method 200 further includes an operation 220 of fabricating a photoresist mask according to a tape-out line that defines a modified IC layout of the semiconductor structure 100 having the modified RDL structure 140 .

[0100] In some embodiments, the method 200 further includes an operation 222 to use the above-mentioned photoresist mask to manufacture the semiconductor structure 100 having the modified RDL structure 140. In particular, the operation 222 includes manufacturing the RDL structure 140 using the photoresist mask defining the modified RDL structure 140. The method 200 of manufacturing the semiconductor structure 100 having the modified RDL structure 140 will be further described below according to some embodiments.

[0101] Figure 5A 2 is a flow chart of a method 222 of manufacturing a semiconductor structure 100 according to some embodiments. Some manufacturing details are provided above and are not repeated here. The method 222 includes: an operation 252, which forms an isolation component 104 on a semiconductor substrate 102; an operation 254, which forms various IC devices (such as FETs, FinFETs, CFETs, diodes, passive devices, image sensors, memory cells, other suitable IC devices or combinations thereof) on the semiconductor substrate 102; an operation 256, which forms an interconnect structure (such as a contact 124, a metal line 126, a guide hole 128 and a top metal line 130) by a suitable method such as a damascene process; and an operation 258, which forms an RDL structure 140. The method 222 may include other operations before, during, or after the above operations. The method of forming the RDL structure 140 is further described in detail below.

[0102] Figure 5B is a flow chart showing a method 258 of forming the RDL structure 140 according to some embodiments, Figure 5C is a flow chart of a method 306 of forming the RDL metal feature 142 . Figures 6 to 15 is a cross-sectional view of a semiconductor structure 100 at various stages of fabrication according to some embodiments. Figures 6 to 15 The method 258 and the semiconductor structure 100 are collectively described.

[0103] Reference Figure 5B Box 302 and Figure 6 , method 258 includes the operation of depositing a first passivation layer 144 on the interconnect structure 120. For simplicity, Figure 6 (and other figures) skip some components on the substrate 102 and the interconnect structure 120 (such as the isolation component 104, the IC device, the contact 124, the metal line 126 and the via 128). The first passivation layer 144 includes one or more dielectric material layers. In the present embodiment, the first passivation layer 144 includes a first dielectric material layer 144A and a second dielectric material layer 144B disposed on the first dielectric material layer 144A. In a further embodiment, the first dielectric material layer 144A includes silicon nitride (SiN) with a thickness of about 100 Å. to and the second dielectric material layer 144B comprises undoped silica glass (un-doped silica glass, USG), having a thickness of to The first passivation layer 144 is deposited by a suitable deposition technique, such as CVD, high density plasma CVD (HDPCVD), other suitable techniques or combinations thereof. Operation 302 may include multiple steps to deposit a dielectric material layer having a different material than the previous material (precursors).

[0104] Reference Figure 5B Box 304 and Figure 7 , method 258 includes the operation of patterning the first passivation layer 144 to form an RV 602, which is aligned with the corresponding top metal line 130 so that the corresponding top metal line 130 is exposed within the RV 602. In some embodiments, the size of the RV 602 is between 5μm and 20μm. The patterning process in operation 304 includes a photolithography process and an etching process. In some examples, a patterned photoresist layer is formed by a photolithography process, and the photolithography process also includes spin coating, exposure, development, and one or more baking steps. An etching process is applied to the first passivation layer 144 through the opening of the patterned photoresist (or photoresist) layer to form an RV guide hole in the first passivation layer. The etching process may include dry etching, wet etching, or a combination thereof. The etching process may include multiple etching steps of etching each dielectric material layer using different etchants. For example, the etching process may include a first etching process of etching the USG layer 144B using buffered hydrofluoric acid and etching the SiN layer 144A using phosphoric acid. In some examples, operation 304 may use a patterned hard mask to define an area for the RV via. The steps of forming the patterned hard mask may include: depositing a hard mask layer; forming a patterned photoresist layer by a photolithography process; etching the hard mask through an opening of the patterned photoresist layer; and removing the patterned photoresist layer by wet stripping or plasma ashing.

[0105] Reference Figure 5B Block 306 and Figure 8 The method 258 includes an operation of forming an RDL layer (also, an RDL metal feature 142) on the first passivation layer 144 and on the top metal line 130 in the RV 602. The RDL layer 142 directly contacts the top metal line 130 through the RV via. The RDL layer 142 includes a plurality of film layers formed by a plurality of steps. The structure and formation of the RDL layer 142 will be described in further detail below.

[0106] Reference Figure 5B Box 308 and Fig. 9 , method 258 proceeds to an operation of patterning the RDL layer 142 to form an RDL metal component (still represented by element symbol 142). The patterning process in operation 308 includes a photolithography process and etching. Similarly, a patterned photoresist layer is formed by a photolithography process; an etching process is performed on the RDL metal layer to form an RDL metal component. The etching process may include dry etching, wet etching, or a combination thereof. The etching process may include multiple etching steps of etching corresponding film layers in the RDL metal layer using different etchants. In some examples, operation 308 may use a patterned hard mask to define the area of ​​the portion of the RDL metal layer to be removed.

[0107] After operation 308 is completed, RDL metal features 142 are formed on the first passivation layer 144. Each RDL metal feature 142 includes a portion 148, also referred to as an RV 148, extending vertically to and directly contacting a corresponding top metal line 130.

[0108] Reference Figure 5B Block 310 and Fig.10 The method 258 includes an operation of depositing a second passivation layer 146 on the first passivation layer 144 and the RDL metal feature 142. The second passivation layer 146 includes one or more dielectric material layers. In the present embodiment, the second passivation layer 146 includes a first dielectric material layer 146A and a second dielectric material layer 146B disposed on the first dielectric material layer 146A. In further embodiments, the first dielectric material layer 146A includes USG and has a to and the second dielectric material layer 146B includes SiN and has a thickness between to The second passivation layer 146 is deposited by a suitable deposition technique, such as HDPCVD, other suitable techniques, or combinations thereof. Operation 310 may include multiple steps to deposit a dielectric material layer having a different material than the previous material.

[0109] Reference Figure 5B Box 312 and Fig.11, method 258 includes the operation of patterning the second passivation layer 146 to form an opening 152. Portions 150 of the RDL metal features 142 are exposed within the corresponding openings 152. The portions 150 serve as bonding pads. For example, solder balls may be further formed on the bonding pads 150 and connected to corresponding conductive features in the circuit board during wafer-level chip bonding. In some embodiments, the size of the openings 152 is between 10 μm and 30 μm. The RDL metal features 142 extend vertically from the second passivation layer 146 to the first passivation layer 144 to directly contact the corresponding top metal line 130 within the RV vias, and extend horizontally from the RV 148 to the bonding pads 150 to redistribute the bonding positions, such as from the edge of the chip to the center of the chip.

[0110] The patterning process in operation 312 includes a photolithography process and an etching process. In some examples, a patterned photoresist layer is formed by a photolithography process. An etching process is applied to the second passivation layer 146 through the opening of the patterned photoresist layer to form an opening 152 in the second passivation layer 146. The etching process may include dry etching, wet etching, or a combination thereof. The etching process may include multiple etching steps for etching each dielectric material layer using different etchants. For example, the etching process may include a first etching process for etching the USG layer 146A using buffered hydrofluoric acid and etching the SiN layer 146B using phosphoric acid. In some examples, operation 312 may define the opening 152 using a patterned hard mask.

[0111] Now continue to refer to Figure 5B , the operation 306 of forming the RDL layer 142 was previously described, and now with reference to Figure 5C and Figure 12 to Figure 14 Described in further detail. Figure 5C is a flow chart of a method 306 of forming the RDL layer 142; and Figure 12 to Figure 14 is a cross-sectional view of an RDL metal layer at various manufacturing stages according to some embodiments. Figure 12 to Figure 14 Only various conductive films of the RDL layer 142 are shown.

[0112] Reference Figure 5C At block 402, method 306 includes performing a degas process on semiconductor structure 100. The degas process is performed in a high temperature inert gas environment (e.g., argon) to dehydrate semiconductor structure 100. According to some examples, the degas process is performed at a temperature range between 200° C. and 400° C., and the duration of the degas process is between 30 seconds and 300 seconds. In the present embodiment, the degas process is performed in a PVD tool, such as a PVD cluster tool having multiple processing chambers.

[0113] Reference Figure 5C At block 404 of method 306 , a remote-plasma-cleaning (RPC) process is performed on the semiconductor structure 100 to clean the semiconductor structure 100 , particularly the top metal line 130 . The RPC process removes particles, residues and other contaminants from the top metal line. The RPC process is performed in a gas environment under plasma conditions. In the present embodiment, the RPC process includes hydrogen and helium at room temperature. According to some examples, hydrogen accounts for 3% to 10% (atomic percentage) of the gas, and helium accounts for 97% to 90% of the gas. In some examples, the gas pressure ranges from 10 mTorr to 30 mTorr. The EF power for generating the plasma is between 500 W and 1500 W. The RPC process duration is between 30 seconds and 300 seconds. In the present embodiment, the RPC process is implemented in the same PVD tool.

[0114] Reference Figure 5C Block 406 and Fig.12 , method 306 includes the operation of depositing a barrier layer 1102 on the first passivation layer 144 and the top metal line 130 in the RV via. The barrier layer 1102 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), other suitable materials or combinations thereof. In the present embodiment, the barrier layer 1102 includes a Ta film 1102A and a TaN film 1102B. In some examples, the thickness of the Ta film 1102A is between 100 and 150 mm. to and the thickness of the TaN film 1102B is between to In this embodiment, the barrier layer 1102 is also deposited in the same PVD tool. For example, in one deposition chamber, tantalum is deposited using a tantalum target, and then tantalum nitride is deposited using additional nitrogen in the same chamber or in a different deposition chamber. In this embodiment, the barrier layer 1102 has a polycrystalline structure.

[0115] Reference Figure 5C At block 408, method 306 performs a cooling process on semiconductor structure 100. For example, the cooling process is performed in an inert gas (eg, argon) environment for a suitable duration, such as a duration between 20 seconds and 60 seconds. The cooling process is also performed in the same PVD tool.

[0116] Reference Figure 5C Block 410 and Fig.13Method 306 includes performing an oxidation treatment on barrier layer 1102 to form diffusion layer 1202. Diffusion layer 1202 is a metal oxide layer including oxygen and metal. In this embodiment, diffusion layer 1202 includes oxygen and tantalum. In other embodiments, diffusion layer 1202 also includes nitrogen. The thickness of diffusion layer 1202 can be to The diffusion layer 1202 has a gradient composition with a maximum oxygen concentration at the top surface of the diffusion layer 1202. In some examples, the maximum oxygen concentration is greater than 35% (atomic percentage) but less than 45%. In this embodiment, the diffusion layer 1202 has an amorphous structure, and the barrier layer 1102 has a polycrystalline structure.

[0117] During the oxidation process, oxygen diffuses into the barrier layer 1102. The oxidation process is also performed in the same PVD tool. The oxidation process is performed in an oxygen environment at room temperature with an oxygen flow rate between 1 sccm and 20 sccm. In some embodiments, plasma can be applied to the oxygen with a low plasma power, such as between 500 W and 1500 W, so that the oxygen concentration is controlled at a low level to maintain a suitable contact resistance.

[0118] Reference Figure 5C At block 412 of the method 306 , after forming the barrier layer 1102 and the diffusion layer 1202 , a second degassing process is performed on the semiconductor structure 100 . In operation 402 , the second degassing process is similar to the first degassing process. For example, the second degassing process is performed in a high temperature argon environment to dehydrate the semiconductor structure 100 . According to some examples, the degassing process is performed at a temperature between 200° C. and 400° C., and the degassing duration is between 30 seconds and 300 seconds. In the present embodiment, the degassing process is performed in the same PVD tool.

[0119] Reference Figure 5CIn block 414 of method 306, a second RPC process is performed on the semiconductor structure 100 to clean the semiconductor structure 100, in particular, the barrier layer 1102 and the diffusion layer 1202. The second RPC process removes particles, residues and other contaminants, such as contaminants from those metal material layers. The second RPC process is similar to the first RPC process in operation 404. For example, the second RPC process is performed in a gas environment under plasma conditions. In the present embodiment, the second RPC process includes hydrogen and helium at room temperature. According to some examples, hydrogen accounts for 3% to 10% of the gas, and helium accounts for 97% to 90% of the gas. In some examples, the gas pressure is between 10mTorr and 30mTorr. The EF power for generating plasma is between 500W and 1500W. The duration of the second RPC treatment is between 30 seconds and 300 seconds. In the present embodiment, the RPC process is implemented in the same PVD tool.

[0120] Reference Figure 5C Box 416 and Fig.14 , method 306 includes an operation of depositing a metal layer 1302 on the diffusion layer 1202. The metal layer 1302 may include aluminum, copper, tungsten, other suitable metals, metal alloys, or combinations thereof. In the present embodiment, the metal layer 1302 includes an aluminum-copper (AlCu) alloy. In a further embodiment, the AlCu layer 1302 includes about 99.5% aluminum and about 0.5% copper. The AlCu layer 1302 is deposited by sputtering in a PVD tool at a high deposition temperature greater than 300°C, such as at a temperature between 300°C and 500°C. In some examples, the deposition temperature is between 350°C and 450°C. In the present embodiment, the AlCu layer 1302 thus formed has a polycrystalline structure. Specifically, the die size of the AlCu layer 1302 is substantially distributed between 5μm and 20μm. In some embodiments, in the die size distribution of the AlCu layer 1302, more than 50% of the polycrystalline die have a die size greater than 1 micron. In some embodiments, the thickness of the AlCu layer 1302 is to between.

[0121] In the prior art, the AlCu layer is deposited under low temperature conditions, such as at a deposition temperature below 300° C. Therefore, the deposited AlCu layer cannot properly fill gaps (such as RV vias), leaving a tooth-like profile. This further results in incomplete or incorrect filling of the second passivation layer 146, causing various performance and reliability issues. By implementing hot deposition in the disclosed method, the AlCu layer 1302 has improved gap filling on one side, but may cause metal extrusion from the other side. In particular, the tantalum in the barrier layer 1102 diffuses into the AlCu layer 1302 and causes TaN lattice vacancies, which further provide opportunities for the formation of copper extrusion from the copper of the top metal line 130. In addition, the aluminum in the AlCu layer 1302 is susceptible to aluminum extrusion due to thermal stress. By forming a diffusion layer 1202 between the AlCu layer 1302 and the barrier layer 1102 to separate the two, various metal extrusions can be effectively eliminated or significantly reduced. The disclosed method of forming the diffusion layer 1202 by thermal deposition and oxidation treatment of the AlCu layer 1302 improves the filling problem and the metal squeeze-out problem.

[0122] During operation 416 of depositing the AlCu layer 1302, due to the high temperature deposition, aluminum from the AlCu layer 1302 may diffuse into the diffusion layer 1202. In this case, the diffusion layer 1202 also includes aluminum. In some embodiments, the diffusion layer 1202 includes tantalum, oxygen, aluminum, and nitrogen.

[0123] In addition, all the above operations in method 306 are performed in various chambers of the cluster PVD. When the workpiece 100 is fed into the PVD tool through a load-lock, and is fed out after completing the above operations, the manufacturing cost is reduced and contamination between operations is avoided. For example, the PVD cluster tool includes one or more degassing chambers, one or more pre-cleaning chambers, one or more pass-through chambers, and multiple deposition chambers. In a further embodiment, a degassing operation is performed in the degassing chamber; an RPC operation is performed in the pre-cleaning chamber; a cooling operation can be performed in the pass-through chamber; various deposition operations (deposition of Ta, TaN, and AlCu) are performed in various deposition chambers; and an oxidation treatment is performed in the degassing chamber, the pre-cleaning chamber, or the deposition chamber.

[0124] exist Fig.152 further illustrates such a semiconductor structure 100 in cross-sectional view, which is constructed according to some embodiments and formed by method 200. In particular, an RDL structure 140 is formed by method 200. More specifically, an RDL metal feature 142 is generated based on the modified RDL structure 140 and formed by method 222. Method 220, method 258, and method 306 are part of method 200, but they detail multiple sub-operations.

[0125] The method 200 may additionally include other operations before, during, or after the above operations. The semiconductor structure may also include other components. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3D IC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods for intermediate verification of known good dies to increase yield and reduce costs.

[0126] The present disclosure provides a semiconductor structure 100 and a method 200 for manufacturing the same in various embodiments. The semiconductor structure 100 includes an RDL structure 140 having an RDL metal component 142 produced by the method 200 and formed by the method 222. In particular, the RDL structure 140 is modified to adjust the layout of the RDL structure by inserting dummy components and adjusting the RDL metal components. By implementing the disclosed method in various embodiments, some of the advantageous effects described below can be presented. However, it should be understood that different embodiments disclosed herein provide different advantageous effects, and all embodiments do not necessarily require specific advantageous effects. As an example, deformations such as warping of the semiconductor structure are reduced or eliminated.

[0127] In one exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes: receiving an integrated circuit layout including a semiconductor structure, wherein the integrated circuit layout includes a redistribution layout structure having a plurality of redistribution layout metal components; modifying the integrated circuit layout so that the modified redistribution layout structure meets a criterion related to an XY ratio gap; generating a tape-out according to the modified integrated circuit layout; and manufacturing the semiconductor structure according to the modified integrated circuit layout defined in the tape-out.

[0128] In some embodiments, a redistribution layout structure is formed in a passivation layer above a semiconductor substrate; a plurality of redistribution layout metal components include a plurality of first conductive components and a plurality of second conductive components, wherein the plurality of first conductive components are longitudinally oriented along a first direction X, and the plurality of second conductive components are longitudinally oriented along a second direction Y perpendicular to the first direction X; and the step of modifying the integrated circuit layout also includes: determining a criterion related to an XY ratio difference based on manufacturing data, wherein the XY ratio difference is defined as a difference between a first duty ratio of the plurality of first conductive components and a second duty ratio of the plurality of second conductive components, wherein the criterion for the XY ratio difference is a value less than 1; evaluating the redistribution layout structure based on the criterion; and adding a plurality of dummy components to the redistribution layout structure until an absolute value of the XY ratio difference is less than the value.

[0129] In some embodiments, the step of adding a plurality of dummy components to the redistribution layout structure includes: if the XY ratio difference is a positive value, adding a plurality of dummy components longitudinally oriented along the Y direction to the redistribution layout structure.

[0130] In some embodiments, the step of adding a plurality of dummy components to the redistribution layout structure includes: if the XY ratio difference is a negative value, adding a plurality of dummy components longitudinally oriented along the X direction to the redistribution layout structure.

[0131] In some embodiments, the standard is 30% determined from manufacturing data.

[0132] In some embodiments, the criterion is a first criterion, wherein the step of modifying the integrated circuit layout further comprises modifying the integrated circuit layout according to a second criterion, and wherein the second criterion is related to an average spacing of multiple redistribution layout metal features of the redistribution layout structure.

[0133] In some embodiments, the second criterion is related to an average spacing between a plurality of redistribution layout metal features of the redistribution layout structure, and wherein the step of evaluating the redistribution layout structure further comprises evaluating the redistribution layout structure according to the second criterion.

[0134] In some embodiments, the step of modifying the integrated circuit layout further includes modifying the redistribution layout structure so that the modified redistribution layout structure meets a second standard related to the average spacing.

[0135] In some embodiments, the step of modifying the integrated circuit layout includes adjusting the plurality of redistribution layout metal features to comply with a second criterion.

[0136] In some embodiments, adjusting the plurality of redistribution layout metal features includes resizing the plurality of redistribution layout metal features.

[0137] In some embodiments, the second standard is 3 μm; and the step of resizing the plurality of redistribution layout metal features includes increasing widths of the plurality of redistribution layout metal features.

[0138] In some embodiments, the step of manufacturing a semiconductor structure according to the modified integrated circuit layout defined in the offline process also includes: making multiple photoresist masks according to the modified integrated circuit layout defined in the offline process; and using multiple photoresist masks to manufacture the semiconductor structure, wherein at least one of the multiple photoresist masks defines a modified redistribution layout structure including multiple redistribution layout metal components and multiple dummy components.

[0139] In another exemplary embodiment, the present disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes: receiving an integrated circuit layout of a semiconductor structure, wherein the semiconductor structure includes a redistribution layout structure of a plurality of redistribution layout metal parts, wherein the plurality of redistribution layout metal parts are formed in a passivation layer on a semiconductor substrate, wherein the plurality of redistribution layout metal parts include a plurality of first conductive parts and a plurality of second conductive parts, the plurality of first conductive parts are longitudinally oriented along a first direction X, and the plurality of second conductive parts are longitudinally oriented along a second direction Y perpendicular to the first direction X; determining a standard according to manufacturing data, wherein the standard includes a first standard related to an XY ratio difference and a second standard related to an average spacing of the plurality of redistribution layout metal parts, wherein the XY ratio difference is defined as a difference between a first operating cycle of the plurality of first conductive parts and a second operating cycle of the plurality of second conductive parts; modifying the integrated circuit layout so that the modified redistribution layout structure meets the first standard and the second standard; and generating a tape-out according to the modified integrated circuit layout.

[0140] In some embodiments, the method for manufacturing a semiconductor structure also includes: making multiple photoresist masks according to the modified integrated circuit layout defined in the offline process; and using multiple photoresist masks to manufacture the semiconductor structure, wherein at least one of the multiple photoresist masks defines a modified redistribution layout structure, and the modified redistribution layout structure includes multiple redistribution layout metal components and multiple dummy components.

[0141] In some embodiments, the step of modifying the integrated circuit layout further includes adding a plurality of dummy components to the redistribution layout structure, and adjusting a plurality of redistribution layout metal components of the redistribution layout structure.

[0142] In some embodiments, the step of determining the standard includes determining a first standard related to an XY ratio difference, wherein the XY ratio difference is defined as a difference between a first operating period of a plurality of first conductive components and a second operating period of a plurality of second conductive components, wherein the first standard for the XY ratio difference is a numerical value less than 1; and the step of modifying the integrated circuit layout also includes adding a plurality of dummy components to the redistribution layout structure until an absolute value of the XY ratio difference is less than the numerical value.

[0143] In some embodiments, the step of adding a plurality of dummy components to the redistribution layout structure includes: if the XY ratio difference is a positive value, adding a plurality of dummy components longitudinally oriented along the Y direction to the redistribution layout structure.

[0144] In some embodiments, the step of adding a plurality of dummy components to the redistribution layout structure includes: if the XY ratio difference is a negative value, adding a plurality of dummy components longitudinally oriented along the X direction to the redistribution layout structure.

[0145] In another exemplary embodiment, the present disclosure provides a semiconductor structure. The semiconductor structure includes a plurality of semiconductor devices, an interconnect structure, and a redistribution layout structure. A plurality of semiconductor devices are formed on a semiconductor substrate. The interconnect structure is disposed on a plurality of semiconductor devices. The redistribution layout structure is disposed on a semiconductor substrate, wherein the redistribution layout structure includes a plurality of redistribution layout metal components embedded in a passivation layer, the plurality of redistribution layout metal components include a plurality of first conductive components and a plurality of second conductive components, the plurality of first conductive components are longitudinally oriented along a first direction X, and the plurality of second conductive components are longitudinally oriented along a second direction Y perpendicular to the first direction X; the XY ratio difference is defined as the difference between a first operating period of the plurality of first conductive components and a second operating period of the plurality of second conductive components, and the XY ratio difference is less than 1.

[0146] In some embodiments, an average pitch of the plurality of redistribution layout metal features is less than 3 μm; and the plurality of redistribution layout metal features include a plurality of dummy metal features, and each of the plurality of dummy metal features is isolated from other conductive features.

[0147] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of semiconductor devices are formed on a semiconductor substrate; an interconnect structure disposed on a plurality of the semiconductor devices; as well as A redistribution layout structure is disposed on the semiconductor substrate, wherein The redistribution layout structure includes a plurality of redistribution layout metal components buried in a passivation layer. The plurality of redistribution layout metal components include a plurality of first conductive components and a plurality of second conductive components, the plurality of first conductive components are longitudinally oriented along a first direction X, and the plurality of second conductive components are longitudinally oriented along a second direction Y perpendicular to the first direction X; An XY ratio difference is defined as a difference between a first duty cycle of the plurality of first conductive components and a second duty cycle of the plurality of second conductive components, and The XY ratio difference is less than 1.

2. The semiconductor structure according to claim 1, wherein: An average pitch of the plurality of redistribution layout metal features is less than 3 μm; and The plurality of redistribution layout metal components include a plurality of dummy metal components, and each of the plurality of dummy metal components is isolated from other conductive components.

3. The semiconductor structure according to claim 1, wherein: The XY ratio difference is less than 30%.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The passivation layer includes a first passivation layer and a second passivation layer, and a plurality of the redistribution layout metal components are located between the first passivation layer and the second passivation layer.

5. The semiconductor structure according to claim 4, characterized in that The first passivation layer includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, and a plurality of redistribution layout metal components directly contact a top metal line through a redistribution via penetrating the first dielectric material layer and the second dielectric material.

6. The semiconductor structure according to claim 5, characterized in that The size of the redistribution via is between 5 μm and 20 μm.

7. The semiconductor structure according to claim 5, characterized in that The first dielectric material layer is a silicon nitride layer having a thickness of to wherein the second dielectric material layer is an undoped quartz glass layer having a thickness of to between.

8. The semiconductor structure according to claim 4, wherein: The second passivation layer includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, and a plurality of redistribution layout metal components are exposed from an opening in the first dielectric material layer and the second dielectric material layer.

9. The semiconductor structure according to claim 8, characterized in that The size of the opening is between 10 μm and 30 μm.

10. The semiconductor structure according to claim 8, wherein: The first dielectric material layer is an undoped quartz glass layer with a thickness of to wherein the second dielectric material layer is a silicon nitride layer having a thickness of to between.

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