Integrated circuit structure

Abstract

An integrated circuit structure includes a semiconductor substrate; the interconnection structure is formed above the semiconductor substrate; a redistribution layer structure is formed over the interconnect structure, the redistribution layer structure including: a redistribution layer pad portion having a pad via array having via holes seated on a first top metal line of the interconnect structure; a redistribution layer signal routing portion having a signal routing via located on a second top metal line of the interconnect structure; and a redistribution layer top portion over the redistribution layer pad portion and the redistribution layer signal wiring portion. The via holes of the connecting pad via hole array comprise square via holes and adjacent sacrificial via holes, the square via holes have the width of the square via holes, the sacrificial via holes have the width of the sacrificial via holes, and the width of the square via holes is larger than the width of the sacrificial via holes.

Description

Technical Field

[0001] The embodiments of the utility model relate to an integrated circuit technology, and in particular to an integrated circuit structure. Background Art

[0002] The electronics industry has a growing demand for smaller and faster electronic devices that can simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power integrated circuits. To date, these goals have been largely achieved by reducing the size of integrated circuits (e.g., minimizing the size of integrated circuit components), thereby improving production efficiency and reducing associated costs. However, these miniaturizations have also increased the complexity of the integrated circuit manufacturing process. Therefore, to achieve continued progress in integrated circuit devices and their performance, similar progress in integrated circuit manufacturing processes and technologies is needed.

[0003] Many technological advances have occurred in the field of integrated circuit packaging, which may involve chip bonding and rerouting input / output signals to different locations on the integrated circuit chip. To this end, metal redistribution layers (RDLs) are often used to reroute connections from lower layers (such as interconnect and device areas) to the desired bonding locations to better contact the bonding pads when necessary. The redistribution layer can also be used to distribute contact points around the die to alleviate thermal stress during installation. However, when larger bulk metal redistribution layer pads are formed together with smaller and thinner vias (such as through a damascene process), metal filling problems may occur in the smaller vias. Metal filling problems may be caused by stress generated by the difference in thermal expansion coefficients of metal (such as copper) and surrounding dielectric materials. Specifically, the stress gradient in the bottom area of ​​the via changes, resulting in defects and vacancies in the via portion of the metal redistribution layer. In addition, larger bulk metals produce more vacancies, and the stress gradients can cause vacancy aggregation and void nucleation to balance the stress in the metal, thereby reducing the reliability of the component. Furthermore, the thermal expansion stress of the larger bulk metal portion can pull the via portion upward, causing it to break and disconnect the component.

[0004] Thus, while existing methods and structures relating to redistribution layer structures are generally adequate for their intended purposes, these methods and structures are not completely satisfactory in all respects. Utility Model Content

[0005] The purpose of the present invention is to provide an integrated circuit structure to solve at least one of the above problems.

[0006] In some embodiments, an integrated circuit structure is provided, which includes a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and a redistribution layer structure formed above the interconnect structure, wherein the redistribution layer structure includes: a redistribution layer pad portion, having a pad via array, the pad via array having multiple vias located on a first top metal line of the interconnect structure; a redistribution layer signal wiring portion, having a signal wiring via located on a second top metal line of the interconnect structure; and a redistribution layer top, located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connects the redistribution layer pad portion and the redistribution layer signal wiring portion together, wherein the multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width along a first direction, the sacrificial via having a sacrificial via width along the first direction, and the block via width is greater than the sacrificial via width, wherein the sacrificial via is closer to the block via than the signal wiring via.

[0007] According to one embodiment of the present invention, the redistribution layer pad portion and the redistribution layer signal wiring portion are connected together through a connecting portion on the top of the redistribution layer, and the connecting portion is located directly above an interlayer dielectric layer of the interconnect structure.

[0008] According to one embodiment of the present invention, a redistribution layer pad area is provided on the top of the redistribution layer directly above the first top metal line, and the redistribution layer pad area has a pad width along the first direction and the same pad width along a second direction perpendicular to the first direction, wherein the connection portion at the top of the redistribution layer has a redistribution layer connection area, and the redistribution layer connection area has a line length along the first direction and a line width along the second direction, wherein the pad width is greater than the line width.

[0009] According to one embodiment of the present invention, the sacrificial via is a first sacrificial via of a plurality of sacrificial vias, and a layer of the plurality of sacrificial vias on each side of the block via surrounds the block via, and each of the plurality of sacrificial vias is separated from each other by a passivation layer.

[0010] According to one embodiment of the present invention, the sacrificial via is a first sacrificial via of a plurality of sacrificial vias, wherein a layer of the plurality of sacrificial vias on a first side and a second side of the block via surrounds the block via, two layers of the plurality of sacrificial vias on a third side of the block via surround the block via, and no layer of the plurality of sacrificial vias on a fourth side of the block via surrounds the block via, wherein the two layers of the plurality of sacrificial vias are disposed between the block via and the signal wiring via, wherein each of the plurality of sacrificial vias is separated from each other by a passivation layer.

[0011] In some embodiments, an integrated circuit structure is provided, which includes a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and a redistribution layer structure formed above the interconnect structure, wherein the redistribution layer structure includes: a redistribution layer pad portion having a pad via array, the pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal wiring portion having a signal wiring via located on a second top metal line of the interconnect structure; and a redistribution layer top located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, wherein the plurality of vias of the pad via array include a plurality of peripheral vias arranged along an edge of the redistribution layer pad portion, wherein each of the plurality of peripheral vias is closer to another of the plurality of peripheral vias than to the signal wiring via.

[0012] According to one embodiment of the present invention, the plurality of peripheral vias have the same size.

[0013] According to one embodiment of the present invention, the plurality of via holes of the pad via array further include a plurality of central via holes surrounded by the plurality of peripheral via holes, and the plurality of central via holes have the same size as the plurality of peripheral via holes.

[0014] According to one embodiment of the present invention, the spacings between adjacent central vias, between adjacent peripheral vias, and between one of the peripheral vias and one of the central vias are the same.

[0015] In some other embodiments, an integrated circuit structure is provided, which includes a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and a redistribution layer structure formed above the interconnect structure, wherein the redistribution layer structure includes: a redistribution layer pad portion, having a pad via array, the pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal wiring portion, having a signal wiring via located on a second top metal line of the interconnect structure; and a redistribution layer top, located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, wherein the first top metal line has a first length along a first direction, the second top metal line has a second length along the first direction, and the first length is greater than the second length, wherein the first top metal line has a bottom surface that is not in contact with any metal component, and the second top metal line has a bottom surface that directly contacts a metal via of a semiconductor device that is wired to the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0017] Figure 1 A redistribution layer (RDL) structure with a via array is shown according to an embodiment of the present invention.

[0018] Figure 2 Another embodiment of the present invention is shown, which is a redistribution layer structure with a via array.

[0019] Figure 3A show Figure 1 The redistribution layer structure, Figure 3B Display edge Figure 3A A schematic cross-sectional view taken along line BB'.

[0020] Figure 4 The redistribution layer structure of the embodiment of the present invention is described in detail.

[0021] Figure 5 An integrated circuit (IC) structure with a redistribution layer structure according to an embodiment of the present invention is shown.

[0022] Figure 6FIG. 2 shows an integrated circuit (IC) structure with a redistribution layer structure according to another embodiment of the present invention.

[0023] Figure 7 , Figure 8 , Fig. 9 A redistribution layer structure with a via array according to another embodiment of the present invention is shown.

[0024] The reference numerals are as follows:

[0025] 100: Integrated Circuit Structure

[0026] 102: Base

[0027] 104: Isolation components

[0028] 106: Active area

[0029] 110: Transistor device

[0030] 120: Interconnection structure

[0031] 122: Interlayer dielectric layer

[0032] 124:Contact

[0033] 126: Metal wire

[0034] 128: Through hole

[0035] 130, 130a, 130b: top metal wire

[0036] 140: Rewiring layer structure

[0037] 140a: Bonding pad portion

[0038] 140b: Connecting part

[0039] 140c: Signal wiring part

[0040] 142: Bonding pad

[0041] 144: Passivation layer

[0042] 148: Sacrificial via

[0043] 149: Square via

[0044] 150: Signal wiring via

[0045] 151: Conductive barrier layer

[0046] 400: Stress gradient event

[0047] 412: Vacant

[0048] 414: Nucleation void

[0049] BP: Bottom

[0050] TP:Top

[0051] d1,d2,L1,L2,V1,V2,W1,W2: Dimensions

[0052] e1,e2: edge spacing DETAILED DESCRIPTION

[0053] It should be understood that the following disclosure provides many different embodiments or examples to implement different parts of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not used to limit the embodiments of the utility model. For example, the size of the component is not limited to the scope or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed in direct contact, and may also include an additional component that can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to limit the relationship between each embodiment and / or the appearance structure.

[0054] Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used to conveniently describe the relationship of one element or component to another (plural) element or component in the drawings. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used would be interpreted accordingly.

[0055] Furthermore, when "about," "approximately," etc. are used to describe a number or a range of numbers, such terms are intended to encompass numbers within a reasonable range including the described number, such as within + / -10% of the described number, or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" may encompass a size range from 4.5 nm to 5.5 nm. Furthermore, when the size or size of one component is compared to another component, the terms "approximately the same," "substantially the same," "similar size," etc. should be understood to be within + / -10% between the two compared components.

[0056] This article is about different embodiments of a redistribution layer (RDL) structure in an integrated circuit (IC). The redistribution layer structure has a bonding pad portion and a signal wiring portion connected together through the top of the redistribution layer structure. The bonding pad portion includes a via array having a plurality of vias, and the signal wiring portion includes a signal wiring via that is wired to the underlying signal line. The bonding pad portion is larger than the signal wiring portion. However, since the bonding pad portion (and the top portion above the bonding pad portion) includes a larger amount of bulk metal, there is a risk of defects and vacancies caused by the bulk metal pullback on the signal wiring via. As such, the utility model embodiment combines a via array in the bonding pad portion. The via array will attract vacancies in the bonding pad portion to aggregate and nucleate holes, thereby reducing or eliminating the pullback of the vias on the signal wiring vias in the signal wiring portion. In other words, the via array absorbs any voids and defects caused by stress instead of the signal wiring vias. This can prevent the signal wiring vias from being disconnected and causing an open circuit along the signal path.

[0057] Figure 1 A redistribution layer (RDL) structure 140 with a via array according to an embodiment of the present invention is shown. Figure 1The redistribution layer structure 140 is shown in a top view. As shown, the redistribution layer structure 140 includes a bonding pad portion 140a having an area defined by dimensions L1 and W1. The bonding pad portion 140a may be rectangular, wherein the dimension L1 is different from the dimension W1. Alternatively, as shown, the bonding pad portion 140a may be square, wherein the dimension L1 is equal to the dimension W1. In other words, the width or length of the bonding pad portion 140a along the x-direction is equal to the width or length of the bonding pad portion 140a along the y-direction. In one embodiment, the dimensions L1 and W1 are in the range of 30-50μm. In one embodiment, the dimensions L1 and W1 are both approximately 50μm. The bonding pad portion 140a includes a via array having a block via 149 and a plurality of sacrificial vias 148 surrounding the block via 149. The block via 149 has a dimension V1 along the x-direction and the y-direction, and each sacrificial via 148 has a dimension V2 along the x-direction and the y-direction. Dimension V1 is greater than dimension V2. In one embodiment, the ratio of V1 to V2 is greater than 12. In one embodiment, dimension V1 is approximately 40 μm, and dimension V2 is approximately 2.7 μm. In one embodiment, dimension V2 is in the range of 1-3 μm. It should be noted that the block via 149 cannot be too large, where dimension V1 is close to dimension L1 or W1. If the block via 149 is too large, there is not enough space for the sacrificial via 148 to achieve the desired stress relief effect, and the block via 149 will generate excessive pull-back force on the signal wiring via 150. Therefore, the ratio of L1 to V1 and / or W1 to V1 should be greater than 1.1. In one embodiment, the ratio of L1 to V1 is approximately 1.25. Please refer to Figure 1 The bonding pad portion 140a includes a spacing of dimension d1 between each adjacent sacrificial via 148 and between the block via 149 and the sacrificial via 148. In one embodiment, dimension d1 is in the range of 1.6-2 μm. In one embodiment, dimension d1 is 1.8 μm. Please refer to Figure 1 The bonding pad portion 140a includes an edge spacing e1 between an outer edge of the bonding pad portion 140a and an outer edge of the sacrificial via 148. In one embodiment, the edge spacing e1 is in a range between 0.25 and 0.65 μm. In one embodiment, the edge spacing e1 is about 0.65 μm. Figure 1 As shown, the dimension L1 or W1 = 2(e1+V2+d1)+V1. In one embodiment, the dimension L1 or W1 =

[0058] 2(0.65+2.7+1.8)+39.7=50μm.

[0059] Please refer to Figure 1, the redistribution layer structure 140 also includes a signal wiring portion 140c defined by dimensions L2 and W2. The signal wiring portion 140c includes a signal wiring via 150 that is spaced apart from edge portions of the signal wiring portion 140c (i.e., edge spacings e1 and e2). In one embodiment, the signal wiring via 150 has the same dimensions as the sacrificial via 148 (e.g., has a dimension V2). In other embodiments, the signal wiring via 150 has a dimension that is larger than the dimension V2. In any case, the signal wiring via 150 may have dimensions similar to the sacrificial via 148, but as will be explained in more detail below, the signal wiring via 150 routes the signal line and has a different function than the sacrificial via 148. Dimension L2 is along the x-direction and includes the dimensions of the signal wiring via 150 and the edge spacing e1. Dimension W2 is along the y-direction and includes the dimensions of the signal wiring via 150 and the edge spacing e2. The signal wiring via 150 is spaced apart from the edge portion of the signal wiring portion 140c in the y direction by an edge spacing e2, and is spaced apart from the edge portion of the signal wiring portion 140c in the x direction by an edge spacing e1 (as described above). In one embodiment, dimension W2 is in the range of 1.5-4 μm. In one embodiment, dimension W2 is about 3.6 μm. In one embodiment, edge spacing e2 is greater than edge spacing e1. This is because dimension W2 defines edge spacing e2, and dimension W2 is greater than dimension V2 by a certain amount, so that edge spacing e2 is greater than edge spacing e1. For example, e1=0.65 (as described above), e2=0.9, and V2=2.7, and where W2=2*e2+V2, so W2=2*0.9+2.7=3.6 μm.

[0060] Please refer to Figure 1, the redistribution layer structure 140 also includes a connection portion 140b, which has an area defined by dimensions d2 and W2. The connection portion 140b connects the signal wiring via 150 to the sacrificial via 148 and the block via 149. Dimension W2 (as described above) is also the width of the connection portion 140b along the y direction, and dimension d2 is the length of the connection portion 140b along the x direction between the bonding pad portion 140a and the signal wiring portion 140c. Dimension W2 can also be referred to as the redistribution layer structure line width. With reference to dimension W1 as the redistribution layer pad width (i.e., the width of the bonding pad portion 140a), the redistribution layer pad width is greater than the redistribution layer line width. In other words, dimension W1 is greater than dimension W2. In one embodiment, dimension W1 is at least 7 times greater than dimension W2. In one embodiment, the ratio of W1 to W2 is in the range between 7 and 35. Dimension W1 should be larger than dimension W2 because the pad portion 140a of the redistribution layer structure 140 is used as an external metal block to redistribute the signal to the external pad. Due to the significant difference between dimensions W1 and W2 (in some embodiments, the block via itself has a dimension V1 that is larger than dimension W2), a sacrificial via 148 as described above is required to relieve stress and reduce the metal pullback effect on the signal routing via 150. In one embodiment, V1 / W2 is in the range between 2 and 6. Please refer to Figure 1 , dimension d2 may also be referred to as the redistribution layer line width. In one embodiment, dimension d2 (redistribution layer line width) is greater than 3 times dimension V2 (sacrificial or signal wiring via width). In one embodiment, dimension d2 is approximately 10 μm. Since dimension d2 is the length of the line connected by the redistribution vias in different parts of the redistribution layer structure 140, dimension d2 should also be greater than dimension d1 (the spacing between the vias in the bonding pad portion 140a). In one embodiment, the ratio of d2 to d1 is greater than 5.

[0061] Please refer to Figure 1 , there may be M1 and M2 rows of sacrificial vias 148 arranged on both sides of the block via 149 along the y direction. There may be N1 and N2 rows of sacrificial vias 148 on both sides of the block via 149 along the x direction. In the embodiment shown, M1, M2, N1 and N2 are all equal to 1. In other words, a layer of sacrificial vias 148 surrounds all four sides of the block via 149. Since there is only one layer of sacrificial vias 148, the sacrificial vias 148 in this layer may also be referred to as peripheral vias. In other embodiments, M1, M2, N1 and N2 are all equal to 2 or greater. In this case, additional layers of sacrificial vias 148 surround all four sides of the block via 149. Depending on design considerations, these additional layers may produce additional stress relief effects.

[0062] Figure 2Another embodiment of the present invention is shown, which is a redistribution layer structure 140 having a via array. Figure 2 The redistribution layer structure 140 in Figure 1 The redistribution layer structure 140 shown in FIG. 1 is similar to the redistribution layer structure 140 shown in FIG. 1 , and similar aspects may apply thereto. The difference is that the bonding pad portion 140a may be circular (as shown), with a circular square via 149 and a plurality of circular sacrificial vias 148. Furthermore, the signal wiring via 150 may also be circular. The spacing between the vias in the bonding pad portion 140a is dimension d1, as described above with reference to FIG. Figure 1 The block via 149 may have a size V1, as described above with reference to Figure 1 Furthermore, the sacrificial via 148 and the signal wiring via 150 may have a size V2, as shown in the above reference Figure 1 For the sake of brevity, I will not go into details. Figure 1 Similar other parts.

[0063] Please refer to Figure 2 , there may be L layers of sacrificial vias 148 surrounding the perimeter of the circular block via 149. In the embodiment shown, L is equal to 1. In other words, one layer of sacrificial vias 148 surrounds the block via 149. Since there is only one layer of sacrificial vias 148, this layer of sacrificial vias 148 may also be referred to as perimeter vias. In other embodiments, L is equal to 2 or greater. In this case, additional layers of sacrificial vias 148 surround the block via 149. Depending on design considerations, these additional layers may provide additional stress relief.

[0064] Figure 3A show Figure 1 The redistribution layer structure 140, and Figure 3B Display edge Figure 3A A schematic cross-sectional view taken along line BB'. Figure 1 The same reference symbols used in Figure 3B. In this view, the top TP and bottom BP of the redistribution layer structure 140 are shown. The top TP extends laterally along the x-direction across the bonding pad portion 140a, the connection portion 140b, and the signal wiring portion 140c. Below the top TP is the bottom BP. The bottom BP includes all vias (i.e., sacrificial vias 148, block vias 149, and signal wiring vias 150) as part of the redistribution layer structure 140. It should be noted that the connection portion 140b does not have a bottom BP, and there are no vias in this portion of the redistribution layer structure 140. The vias of the redistribution layer structure 140 are spaced apart from each other by the passivation layer 144. In other words, different portions of the passivation layer 144 fill the edge spacing e1, dimensions d1, and d2. Each via passes through the passivation layer 144 to be located on the underlying structure (e.g., the top metal line 130). In the embodiment shown, the block via 149 and the sacrificial via 148 are located on the top metal line 130a, and the signal routing via 150 is located on the top metal line 130b. The top metal line 130a and the top metal line 130b may be separated by an interlayer dielectric (ILD) layer 122.

[0065] Please refer to Figure 3B , the bonding pad portion 140a is directly above the top metal line 130a, the connecting portion 140b is directly above the interlayer dielectric layer 122, and the signal wiring portion 140c is directly above the top metal line 130b. The top metal lines 130a and 130b may include copper or other suitable metal materials, such as tungsten or cobalt. The interlayer dielectric layer 122 may include silicon oxide, a silicon oxide-containing material, or a low-k dielectric layer, such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG) and / or other suitable low-k dielectric materials. The redistribution layer structure 140 and all its parts may include copper to form copper pads, copper vias and copper lines. The passivation layer 144 may include silicon oxide, silicon nitride or a suitable dielectric material.

[0066] Please refer to Figure 3B, the redistribution layer structure 140 can be lined with a conductive barrier layer 151 on the bottom surface and side surface of each of the sacrificial vias 148, the block vias 149 and the signal wiring vias 150. The conductive barrier layer 151 can also serve as a liner for the bottom surface of the top TP of the redistribution layer structure 140. The conductive barrier layer 151 includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or a combination of the foregoing. The redistribution layer structure 140 with the conductive barrier layer 151 can be formed by a damascene process (e.g., a dual damascene manufacturing process). For example, the passivation layer 144 can be deposited by a suitable deposition technique, such as chemical vapor deposition, high density plasma chemical vapor deposition (HDPCVD), other suitable techniques or a combination of the foregoing. Then, the passivation layer 144 is patterned in multiple steps to form a through-hole trench (in the bottom BP) and a redistribution layer trench (in the top TP). Next, the conductive barrier layer 151 is conformally deposited in the trenches by any suitable deposition technique. Finally, a metal fill deposition is performed to simultaneously fill the via trenches and the redistribution layer trenches, thereby forming the redistribution layer structure 140. The metal filler may be copper, and after the metal filler, a planarization process such as chemical mechanical polishing (CMP) may be performed. In this way, the redistribution layer structure 140 has a consistent metal filler between the bottom BP (conductive hole) and the top TP (metal pad and conductor).

[0067] The above-mentioned bonding pad portion 140a and signal wiring portion 140c include top TP and bottom BP. Without departing from the scope of the utility model embodiment, other ways of describing the redistribution layer structure are also possible. For example, the bonding pad portion 140a can represent only the top TP of the bonding pad portion 140a, and the signal wiring portion 140c can represent only the top TP of the signal wiring portion 140c. In this case, the via in the bottom BP can be referred to as the bonding pad via or the signal wiring via below the bonding pad portion 140a and the signal wiring portion 140c, respectively. For another example, the bonding pad portion 140a can represent only the bottom BP of the bonding pad portion 140a, and the signal wiring portion 140c can represent only the bottom BP of the signal wiring portion 140c. In this case, the top TP can be referred to as the redistribution layer connection portion that connects the bonding pad portion 140a to the signal wiring portion 140c.

[0068] Please refer to FIG. 3A to FIG. 3B, the top metal line 130a may have a larger size in the x and y directions than the top metal line 130b. This is because the bonding pad portion 140a of the redistribution layer structure 140 is larger than the signal wiring portion 140c of the redistribution layer structure 140. Furthermore, in order to accommodate the size difference, the size of the corresponding top metal line 130 is adjusted according to the via bonding area.

[0069] Figure 4 A redistribution layer structure 140 is shown that details the stress release mechanism of an embodiment of the present invention. As shown, after the redistribution layer structure 140 is formed, there may be vacancies 412 (or air gaps) in the metal filling material (e.g., copper) and particularly in the block portions (top TP and block vias 149) of the redistribution layer structure 140. It has been found that over time, due to the exacerbation of electrical or thermal stress, the vacancies 412 will migrate and nucleate from the high stress area (bulky portion) to the low stress area (thinner portion, such as the thin signal wiring via 150). Specifically, the vacancies 412 are affected by the stress gradient, which moves the vacancies from the larger volume top TP to the smaller volume bottom BP, resulting in the accumulation of vacancies at the bottom corners of the thinner vias (e.g., signal wiring vias 150). Furthermore, the pulling force from the larger block vias (e.g., block vias 149) may also pull and cause vacancies or defects in the thinner vias (e.g., signal wiring vias 150). These issues may result in fractures, which in turn may result in an open circuit between the signal wiring via 150 and the top metal line 130b. Because, in order to address these issues, the sacrificial via 148 is used to mitigate defects and voids that would otherwise reach the signal wiring via 150. Incorporating the sacrificial via 148 means that the block via 149 needs to be smaller, leaving space given the above-mentioned dimensions L1 or W1 to form the sacrificial via 148. Having a smaller block via 149 results in less pull and stress effects on the signal wiring via 150, which is desirable. This is because by reducing the metal volume of the block via 149, the source of vacancies and pull stress is also reduced, thereby improving the via bottom delamination problem.

[0070] Please refer to Figure 4, a stress gradient event 400 occurs, which causes the movement and migration of the vacancy 412. The stress gradient event 400 can be caused by applying a voltage or current, applying heat or heat treatment, or even just the passage of time. As shown, due to the sacrificial via 148, the vacancy migration and pull-back effect in the signal wiring via 150 is reduced or eliminated. To this end, the sacrificial via 148 provides a path for releasing stress, and the vacancy migration and pull-back instead occur on the sacrificial via 148. This is possible because the sacrificial via 148 is closer to the block via 149 than the signal wiring via 150. In this way, the sacrificial via 148 will attract the vacancy and pull it back before the vacancy travels to the signal wiring via 150. In other words, the stress defect problem is solved in the bonding pad portion 140a before the stress defect problem becomes a problem in the signal wiring portion 140c. Additionally or independently, due to the stress-mitigating sacrificial via scheme, any remaining vacancies in the signal wiring portion 140c can be nucleated without excessive stress affecting the bottom of the signal wiring via 150. That is, after sufficient vacancies are accumulated in the sacrificial via 148, the stress is balanced so that no excessive stress affects the signal wiring via 150, thereby avoiding or minimizing pullback fractures and voids.

[0071] Please refer to Figure 4 , after the stress gradient event 400, the vacancies 412 will result in nucleation voids 414 in the sacrificial vias 148. In one embodiment, the nucleation voids 414 are only in the sacrificial vias 148 and not in the signal wiring vias 150. If there are any nucleation voids 414 in the signal wiring vias 150, these nucleation voids are insignificant and will not result in pull-back fracture. In one embodiment, there are more nucleation voids 414 in the sacrificial vias 148 than in the signal wiring vias 150.

[0072] Figure 5 An integrated circuit (IC) structure 100 having a redistribution layer structure 140 is shown according to an embodiment of the present invention. The integrated circuit structure 100 includes a substrate 102 (sometimes also referred to as a semiconductor substrate), the substrate 102 having an active region 106 for forming a transistor device 110, such as a logic device, a memory device, or other type of device. The active region 106 includes a channel region and a source / drain region. In one embodiment, the active region 106 may be an active region protruding from the substrate 102. The substrate 102 includes a bulk silicon substrate. Alternatively, the substrate 102 may include an elemental semiconductor (such as silicon or germanium in a crystal structure), a compound semiconductor (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), or a combination of the foregoing. Possibly, the substrate 102 also includes a silicon overlying insulating layer.

[0073] The silicon-on-insulator (SOI) substrate may be fabricated by using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0074] The substrate 102 also includes various isolation features, such as isolation features 104 formed on or in the substrate 102 and defining various active regions 106 on the substrate 102. The isolation features 104 use isolation technology (e.g., shallow trench isolation (STI)) to define and electrically isolate the various active regions 106. The isolation features 104 include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination of the foregoing. The isolation features 104 are formed by any suitable process. For example, the formation of the shallow trench isolation features includes a photolithography process to expose a portion of the substrate, etching a trench in the exposed portion of the substrate (e.g., by using dry etching and / or wet etching), filling the trench with one or more dielectric materials (e.g., using a chemical vapor deposition process), and planarizing the substrate and removing excess portions of the dielectric material by a polishing process (e.g., a chemical mechanical polishing (CMP) process). In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer and a filling layer of silicon nitride or silicon oxide.

[0075] The active region 106 is a region of the semiconductor surface where various doped features are formed and configured into one or more devices, such as diodes, transistors, and / or other suitable devices. The active region may include a semiconductor material similar to the bulk semiconductor material of the substrate 102 (e.g., silicon) or a different semiconductor material (e.g., silicon germanium (SiGe), silicon carbide (SiC), or multiple semiconductor material layers (e.g., alternating silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth for performance enhancement, such as strain effects to increase carrier mobility.

[0076] The integrated circuit structure 100 also includes an interconnect structure 120 formed on the substrate 102. The interconnect structure 120 includes various conductive components to couple the various transistor devices 110 into the integrated circuit. The interconnect structure 120 also includes an interlayer dielectric (ILD) layer 122 to separate and isolate the various conductive components. For example, the interconnect structure 120 includes contacts 124, metal lines 126, and vias 128. The metal lines 126 are distributed in multiple metal layers. Figure 5, four metal layers are shown. The top metal line 130 is individually labeled. The contact 124 provides vertical electrical routing from the substrate 102 to the metal line. The via 128 provides vertical electrical routing between adjacent metal layers. Various conductive components are formed by one or more conductive materials, such as metals, metal alloys, or silicides. For example, the metal line 126 may include copper, aluminum-copper alloys, other suitable conductive materials, or a combination of the foregoing. The via 128 may include copper, aluminum-copper alloys, other suitable conductive materials, or a combination of the foregoing. The contact 124 may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or a combination of the foregoing. In some examples, the various conductive components may also include barrier layers, such as tantalum and tantalum nitride, titanium and titanium nitride. In the present embodiment, the top metal line 130 includes copper or other suitable metal materials, such as tungsten or cobalt.

[0077] As mentioned above Figure 3B The interlayer dielectric layer 122 may include silicon oxide, a silicon oxide-containing material or a low-k dielectric layer, such as tetraethoxysilane oxide, undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG) and / or other suitable low-k dielectric materials. The interlayer dielectric layer 122 provides isolation functions for various device components (such as gates) and various conductive components (such as metal lines, contacts and vias). The formation of the interlayer dielectric layer 122 includes, for example, deposition and chemical mechanical polishing. Deposition may include spin coating, chemical vapor deposition, other suitable deposition techniques or a combination of the foregoing. The interlayer dielectric layer 122 may include multiple layers, and various conductive components are formed together by a suitable process (such as a damascene process).

[0078] In some embodiments, the interconnect structure 120 or a portion of the interconnect structure 120 is formed by deposition and patterning. For example, a metal (or metal alloy) (e.g., copper or aluminum copper) is deposited by physical vapor deposition (PVD) and then patterned by photolithography and etching. Then, the interlayer dielectric layer 122 is disposed by deposition (and chemical mechanical polishing). In some embodiments, the interconnect structure 120 uses a damascene process to form metal lines 126, vias 128, and contacts 124.

[0079] Please refer to Figure 5 , the integrated circuit structure 100 includes a redistribution layer structure 140 above the interconnect structure 120 . Figure 5The redistribution layer structure 140 corresponds to the redistribution layer structure 140 in Figures 1 and 3B. As such, similar components are not described in detail for the sake of brevity. In the embodiment shown, the bonding pad portion 140a of the redistribution layer structure 140 is located on the top metal line 130a, and the signal wiring portion 140c of the redistribution layer structure 140 is located on the top metal line 130b. The top metal line 130a is used as an etch stop layer for the landing of the bonding pad portion 140a. It is advantageous to have the top metal line 130a for horizontal landing and more ideally forming the block vias 149 and the sacrificial vias 148. However, the top metal line 130a is not connected to any other conductive components in addition. In other words, the top metal line 130a is not wired to anywhere outside the redistribution layer structure 140. As such, the bottom surface of the top metal line 130a is not wired to any vias 128 of the underlying metal line 126. On the other hand, the top metal line 130b is a signal wiring top metal. The top metal line 130b is connected to the via 128 and the metal line 126, and is routed to the transistor device 110 below. Since the top metal line 130b routes the actual signal line, the interface between the redistribution layer structure 140 (e.g., the signal routing portion 140c) and the top metal line 130b should not have any of the above-mentioned undesirable pullbacks and gaps. On the other hand, since the top metal line 130a is only used as an etch stop and does not route any signal, it is possible to have a gap and pullback in the interface between the redistribution layer structure 140 (e.g., the bonding pad portion 140a) and the top metal line 130a. This gap relieves the stress from the signal routing via 150 without affecting the connection between the bonding pad portion 140a and the signal routing portion 140c.

[0080] Please refer to Figure 5 , the redistribution layer structure 140 is buried in the passivation layer 144. The bonding pad 142 may be formed in an opening of the passivation layer 144, wherein the opening is formed directly above the bonding pad portion 140a of the redistribution layer structure 140. Figure 3B Passivation layer 144 is described and may be multiple layers (not shown) depending on design considerations. Bond pad 142 may have a similar composition to redistribution layer structure 140. Bond pad 142 serves as a contact of integrated circuit structure 100 (e.g., for bonding to other integrated circuit structures or for integrated circuit testing (e.g., probe testing).

[0081] Figure 6 An integrated circuit (IC) structure 100 having a redistribution layer structure 140 according to another embodiment of the present invention is shown. Figure 6 The integrated circuit structure 100 is similar to Figure 5 The integrated circuit structure 100 is shown in FIG. 1 . For the sake of brevity, similar components are not described in detail. Figure 6In the embodiment, the top metal line 130a is not present in the interconnect structure 120. As described above, the top metal line 130a is used as an etch stop layer and does not route any real signal from the transistor device 110. As such, in some embodiments, the top metal line 130a may be removed. However, as shown, the removal of the top metal line 130a may result in uneven over-etching when forming the block vias 149 and the sacrificial vias 148. In these cases, the block vias 149 and the sacrificial vias 148 may penetrate a portion of the interlayer dielectric layer 122. In other aspects, the stress release mechanism of the embodiments of the present invention is still applicable.

[0082] Figure 7 A redistribution layer structure 140 having a via array according to another embodiment of the present invention is shown. Figure 7 Similar to FIG. 1 , and for the sake of brevity, similar components are not repeated. The difference lies in the location of the block via 149. The block via 149 is moved away from the signal wiring via 150 to make room for another column of sacrificial vias 148. In this case, due to space limitations, none of the columns of sacrificial vias 148 are on the other side of the block via 149. As shown, in this configuration, M1=2 and M2=0. Since there are two columns in the M1 column, there is an additional buffer layer between the block via 149 and the signal wiring via 150. This is an additional layer that captures the vacancy 412 before it travels and nucleates in the signal wiring via 150. Although the total amount of sacrificial vias 148 plus block vias 149 is the same as Figure 1 but in some cases, Figure 1 Compared with when M1=1 and M2=1, having an additional intermediate buffer layer so that M1=2 and M2=0 allows for more targeted stress relief.

[0083] Figure 8 A redistribution layer structure 140 having a via array according to another embodiment of the present invention is shown. Figure 8 Similar to FIG. 1 , and for the sake of brevity, similar components are not described in detail. The difference is that the block via 149 is removed. In this case, the bonding pad portion 140a (or the bottom BP of the bonding pad portion 140a) only includes the sacrificial via 148. In this way, the bulk metal stress effect only comes from the top TP of the bonding pad portion 140a, and the volume of the top TP of the bonding pad portion 140a is larger than the top TP of the connecting portion 140b and the top TP of the signal wiring portion 140c. Therefore, the top TP of the bonding pad portion 140a can still have an adverse effect on the signal wiring via 150 through the gap and pull-back effect. In this way, the sacrificial via 148 (or the peripheral via) can still be used to implement the stress release mechanism of the embodiment of the utility model.

[0084] Fig. 9 A redistribution layer structure 140 having a via array according to another embodiment of the present invention is shown. Fig. 9 Similar to FIG. 1 , similar parts are not described for simplicity. The difference is that the additional sacrificial vias 148 replace the square vias 149. In this way, the peripheral sacrificial vias 148 surround the central sacrificial via 148. In this case, similar to FIG. Figure 8 , the bonding pad portion 140a (or the bottom BP of the bonding pad portion 140a) only includes the sacrificial via hole 148. In this way, similar to Figure 8 , the bulk metal stress effect only comes from the top TP of the bonding pad portion 140a, and the volume of the top TP of the bonding pad portion 140a is larger than the top TP of the connection portion 140b and the top TP of the signal wiring portion 140c. Therefore, the top TP of the bonding pad portion 140a can still have an adverse effect on the signal wiring via 150 through the gap and pull-back effect. Figure 8 , the sacrificial via 148 can still be used to implement the stress release mechanism of the embodiment of the present invention, but the additional sacrificial via 148 here is used for additional stress release for different design applications.

[0085] Although not limiting, embodiments of the present invention provide many advantages for integrated circuit semiconductor structures having redistribution layer (RDL) structures. One example advantage is the introduction of sacrificial vias adjacent to block vias, thereby alleviating stress and pullback effects that would otherwise affect the signal routing vias. Another example advantage is the relocation or even removal of block vias to further improve the connection of the signal routing vias to the integrated circuit device. Another example advantage is the introduction of a top metal line as a landing etch stop layer for the pad portion of the redistribution layer structure.

[0086] One aspect of an embodiment of the utility model is an integrated circuit (IC) structure. The integrated circuit structure includes a semiconductor substrate; an interconnect structure formed on the semiconductor substrate; and a redistribution layer (RDL) structure formed on the interconnect structure, wherein the redistribution layer structure includes: a redistribution layer pad portion having a pad via array, the pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal wiring portion having a signal wiring via located on a second top metal line of the interconnect structure; and a redistribution layer top portion located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top portion connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, wherein the plurality of vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width along a first direction, the sacrificial via having a sacrificial via width along the first direction, and the block via width is greater than the sacrificial via width, wherein the sacrificial via is closer to the block via than the signal wiring via.

[0087] In one embodiment, the ratio of the block via width to the sacrificial via width is greater than 10.

[0088] In one embodiment, the redistribution layer pad portion and the redistribution layer signal wiring portion are connected together through a connection portion at the top of the redistribution layer, and the connection portion is located directly above the interlayer dielectric (ILD) layer of the interconnect structure. In another embodiment, the connection portion at the top of the redistribution layer has a line length along the first direction, and the line length is greater than 3 times the width of the sacrificial via. In another embodiment, the line length is greater than the via pitch between the block via and the sacrificial via. In another embodiment, the ratio of the line length to the via pitch is greater than 5.

[0089] In one embodiment, the top of the redistribution layer directly above the first top metal line has a redistribution layer pad area, the redistribution layer pad area has a pad width along a first direction and the same pad width along a second direction perpendicular to the first direction, and the connection portion of the top of the redistribution layer has a redistribution layer connection area, the redistribution layer connection area has a line length along the first direction and a line width along the second direction, and the pad width is greater than the line width. In another embodiment, the ratio of the pad width to the line width is in a range between 7 and 35.

[0090] In one embodiment, the sacrificial via is a first sacrificial via of a plurality of sacrificial vias, and a layer of the plurality of sacrificial vias on each side of the block via surrounds the block via, each of the plurality of sacrificial vias being separated from each other by a passivation layer.

[0091] In one embodiment, the sacrificial via is a first sacrificial via of the plurality of sacrificial vias, one layer of the plurality of sacrificial vias on the first side and the second side of the block via surrounds the block via, two layers of the plurality of sacrificial vias on the third side of the block via surround the block via, and no layer of the plurality of sacrificial vias on the fourth side of the block via surrounds the block via. The two layers of the plurality of sacrificial vias are disposed between the block via and the signal wiring via, wherein each of the plurality of sacrificial vias is separated from each other by a passivation layer.

[0092] Another aspect of the present invention is an integrated circuit (IC) structure. The integrated circuit structure includes a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and a redistribution layer (RDL) structure formed above the interconnect structure, wherein the redistribution layer structure includes: a redistribution layer pad portion having a pad via array, the pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal wiring portion having a signal wiring via located on a second top metal line of the interconnect structure; and a redistribution layer top located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, wherein the plurality of vias of the pad via array include a plurality of peripheral vias disposed along an edge of the redistribution layer pad portion, wherein each of the plurality of peripheral vias is closer to another of the plurality of peripheral vias than to the signal wiring via.

[0093] In one embodiment, the redistribution layer pad portion and the redistribution layer signal wiring portion are connected together through a connection portion at the top of the redistribution layer, and the connection portion is located directly above the interlayer dielectric layer of the interconnect structure. In another embodiment, the top of the redistribution layer directly above the first top metal line has a redistribution layer pad area, the redistribution layer pad area has a pad width along a first direction and the same pad width along a second direction perpendicular to the first direction. The connection portion at the top of the redistribution layer has a redistribution layer connection area, the redistribution layer connection area has a line length along the first direction and a line width along the second direction, wherein the pad width is at least 7 times greater than the line width.

[0094] In one embodiment, the plurality of peripheral vias have substantially the same size. In another embodiment, the plurality of vias of the pad via array further include a plurality of central vias surrounded by the plurality of peripheral vias, the plurality of central vias having substantially the same size as the plurality of peripheral vias. In another embodiment, the spacing between adjacent plurality of central vias, between adjacent plurality of peripheral vias, and between one of the plurality of peripheral vias and one of the adjacent plurality of central vias are substantially the same.

[0095] Another aspect of the present invention is an integrated circuit (IC) structure. The integrated circuit structure includes a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and a redistribution layer (RDL) structure formed above the interconnect structure, wherein the redistribution layer structure includes: a redistribution layer pad portion having a pad via array, the pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal wiring portion having a signal wiring via located on a second top metal line of the interconnect structure; and a redistribution layer top portion located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top portion connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together. The integrated circuit also includes a first top metal line having a first length along a first direction, a second top metal line having a second length along the first direction, and the first length is greater than the second length, wherein the first top metal line has a bottom surface that is not in contact with any metal component, and the second top metal line has a bottom surface that directly contacts a metal via of a semiconductor device that is wired to the semiconductor substrate.

[0096] In one embodiment, the integrated circuit structure further includes a bonding pad located directly above the redistribution layer pad portion of the redistribution layer structure.

[0097] In one embodiment, the integrated circuit structure further comprises a passivation layer surrounding the redistribution layer structure, wherein the redistribution layer structure comprises copper and the passivation layer comprises a dielectric material. In another embodiment, the integrated circuit structure further comprises a conductive barrier layer lining the bottom surface and the side surface of each of the plurality of vias in the pad via array and the signal wiring via, wherein the conductive barrier layer comprises tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0098] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the utility model from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the utility model, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the embodiments of the utility model. Various changes, substitutions or modifications can be made to the embodiments of the utility model without departing from the spirit and scope of the embodiments of the utility model.

Claims

1. An integrated circuit structure, characterized in that: include: a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and A redistribution layer structure is formed above the interconnect structure, wherein the redistribution layer structure comprises: a redistribution layer pad portion having a pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal routing portion having a signal routing via located on a second top metal line of the interconnect structure; and a redistribution layer top, located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, The plurality of vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width along a first direction, the sacrificial via having a sacrificial via width along the first direction, and the block via width is greater than the sacrificial via width, wherein the sacrificial via is closer to the block via than the signal wiring via.

2. The integrated circuit structure according to claim 1, wherein: The redistribution layer pad portion and the redistribution layer signal wiring portion are connected together through a connecting portion on the top of the redistribution layer, and the connecting portion is located directly above an interlayer dielectric layer of the interconnection structure.

3. The integrated circuit structure according to claim 2, wherein: A redistribution layer pad area is provided at the top of the redistribution layer directly above the first top metal line, the redistribution layer pad area having a pad width along the first direction and the same pad width along a second direction perpendicular to the first direction, wherein the connection portion at the top of the redistribution layer has a redistribution layer connection area, the redistribution layer connection area having a line length along the first direction and a line width along the second direction, wherein the pad width is greater than the line width.

4. The integrated circuit structure according to any one of claims 1 to 3, characterized in that: The sacrificial via is a first sacrificial via of a plurality of sacrificial vias, and a layer of the plurality of sacrificial vias on each side of the block via surrounds the block via, and wherein each of the plurality of sacrificial vias is separated from each other by a passivation layer.

5. The integrated circuit structure according to any one of claims 1 to 3, characterized in that: The sacrificial via is a first sacrificial via of a plurality of sacrificial vias, wherein one layer of the plurality of sacrificial vias on a first side and a second side of the block via surrounds the block via, two layers of the plurality of sacrificial vias on a third side of the block via surround the block via, and no layer of the plurality of sacrificial vias on a fourth side of the block via surrounds the block via, wherein the two layers of the plurality of sacrificial vias are disposed between the block via and the signal wiring via, wherein each of the plurality of sacrificial vias is separated from each other by a passivation layer.

6. An integrated circuit structure, characterized in that: include: a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and A redistribution layer structure is formed above the interconnect structure, wherein the redistribution layer structure comprises: a redistribution layer pad portion having a pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal routing portion having a signal routing via located on a second top metal line of the interconnect structure; and a redistribution layer top, located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, The plurality of vias of the pad via array include a plurality of peripheral vias arranged along the edge of the redistribution layer pad portion, wherein each of the plurality of peripheral vias is closer to another of the plurality of peripheral vias than the signal wiring via.

7. The integrated circuit structure according to claim 6, characterized in that: The plurality of peripheral vias have the same size.

8. The integrated circuit structure according to claim 7, wherein: The plurality of vias of the pad via array further include a plurality of central vias surrounded by the plurality of peripheral vias, the plurality of central vias having the same size as the plurality of peripheral vias. 9 . The integrated circuit structure of claim 8 , wherein the spacings between adjacent central vias, between adjacent peripheral vias, and between one of the peripheral vias and one of the central vias are the same.

10. An integrated circuit structure, characterized in that: include: a semiconductor substrate; an interconnect structure formed above the semiconductor substrate; and A redistribution layer structure is formed above the interconnect structure, wherein the redistribution layer structure comprises: a redistribution layer pad portion having a pad via array having a plurality of vias located on a first top metal line of the interconnect structure; a redistribution layer signal routing portion having a signal routing via located on a second top metal line of the interconnect structure; and a redistribution layer top, located above the redistribution layer pad portion and the redistribution layer signal wiring portion, the redistribution layer top connecting the redistribution layer pad portion and the redistribution layer signal wiring portion together, The first top metal line has a first length along a first direction, the second top metal line has a second length along the first direction, and the first length is greater than the second length. The first top metal line has a bottom surface that is not in contact with any metal component, and the second top metal line has a bottom surface that is directly in contact with a metal via of a semiconductor device wired to the semiconductor substrate.

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