Anti-creeping switching circuit

Abstract

The utility model relates to an anti-creeping switching circuit, which comprises P-type MOS (Metal Oxide Semiconductor) tubes PM0, PM1, PM3, PM4, PM5, PM6 and PM7, N-type MOS tubes NM0, NM1 and NM2, a buffer 1, a buffer 2 and a buffer 3, pM0, PM1, PM2, PM3 and PM4 are connected to the same floating N well 1, and PM5, PM6 and PM7 are connected to the same floating N well 2; the NM0 is connected with the PM6 and the PM7, the NM1 is connected with the PM0, and the NM2 is connected with the PM2 and the PM4; the input end of the buffer 1 is connected with an input switching signal SW, and the output end of the buffer 1 is connected with the PM5 and the NM1; the input end of the buffer 2 is connected with VDD, and the output end is connected with PM7; the input end of the buffer 3 is connected with VDD, and the output end is connected with PM4. According to the utility model, the problem of electric leakage caused by the fact that a preceding-stage chip provides voltage for an I / O port after the chip is powered down is prevented.

Description

Technical Field

[0001] The utility model relates to the field of leakage protection, in particular to an anti-leakage switch circuit. Background Art

[0002] After the MCU chip of the existing leakage protection circuit is powered off, its previous chip still provides voltage to its pin or IO port. In this scenario, if the IO port uses a P-type MOS tube as the input of the IO port, such as Figure 1 As shown, there is a PN junction between the input of the P-type MOS tube and the N-type well of the MOS tube. The PN junction is forward-conducted, which will cause serious leakage.

[0003] like Figure 2 As shown, the prior art avoids the leakage problem of using P-type MOS tubes by using N-type MOS tubes and the principle that the parasitic PN junction of the NMOS tube is reverse non-conductive; however, when the input signal is close to VDD, the switch impedance of this technical solution increases rapidly, which seriously limits the upper limit of the input signal and cannot support rail-to-rail input signals. In addition, in order to transmit rail-to-rail input signals, a higher gate voltage is required. Utility Model Content

[0004] The purpose of the utility model is to overcome the shortcomings of the prior art, provide an anti-leakage switch circuit, and solve the deficiencies of the prior art.

[0005] The purpose of the utility model is achieved by the following technical solutions: an anti-leakage switch circuit, which includes P-type MOS tubes PM0, PM1, PM3, PM4, PM5, PM6 and PM7, N-type MOS tubes NM0, NM1 and NM2, and buffers 1, 2 and 3;

[0006] The PM0, PM1, PM2, PM3 and PM4 are connected to the same floating N well 1, and PM5, PM6 and PM7 are connected to the same floating N well 2; the NM0 is connected to PM6 and PM7, NM1 is connected to PM0, NM2 is connected to PM2 and PM4, and NM0, NM1 and NM2 are also connected to VDD; the PM0 and PM3 are connected to the I / O port;

[0007] The input end of the buffer 1 is connected to the input switch signal SW, and the output end is connected to PM5 and NM1; the input end of the buffer 2 is connected to VDD, and the output end is connected to PM7; the input end of the buffer 3 is connected to VDD, and the output end is connected to PM4.

[0008] The gate of PM0, the source of PM1, the source of PM2, the source of PM3 and the source of PM4 are connected to the same floating N-well 1; the sources of PM5, PM6 and PM7 are connected to the same floating N-well 2; the gate of PM0 is also connected to the drain of PM1 and the drain of PM5.

[0009] The gate of NM0 is connected to VDD, the source is grounded, and the drain is connected to the gate of PM7 and the drain of PM6; the gate of NM1 is connected to the output end of buffer 1, the source is grounded, and the drain is connected to the gate of PM0; the gate of NM2 is connected to VDD, the source is grounded, and the drain is connected to the gate of PM4 and the drain of PM2.

[0010] The input end of the buffer 1 is connected to the switching signal SW, and the output end is connected to the gates of PM5 and NM1 respectively; the input end of the buffer 2 is connected to VDD, and the output end is connected to the drain of PM7; the input end of the buffer 3 is connected to VDD, and the output end is connected to the drain of PM4.

[0011] The I / O ports are respectively connected to the source of PM0 and the drain of PM3 , the gates of PM1 and PM2 are also connected to VDD, and the input switch signal SW is also connected to the gate of NM3 .

[0012] The utility model has the following advantages: an anti-leakage switch circuit prevents the problem of leakage caused by the front-stage chip providing voltage to the I / O port after the chip loses power. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Schematic diagram of the traditional CMOS switch state in a power-off scenario;

[0014] Figure 2 Schematic diagram of the NMOS switch state in a power-off scenario;

[0015] Figure 3 It is a circuit diagram of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. The utility model is further described below in conjunction with the drawings.

[0017] like Figure 1 As shown, the utility model specifically relates to an anti-leakage switch circuit, which includes P-type MOS tubes PM0, PM1, PM3, PM4, PM5, PM6 and PM7, N-type MOS tubes NM0, NM1 and NM2, and buffer 1 (buffer1), buffer 2 (buffer2) and buffer 3 (buffer3); PM0, PM1, PM2, PM3 and PM4 are connected to the same floating N well 1, PM5, PM6 and PM7 are connected to the same floating N well 2; NM0 is connected to PM6 and PM7, NM1 is connected to PM0, NM2 is connected to PM2 and PM4, and NM0, NM1 and NM2 are also connected to VDD; PM0 and PM3 are connected to an I / O port; the input end of buffer 1 is connected to an input switch signal SW, and the output end is connected to PM5 and NM1; the input end of buffer 2 is connected to VDD, and the output end is connected to PM7; the input end of buffer 3 is connected to VDD, and the output end is connected to PM4.

[0018] PM0 and NM3 are switch tubes, SW is the control signal of the switch, N well 1 is the N well of the input switch tube PM0, and N well 2 is the PMOS tube well in the control circuit of the switch tube PM0. After the chip is powered off, the gate terminal and substrate of the P-type MOS of the switch tube are connected to the input I / O, and can follow the change of the input voltage. The input of the P-type MOS tube to the N well potential is realized, and the input level is followed. The PN junction between the I / O input and the N well cannot be turned on, which solves the leakage current problem and presents a high impedance state to the outside of the chip.

[0019] Furthermore, the gate of PM0, the source of PM1, the source of PM2, the source of PM3 and the source of PM4 are connected to the same floating N-well 1; the sources of PM5, PM6 and PM7 are connected to the same floating N-well 2; the gate of PM0 is also connected to the drain of PM1 and the drain of PM5. The gate of NM0 is connected to VDD, the source is grounded, and the drain is connected to the gate of PM7 and the drain of PM6; the gate of NM1 is connected to the output end of buffer 1, the source is grounded, and the drain is connected to the gate of PM0; the gate of NM2 is connected to VDD, the source is grounded, and the drain is connected to the gate of PM4 and the drain of PM2.

[0020] Furthermore, the input end of buffer 1 is connected to the switch signal SW, and the output end is connected to the gates of PM5 and NM1 respectively; the input end of buffer 2 is connected to VDD, and the output end is connected to the drain of PM7; the input end of buffer 3 is connected to VDD, and the output end is connected to the drain of PM4. The I / O port is connected to the source of PM0 and the drain of PM3 respectively, the gates of PM1 and PM2 are also connected to VDD, and the input switch signal SW is also connected to the gate of NM3.

[0021] The working process of the utility model is as follows: When the chip is powered, the VDD potential exists. ①NM2 is turned on, PM4 is turned on, and PM1 / PM2 / PM3 are turned off. The floating N-well 1 is connected to the power supply voltage VDD, and the substrate of the switch tube PM0 is switched from IO power supply to the power supply voltage VDD. ②NM0 is turned on, PM6 is turned off, PM7 is turned on, and the floating N-well 2 is connected to the power supply voltage. When the input switch control signal SW is high, NM1 is turned on, PM5 is turned off, the gate terminal of PM0 is connected to the ground potential GND, and the switch tube PM0 is turned on; when the input switch signal SW is low, NM1 is turned off, PM5 is turned on, the gate terminal of PM0 is connected to VDD, and the switch tube PM0 is turned off.

[0022] When the chip is powered off, the VDD potential does not exist or is at a low potential. NM2 is turned off, the gate of PM1 / PM3 / PM2 is at a low potential and is in the on state, and the floating N-well 1 is connected to the input IO and follows the input level of IO. When the input IO signal is high, PM3 is turned on, N-well 1 follows the input signal to a high level, the PN junction between the input of input tube PM0 and N-well 1 is not conductive, and there is no leakage. At the same time, PM1 is turned on, the floating N-well 2 and the gate of switch PM0 are connected to the input IO at the same time, the gate of the input tube switch follows the input IO, the switch is in the off state, the channel is disconnected, and the leakage is further reduced.

[0023] The above is only a preferred embodiment of the utility model. It should be understood that the utility model is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used for various other combinations, modifications and improvements, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge in the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the utility model, and should be within the scope of protection of the claims attached to the utility model.

Claims

1. A leakage protection switch circuit, characterized in that: It includes P-type MOS tubes PM0, PM1, PM3, PM4, PM5, PM6 and PM7, N-type MOS tubes NM0, NM1 and NM2, and buffers 1, 2 and 3; The PM0, PM1, PM2, PM3 and PM4 are connected to the same floating N well 1, and PM5, PM6 and PM7 are connected to the same floating N well 2; the NM0 is connected to PM6 and PM7, NM1 is connected to PM0, NM2 is connected to PM2 and PM4, and NM0, NM1 and NM2 are also connected to VDD; the PM0 and PM3 are connected to the I / O port; The input end of the buffer 1 is connected to the input switch signal SW, and the output end is connected to PM5 and NM1; the input end of the buffer 2 is connected to VDD, and the output end is connected to PM7; the input end of the buffer 3 is connected to VDD, and the output end is connected to PM4.

2. The leakage protection switch circuit according to claim 1, characterized in that: The gate of PM0, the source of PM1, the source of PM2, the source of PM3 and the source of PM4 are connected to the same floating N-well 1; the sources of PM5, PM6 and PM7 are connected to the same floating N-well 2; the gate of PM0 is also connected to the drain of PM1 and the drain of PM5.

3. The leakage protection switch circuit according to claim 1, characterized in that: The gate of NM0 is connected to VDD, the source is grounded, and the drain is connected to the gate of PM7 and the drain of PM6; the gate of NM1 is connected to the output end of buffer 1, the source is grounded, and the drain is connected to the gate of PM0; the gate of NM2 is connected to VDD, the source is grounded, and the drain is connected to the gate of PM4 and the drain of PM2.

4. The leakage protection switch circuit according to claim 1, characterized in that: The input end of the buffer 1 is connected to the switching signal SW, and the output end is connected to the gates of PM5 and NM1 respectively; the input end of the buffer 2 is connected to VDD, and the output end is connected to the drain of PM7; the input end of the buffer 3 is connected to VDD, and the output end is connected to the drain of PM4.

5. The leakage protection switch circuit according to claim 1, characterized in that: The I / O ports are respectively connected to the source of PM0 and the drain of PM3 , the gates of PM1 and PM2 are also connected to VDD, and the input switch signal SW is also connected to the gate of NM3 .

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