Power switch circuit and control circuit

Abstract

The embodiment of the utility model belongs to the technical field of power circuits, and particularly relates to a power switch circuit and a control circuit, and the power switch circuit comprises a key, a first time delay circuit, a second time delay circuit, a first switch tube, a second switch tube and a reset circuit. A precise control logic and protection mechanism is realized, multi-level protection can be provided, including de-jitter processing of key operation, and stable triggering is ensured; through the two-stage delay design, the immunity of the system to misoperation is improved, and error reset caused by instantaneous interference is avoided.

Description

Technical Field

[0001] The embodiments of the present application belong to the technical field of power supply circuits, and in particular, relate to a power supply switch circuit and a control circuit. Background Art

[0002] In existing power circuits, the system operation is often suspended and the power control module (MCU) cannot restart autonomously, which requires a manual reset mechanism as a remedial measure. A common practice is to reserve a reset button and corresponding vias inside the device so that the MCU can be reset by physical means. However, this method introduces several design challenges: the first is the problem of electrostatic protection. The exposure of the reset via increases the risk of electrostatic discharge and requires strict electrostatic protection measures. Secondly, for products with a waterproof rating, the via design requires additional sealing technology to maintain its protection performance, which undoubtedly increases manufacturing complexity and cost. In addition, the infrequent use of the reset button leads to its hidden location, and users often need to rely on the instructions, which affects the ease of use of the product. Utility Model Content

[0003] The embodiments of the present application provide a power switch circuit and a control circuit, which realize multiplexing of the power switch and reset functions through a hardware circuit, so that a short press of the switch can turn the machine on and off, and a long press of the switch can reset the power control module.

[0004] On one hand, an embodiment of the present application provides a power switch circuit, including a button, a first delay circuit, a second delay circuit, a first switch tube, a second switch tube and a reset circuit;

[0005] One end of the button is connected to the power button signal input end of the power control module, the output end of the first delay circuit, the output end of the first switch tube, the output end of the second delay circuit and the output end of the second switch tube, and the other end of the button is grounded;

[0006] The input end of the first delay circuit is connected to a power supply, and the control voltage end of the first delay circuit is connected to a controlled end of the first switch tube;

[0007] The input end of the first switch tube is connected to the control voltage end of the second delay circuit and the controlled end of the second switch tube;

[0008] The input end of the second delay circuit is connected to a power supply;

[0009] The input end of the second switch tube is connected to the first output end of the reset circuit;

[0010] The input end of the reset circuit is connected to the power supply, the second output end of the reset circuit is connected to the reset signal input end of the power control module, and the third output end of the reset circuit is grounded.

[0011] In one embodiment, the first delay circuit includes a first capacitor, a fourth resistor and the first resistor;

[0012] One end of the first capacitor and one end of the first resistor are connected together to form the input end of the first delay circuit, one end of the fourth resistor forms the output end of the first delay circuit, and the other end of the first capacitor, the other end of the first resistor and the other end of the fourth resistor are connected together to form the control voltage end of the first delay circuit.

[0013] In one embodiment, the gate of the first switch tube is the controlled end of the first switch tube, the drain of the first switch tube is the input end of the first switch tube, and the source of the first switch tube is the output end of the first switch tube.

[0014] In one embodiment, the second delay circuit includes a third resistor and a second capacitor;

[0015] One end of the third resistor constitutes the input end of the second delay circuit, the other end of the third resistor and one end of the second capacitor are connected together to form the control voltage end of the second delay circuit, and the other end of the second capacitor constitutes the output end of the second delay circuit.

[0016] In one embodiment, the gate of the second switch tube is the controlled end of the second switch tube, the drain of the second switch tube is the input end of the second switch tube, and the source of the second switch tube is the output end of the second switch tube.

[0017] In one embodiment, the reset circuit includes a second resistor, a fifth resistor and a third capacitor;

[0018] One end of the second resistor constitutes the input end of the reset circuit, the other end of the second resistor is connected together with one end of the fifth resistor to constitute the first output end of the reset circuit, the other end of the fifth resistor is connected together with one end of the third capacitor to constitute the second output end of the reset circuit, and the other end of the third capacitor constitutes the third output end of the reset circuit.

[0019] In one embodiment, the delay time of the first delay circuit is shorter than the delay time of the second delay circuit.

[0020] In one embodiment, the delay time of the first delay circuit is shorter than 100 milliseconds.

[0021] In one embodiment, the delay time of the second delay circuit is 5 to 15 seconds.

[0022] Another aspect of the embodiment of the present application further provides a power control circuit, including a power control module and the power switch circuit provided by the first aspect of the embodiment of the present application;

[0023] The reset signal output terminal of the power switch circuit is electrically connected to the reset signal input terminal of the power control module, and the power key signal output terminal of the power switch circuit is electrically connected to the power key signal input terminal of the power control module.

[0024] The power switch circuit provided in the first aspect of the embodiment of the present application includes a button, a first delay circuit, a second delay circuit, a first switch tube, a second switch tube and a reset circuit; one end of the button is connected to the power key signal input end of the power control module, the output end of the first delay circuit, the output end of the first switch tube, the output end of the second delay circuit and the output end of the second switch tube, and the other end of the button is grounded; the input end of the first delay circuit is connected to the power supply, and the control voltage end of the first delay circuit is connected to the controlled end of the first switch tube; the input end of the first switch tube is connected to the control voltage end of the second delay circuit and the controlled end of the second switch tube; the input end of the second delay circuit is connected to the power supply; the input end of the second switch tube is connected to the first output end of the reset circuit; the input end of the reset circuit is connected to the power supply, the second output end of the reset circuit is connected to the reset signal input end of the power control module, and the third output end of the reset circuit is grounded. By integrating the button, the two-stage delay circuit, the switch tube and the reset circuit, precise control logic and protection mechanism are realized. It can provide multi-level protection, including de-jitter processing for key operations to ensure stable triggering; the two-level delay design increases the system's immunity to misoperation and avoids false resets caused by transient interference; at the same time, the integration of the reset circuit directly communicates with the power control module, which not only ensures the accurate transmission of the reset signal, but also supports timely and effective reset control of the power control module, thereby improving the robustness of the entire power management system and user operation experience, and reducing the risk of system instability caused by external interference or abnormal conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 is a structural schematic diagram of a power switch circuit provided by an embodiment of the present application;

[0027] Figure 2is a structural schematic diagram of a power switch circuit provided in yet another embodiment of the present application;

[0028] Figure 3 It is a control flow diagram of a power switch circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0029] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0030] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0031] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. "Multiple" means two or more.

[0034] like Figure 1 As shown, a power switch circuit provided in an embodiment of the present application includes a button 101, a first delay circuit 102, a second delay circuit 104, a first switch tube 103, a second switch tube 105 and a reset circuit 106;

[0035] One end of the button 101 is connected to the power button signal input end of the power control module 20, the output end of the first delay circuit 102, the output end of the first switch tube 103, the output end of the second delay circuit 104 and the output end of the second switch tube 105, and the other end of the button 101 is grounded;

[0036] The input end of the first delay circuit 102 is connected to a power supply, and the control voltage end of the first delay circuit 102 is connected to a controlled end of the first switch tube 103;

[0037] The input end of the first switch tube 103 is connected to the control voltage end of the second delay circuit 104 and the controlled end of the second switch tube 105;

[0038] The input end of the second delay circuit 104 is connected to a power supply;

[0039] The input end of the second switch tube 105 is connected to the first output end of the reset circuit 106;

[0040] An input terminal of the reset circuit 106 is connected to a power source, a second output terminal of the reset circuit 106 is connected to a reset signal input terminal of the power control module 20 , and a third output terminal of the reset circuit 106 is grounded.

[0041] In application, the button 101 may be a mechanical micro switch or a tactile switch, such as the Omron B3F series, for receiving user operation signals such as power on and reset.

[0042] In application, the first delay circuit 102 may adopt an RC (resistance-capacitance) delay circuit, for example, a resistor and a capacitor are connected in series to perform preliminary de-jittering and provide a short delay to ensure the stability of the key signal.

[0043] In application, the second delay circuit 104 can use an RC circuit or a more complex delay circuit such as a 555 timer to reconfirm the operation intention after the first level delay. For example, a longer delay period (several seconds to tens of seconds) is set by the 555 timer to implement a secondary confirmation mechanism.

[0044] In applications, the first switch tube 103 often uses an N-channel MOSFET, such as NP2306FVR, to control the transmission of the signal. When the output signal of the first delay circuit reaches the threshold, the MOSFET is turned on, allowing the signal to continue to flow to the next link. The second switch tube 105 can also use an N-channel MOSFET, such as NP2306FVR, and its function is to trigger the reset function through the reset circuit after the second-stage delay ends.

[0045] In application, the reset circuit 106 can be a Schmitt trigger circuit for shaping and buffering the signal from the second delay circuit and generating a reset pulse to the power control module 20 at an appropriate time. A more complex microprocessor-controlled reset IC, such as MAX810, can also be used to generate a reset signal according to preset conditions and have an adjustable reset delay and a manual reset input function.

[0046] This embodiment provides a power switch circuit, which realizes precise control logic and protection mechanism by integrating buttons, two-stage delay circuit, switch tube and reset circuit. It can provide multi-level protection, including de-jitter processing for button operation to ensure stable triggering; through two-stage delay design, it increases the system's immunity to misoperation and avoids false reset caused by transient interference; at the same time, the integration of the reset circuit directly communicates with the power control module, which not only ensures the accurate transmission of the reset signal, but also supports timely and effective reset control of the power control module, thereby improving the robustness of the entire power management system and the user operation experience, and reducing the risk of system instability caused by external interference or abnormal conditions.

[0047] In one embodiment, Figure 2 As shown, a power switch circuit includes a button K1, a first delay circuit 102, a second delay circuit 104, a switch tube Q1, a switch tube Q2 and a reset circuit 106;

[0048] One end of the button K1 is connected to the power button signal input end of the power control module 20, the output end of the first delay circuit 102, the output end of the switch tube Q1, the output end of the second delay circuit 104 and the output end of the switch tube Q2, and the other end of the button K1 is grounded;

[0049] The input end of the first delay circuit 102 is connected to the power supply, and the control voltage end of the first delay circuit 102 is connected to the controlled end of the switch tube Q1;

[0050] The input end of the switch tube Q1 is connected to the control voltage end of the second delay circuit 104 and the controlled end of the switch tube Q2;

[0051] The input end of the second delay circuit 104 is connected to a power supply;

[0052] The input end of the switch tube Q2 is connected to the first output end of the reset circuit 106;

[0053] An input terminal of the reset circuit 106 is connected to a power source, a second output terminal of the reset circuit 106 is connected to a reset signal input terminal of the power control module 20 , and a third output terminal of the reset circuit 106 is grounded.

[0054] In one embodiment, the first delay circuit 102 includes a capacitor C1, a resistor R4 and a resistor R1;

[0055] One end of the capacitor C1 and one end of the resistor R1 are connected together to form the input end of the first delay circuit 102, one end of the resistor R4 forms the output end of the first delay circuit 102, and the other end of the capacitor C1, the other end of the resistor R1 and the other end of the resistor R4 are connected together to form the control voltage end of the first delay circuit 102.

[0056] In application, due to the existence of the RC network, the voltage rise (or fall) rate is limited, forming a controllable delay effect. This delay time depends on the RC time constant. By adjusting the values ​​of R1 and C1, the delay time can be freely changed to meet different system requirements. Once the delay time is over, the subsequent control logic can be activated by controlling the voltage change of the voltage end (i.e., the charging and discharging node), such as turning on the first switch tube 103, and then starting the second level delay or other predetermined operations. This design not only ensures the stability of the operation, but also improves the anti-interference ability of the system.

[0057] In one embodiment, the gate of the switch tube Q1 is the controlled end of the switch tube Q1 , the drain of the switch tube Q1 is the input end of the switch tube Q1 , and the source of the switch tube Q1 is the output end of the switch tube Q1 .

[0058] In one embodiment, the second delay circuit 104 includes a resistor R3 and a capacitor C2;

[0059] One end of the resistor R3 constitutes the input end of the second delay circuit 104 , the other end of the resistor R3 and one end of the capacitor C2 are connected together to constitute the control voltage end of the second delay circuit 104 , and the other end of the capacitor C2 constitutes the output end of the second delay circuit 104 .

[0060] In one embodiment, the gate of the switch tube Q2 is the controlled end of the switch tube Q2 , the drain of the switch tube Q2 is the input end of the switch tube Q2 , and the source of the switch tube Q2 is the output end of the switch tube Q2 .

[0061] In application, the delay time of the second delay circuit can be precisely controlled by adjusting the resistance of resistor R3 and the capacity of capacitor C2. Therefore, the specific duration of the second-level delay can be freely adjusted according to the needs of actual applications to achieve the best system response and user experience. In addition, the second delay circuit can effectively remove the jitter phenomenon caused by the closing or opening of the switch contacts, ensuring that the subsequent circuit action will only be triggered in a stable state, thereby improving the stability and reliability of the system.

[0062] In one embodiment, the reset circuit 106 includes a resistor R2, a resistor R5 and a capacitor C3;

[0063] One end of the resistor R2 constitutes the input end of the reset circuit 106, the other end of the resistor R2 and one end of the resistor R5 are connected together to constitute the first output end of the reset circuit 106, the other end of the resistor R5 and one end of the capacitor C3 are connected together to constitute the second output end of the reset circuit 106, and the other end of the capacitor C3 constitutes the third output end of the reset circuit 106.

[0064] In the application, the input end of the reset circuit is connected to the power supply through resistor R2. This design helps to filter out the noise that may exist on the power supply line. Resistor R2 plays a preliminary role in voltage stabilization and noise reduction, ensuring the purity of the reset signal, thereby improving the stability and reliability of the circuit. Resistor R2 and capacitor C3 are used to generate reset output when power is turned on, and resistor R5 is used to eliminate the short-term conduction of switch tube Q2 when the key is pressed. By adjusting the values ​​of resistor R5 and capacitor C3, the length of the reset process can be accurately controlled to meet the reset timing requirements of different systems.

[0065] In one embodiment, the delay time of the first delay circuit 102 is shorter than the delay time of the second delay circuit 104 .

[0066] In application, the delay time of the first delay circuit 102 is shorter than 100 milliseconds, and the delay time of the second delay circuit 104 is 5 to 15 seconds.

[0067] In this embodiment, the delay time of the first delay circuit 102 is set to be much shorter than the delay time of the second delay circuit 104, so that the circuit does not accumulate the key press time when the key is pressed intermittently multiple times, thereby preventing multiple key presses from falsely triggering reset.

[0068] The embodiment of the present application also provides a power control circuit, including a power control module 20 and the power switch circuit 10 as described above;

[0069] The reset signal output terminal of the power switch circuit is electrically connected to the reset signal input terminal of the power control module 20 , and the power key signal output terminal of the power switch circuit is electrically connected to the power key signal input terminal of the power control module 20 .

[0070] In the application, the power control module 20 is the control core of the power supply, which can be a microcontroller (MCU), SoC or a dedicated power management IC (such as TPS61090), which is responsible for receiving the power key signal input and the reset signal, and performing the corresponding power on, power off or reset operations according to these signals. The power control circuit of the embodiment of the present application can adapt to different types of power control modules, whether it is a simple microcontroller control or a complex power management system, it can be matched by adjusting the delay time and the characteristics of the reset signal to meet the diverse product requirements.

[0071] like Figure 3 As shown, a control flow of a power switch circuit provided in an embodiment of the present application is as follows:

[0072] When the power control module (MCU) is powered on, if the button is pressed shortly, the device is turned on or off. If the button is pressed long, a reset signal is output to the power control module to reset the device.

[0073] In application, a power switch circuit realizes the control process through the above circuit structure as follows:

[0074] When the MCU is powered on and the button K1 is not pressed, one end of the button K1 pin is grounded and the other end is pulled up in series by resistors R1 and R4. The GPIO of the MCU connected to the KEY_POWER pin is in a high level state. At the same time, the source voltage of the switch tubes Q1 and Q2 is approximately equal to VCC, and the switch tubes Q1 and Q2 are not turned on. The chip reset pin is composed of the reset circuit composed of resistor R2 and capacitor C3, which outputs a high level, and the chip works normally.

[0075] When the MCU is powered on normally, press button K1 for a short time, and the GPIO of the MCU connected to the KEY_POWER pin is connected to GND. The MCU detects the shutdown signal, and the source of the switch tubes Q1 and Q2 are connected to GND. The gate of the switch tube Q1 is in the on state due to the voltage division of the resistor R1 and the resistor R4. The drain of the switch tube Q1 is connected to GND, and the gate of the switch tube Q2 is also connected to GND. The switch tube Q2 is in the off state. The chip can detect the shutdown signal normally, but no reset will be generated.

[0076] When the MCU is powered on normally, press button K1 for a long time, the sources of the switches Q1 and Q2 are connected to GND, and a first-level delay circuit is formed by resistor R4 and capacitor C1. Resistor R4 charges capacitor C1, and the gate voltage of the switch Q1 gradually decreases until the switch Q1 is turned off; after the switch Q1 is turned off, resistor R3 of the second-level delay circuit starts to charge capacitor C2, and the gate voltage of the switch Q2 gradually becomes a high level until the switch Q2 is turned on; after the switch Q2 is turned on, the drain of the switch Q2 is connected to GND, and a reset signal is output at this time to complete the resetting of the MCU.

[0077] When the MCU is powered on normally, the situation of pressing button K1 intermittently multiple times is as follows: when button K1 is released, resistor R1 will discharge capacitor C1. Since the delay time of the first-level delay circuit is short, the gate of switch tube Q1 is quickly charged to the turn-on voltage. When button K1 is pressed again, the source of switch tube Q1 is grounded, switch tube Q1 is turned on, and capacitor C2 connected to the drain of switch tube Q1 will discharge until the first-level delay circuit completes charging. Then switch tube Q1 is turned off, resistor R3 starts to charge capacitor C2, and the second-level circuit delay starts until switch tube Q2 is turned on. It can be seen that this circuit will not accumulate the key press time when the button is pressed intermittently multiple times, which can prevent multiple key presses from triggering reset by mistake;

[0078] In the application, the delay time is determined by R4, C1, R3, C2, voltage VCC and the on-voltage of the switch tube. The delay time is calculated as follows:

[0079] t1=RC*Ln[(V1-V0) / (V1-Vt)]

[0080] Among them, R is the charging resistor; C is the charging capacitor; V0 is the initial voltage of the capacitor; Vt is the turn-on voltage of the switch tube, that is, the capacitor voltage at time t1; V1 is the voltage VCC, that is, the voltage that the capacitor finally charges to.

[0081] When R1=1M, R4=100K, C1=0.1uF, Q1 conduction voltage 0.75V, power supply voltage VCC=3.3V, that is, V0=0, Vt=75, V1=3.3V, the first-stage delay discharge time can be calculated:

[0082] t1=1*106*0.1*10-6*Ln[(3.3-0) / (3.3-0.75)]≈0.0257S

[0083] When R3=3.9M, C2=10uF, Q1 conduction voltage 0.75V, charging voltage VCC=3.3V, that is, V0=0, Vt=75, V1=3.3V, the discharge time, that is, the secondary delay time, can be calculated:

[0084] t1=3.9*106*10*10-6*Ln[(3.3-0) / (3.3-0.75)]≈10.055S

[0085] In the application, after releasing the button K1, the circuit recovery time is determined by R1 and C1, and the discharge time t2 is calculated as follows:

[0086] t2=R1C1*Ln[(V01-V11) / (Vt1-V11)]

[0087] Among them, R1 is the discharging resistor; C1 is the capacitor to be discharged; V01 is the initial voltage of the capacitor; Vt1 is the capacitor voltage at time t2; V11 is the voltage reached by the capacitor after final discharge.

[0088] When R1=1M, C1=0.1uF, power supply voltage 3.3V, switch tube conduction voltage 0.75V, that is, V01=3.3, Vt1=0.75, V11=0, the discharge time can be calculated:

[0089] t2=1*106*0.1*10-6*Ln[(3.3-0) / (0.75-0)]≈0.148S.

[0090] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A power switch circuit, characterized in that: It includes a button, a first delay circuit, a second delay circuit, a first switch tube, a second switch tube and a reset circuit; One end of the button is connected to the power button signal input end of the power control module, the output end of the first delay circuit, the output end of the first switch tube, the output end of the second delay circuit and the output end of the second switch tube, and the other end of the button is grounded; The input end of the first delay circuit is connected to a power supply, and the control voltage end of the first delay circuit is connected to a controlled end of the first switch tube; The input end of the first switch tube is connected to the control voltage end of the second delay circuit and the controlled end of the second switch tube; The input end of the second delay circuit is connected to a power supply; The input end of the second switch tube is connected to the first output end of the reset circuit; The input end of the reset circuit is connected to the power supply, the second output end of the reset circuit is connected to the reset signal input end of the power control module, and the third output end of the reset circuit is grounded.

2. The power switch circuit according to claim 1, characterized in that: The first delay circuit includes a first capacitor, a fourth resistor and the first resistor; One end of the first capacitor and one end of the first resistor are connected together to form the input end of the first delay circuit, one end of the fourth resistor forms the output end of the first delay circuit, and the other end of the first capacitor, the other end of the first resistor and the other end of the fourth resistor are connected together to form the control voltage end of the first delay circuit.

3. The power switch circuit according to claim 1, wherein: The gate of the first switch tube is a controlled end of the first switch tube, the drain of the first switch tube is an input end of the first switch tube, and the source of the first switch tube is an output end of the first switch tube.

4. The power switch circuit according to claim 1, wherein: The second delay circuit includes a third resistor and a second capacitor; One end of the third resistor constitutes the input end of the second delay circuit, the other end of the third resistor and one end of the second capacitor are connected together to form the control voltage end of the second delay circuit, and the other end of the second capacitor constitutes the output end of the second delay circuit.

5. The power switch circuit according to claim 1, wherein: The gate of the second switch tube is the controlled end of the second switch tube, the drain of the second switch tube is the input end of the second switch tube, and the source of the second switch tube is the output end of the second switch tube.

6. The power switch circuit according to claim 1, wherein: The reset circuit includes a second resistor, a fifth resistor and a third capacitor; One end of the second resistor constitutes the input end of the reset circuit, the other end of the second resistor is connected together with one end of the fifth resistor to constitute the first output end of the reset circuit, the other end of the fifth resistor is connected together with one end of the third capacitor to constitute the second output end of the reset circuit, and the other end of the third capacitor constitutes the third output end of the reset circuit.

7. The power switch circuit according to claim 1, wherein: The delay time of the first delay circuit is shorter than the delay time of the second delay circuit.

8. The power switch circuit according to claim 1, wherein: The delay time of the first delay circuit is shorter than 100 milliseconds.

9. The power switch circuit according to claim 1, wherein: The delay time of the second delay circuit is 5 to 15 seconds.

10. A power control circuit, characterized in that: comprising a power control module and a power switch circuit as claimed in any one of claims 1 to 9; The reset signal output terminal of the power switch circuit is electrically connected to the reset signal input terminal of the power control module, and the power key signal output terminal of the power switch circuit is electrically connected to the power key signal input terminal of the power control module.

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