Capacitive coupling type digital isolator
By setting the isolation capacitor separately and using independent substrate and electrode design, the problem of difficult to optimize the dielectric layer thickness and capacitance value in the prior art is solved, and the voltage withstandability and safety of the capacitive coupled digital isolator is improved.
Patent Information
- Application Number
- CN202421631010.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-07-10
AI Technical Summary
The existing capacitively coupled digital isolators have difficulties in flexible optimization of dielectric layer thickness and capacitance value, resulting in insufficient voltage withstandability and safety.
By setting the isolation capacitor separately and using independent substrate and electrode design, it breaks through the limitations of the optional metal level of semiconductor FAB, flexibly adjusts the substrate thickness and electrode area, and optimizes the capacitance value.
The voltage withstandability and safety of the capacitively coupled digital isolators are improved, the chip size limitation is eliminated, and the capacitance value is flexible.
Smart Images
Figure CN222884662U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of power electronics technology, and in particular to a capacitively coupled digital isolator. Background Art
[0002] Signal isolation is to separate the low-voltage domain circuit and the high-voltage domain circuit in the system at the physical layer to protect the low-voltage system and users from high-voltage damage. The signal is transmitted between the high-voltage domain and the low-voltage domain by coupling. Capacitive coupling is a widely used signal isolation technology. Generally, SiO2 between metal layers is used as the isolation barrier. For high-voltage digital isolators, it is necessary to develop a dedicated thick dielectric film process on the standard CMOS process.
[0003] However, in the related art, the design of capacitively coupled digital isolators has the following problems:
[0004] 1. The high-voltage isolation capacitor is integrated on the chip. The high-voltage isolation capacitor based on the standard CMOS process needs to develop a special thick dielectric film process. The required thick SiO2 film is difficult to prepare and requires more metal layers. Therefore, the FAB requirements are high and the cost is also high;
[0005] 2. The metal layers available in FAB are limited, resulting in only a few specifications of SiO2 thickness available as the isolation barrier, which cannot be flexibly adjusted for different withstand voltage levels;
[0006] 3. Since the high-voltage isolation capacitor is integrated on the chip, the metal plate of the capacitor cannot be made very large due to the chip size, resulting in the inability to flexibly optimize the capacitance value according to design requirements. Summary of the invention
[0007] In order to address the deficiencies of the prior art, the purpose of the present application is to provide a capacitively coupled digital isolator, which can solve the technical problems existing in the related art that the dielectric layer thickness of the capacitive digital isolator is difficult to increase and the capacitance value is difficult to flexibly optimize.
[0008] To achieve the above-mentioned purpose, the present application adopts the following technical solution: a capacitively coupled digital isolator, comprising: a first chip, a second chip and an isolation capacitor; the first chip is arranged on a first substrate, on which a signal modulation circuit is provided; the second chip is arranged on a second substrate, on which a signal demodulation circuit is provided; the isolation capacitor is an independent device, which is electrically connected to the first chip and the second chip respectively through leads, wherein the isolation capacitor comprises two electrodes arranged at intervals and a substrate on which the two electrodes are placed.
[0009] Furthermore, the two electrodes at least include an overlapping area on the same projection plane, and a portion of the substrate sandwiched between the two electrodes constitutes a dielectric layer of the capacitor.
[0010] Furthermore, the two electrodes are respectively disposed on the opposite first surface and second surface of the substrate.
[0011] Furthermore, a pad electrically connected to the electrode is provided on the surface of the substrate on at least one side of the electrode.
[0012] Furthermore, the two electrodes are arranged inside the substrate and are separated by a predetermined distance.
[0013] Furthermore, each electrode is led out to a pad disposed on the surface of the substrate through a metal wire.
[0014] Furthermore, the isolation capacitor includes a first capacitor and a second capacitor, the first capacitor and the second capacitor respectively have two electrodes arranged at an interval, and the electrodes on the same side of the first capacitor and the second capacitor are located on the same plane.
[0015] Furthermore, the signal modulation circuit includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal are respectively connected to first side electrodes of the first capacitor and the second capacitor through leads.
[0016] Furthermore, the signal demodulation circuit includes a first receiving end and a second receiving end, and the first receiving end and the second receiving end are connected to the second side electrodes of the first capacitor and the second capacitor respectively through leads.
[0017] Furthermore, the substrate is made of one or a combination of glass, glass fiber epoxy resin, polyimide or polytetrafluoroethylene.
[0018] Furthermore, a shielding protective layer is provided outside the isolation capacitor, and the shielding protective layer at least covers two electrodes of the isolation capacitor.
[0019] Furthermore, two electrodes of the isolation capacitor are arranged inside the substrate, the shielding protection layer is arranged on the surface of the substrate, and the area of the shielding protection layer projected on the corresponding electrode is at least larger than the area of the corresponding electrode.
[0020] According to the above description, the present application can break through the limitation of the optional metal layer of the semiconductor FAB by setting the isolation capacitor separately, and can flexibly adjust the substrate thickness according to different withstand voltage energy levels, thereby improving the withstand voltage capability of the capacitively coupled digital isolator and improving the safety of the capacitively coupled digital isolator. In addition, setting the isolation capacitor separately can also make the capacitor design no longer limited by the chip size, and the area of the first electrode and the second electrode can be adjusted according to the needs, so as to realize the flexible optimization design of the capacitance value of the capacitively coupled digital isolator. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 A schematic diagram of a capacitively coupled digital isolator module provided in an embodiment of the present application;
[0022] Figure 2 A schematic diagram of the structure of a substrate-type high-voltage capacitor provided in the first embodiment of the present application;
[0023] Figure 3 A schematic diagram of the structure of a substrate-type high-voltage capacitor provided in the second embodiment of the present application;
[0024] Figure 4 A schematic diagram of a capacitively coupled digital isolator provided in one embodiment of the present application;
[0025] Figure 5 A schematic diagram of the structure of a substrate-type high-voltage capacitor provided in the third embodiment of the present application;
[0026] Figure 6 Schematic diagram of a digital isolator with a shielding protection layer provided in an embodiment of the present application. DETAILED DESCRIPTION
[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the specific implementation manner of the present application will be clearly and completely described below in conjunction with the drawings in the implementation manner of the present application.
[0028] The purpose of the present application is to provide a capacitively coupled digital isolator, which can solve the technical problems existing in the related art that the dielectric layer thickness of the capacitive digital isolator is difficult to increase and the capacitance value is difficult to flexibly optimize.
[0029] Based on the above purposes, Figure 1 As shown, an embodiment of the present application provides a capacitively coupled digital isolator 100 , including a first chip 11 , a second chip 12 , and an isolation capacitor 13 .
[0030] Among them, the first chip 11 is arranged on the first substrate, and a signal modulation circuit 111 is arranged on it; the second chip 12 is arranged on the second substrate, and a signal demodulation circuit 121 is arranged on it; the isolation capacitor 13 is an independent device, which is electrically connected to the first chip 11 and the second chip 12 through leads, wherein the isolation capacitor 13 includes two electrodes arranged at intervals, and a substrate 133 on which the two electrodes are placed.
[0031] Specifically, the first chip 11 serves as the signal input side of the capacitively coupled digital isolator 100, and is used to receive an input signal and transmit the input signal to a subsequent circuit after modulating the input signal through a signal modulation circuit 111. The second chip 12 serves as the signal output side of the capacitively coupled digital isolator 100, and is used to receive a signal sent by a previous circuit and transmit the signal to the outside after demodulating the signal through a signal demodulation circuit 121. The first chip 11 and the second chip 12 are coupled through an isolation capacitor 13 to realize signal transmission between the first chip 11 and the second chip 12. In actual use, in addition to the above-mentioned signal modulation circuit 111 and signal demodulation circuit 121, the first chip 11 and the second chip 12 also include other circuits to achieve corresponding functions. For the convenience of explanation, in the embodiment of the present invention, only the schematic diagram of the signal modulation circuit 111 and the signal demodulation circuit 121 is shown, and other circuits can be set according to actual usage. Further, considering that the capacitively coupled digital isolator 100 is usually fixed to the circuit board in the form of welding, therefore, solder joints or welding pins can also be set on the first chip 11 and the second chip 12. The specific details shall be based on the actual usage, and the embodiment of the present invention is not limited to this.
[0032] The isolation capacitor 13 provided in the embodiment of the present application includes two electrodes arranged at intervals, and a substrate 133 on which the two electrodes are placed. The two electrodes at least include an overlapping area on the same projection plane, and the portion of the substrate 133 sandwiched between the two electrodes constitutes a dielectric layer of the capacitor.
[0033] For ease of explanation, in the embodiment of the present application, the electrode connected to the first chip 11 is defined as the first electrode 131, and the electrode connected to the second chip 12 is defined as the second electrode 132. The direction perpendicular to the surface of the first electrode 131 is agreed to be the first direction. On the projection plane perpendicular to the first direction, the projection of the first electrode 131 along the first direction and the projection of the second electrode 132 along the first direction at least partially overlap, so that the first electrode 131, the second electrode 132 and the substrate 133 can constitute a capacitor structure, wherein the substrate 133 serves as the dielectric layer of the capacitor, and the substrate 133 is made of insulating material. The material of the substrate 133 can be one or a combination of the following materials: glass, glass fiber epoxy resin, polyimide or polytetrafluoroethylene. The thickness of the substrate 133 will affect the voltage resistance of the capacitor structure.
[0034] It should be noted that the isolation capacitor 13 provided in the present application is an independent device, which is relative to the first chip 11 and the second chip 12, that is, the isolation capacitor 13 is separately set relative to the first chip 11 and the second chip 12. The electrical connection between the isolation capacitor 13 and the first chip 11, and the isolation capacitor 13 and the second chip 12 can be achieved by bonding wires, or the copper pillars or solder balls of the flip chip can be used for implementation. It can also be set according to the actual use situation, and the embodiment of the present invention does not limit this. The present application sets the isolation capacitor 13 separately relative to the first chip 11 and the second chip 12, so that there is no need to develop a special thick dielectric film process based on the standard CMOS process, thereby reducing the difficulty of preparing the thick dielectric film in the isolation capacitor 13. In addition, by setting the isolation capacitor 13 separately, the limitation of the optional metal layer of the semiconductor FAB can be broken, and the thickness of the substrate 133 can be flexibly adjusted for different withstand voltage energy levels, thereby improving the withstand voltage capability of the capacitively coupled digital isolator 100 and improving the safety of the capacitively coupled digital isolator 100.
[0035] In addition, by separately setting the isolation capacitor 13 , the capacitor design is no longer limited by the chip size. The areas of the first electrode 131 and the second electrode 132 can be adjusted as required, thereby achieving flexible optimization design of the capacitance value of the capacitively coupled digital isolator 100 .
[0036] As an optional implementation, in the capacitively coupled digital isolator 100 provided in the embodiment of the present application, two electrodes are respectively arranged on the first surface and the second surface opposite to each other of the substrate 133, and the surface of the substrate 133 is provided with a pad 134 electrically connected to the electrode on at least one side of the electrode.
[0037] Specifically, Figure 2 As shown, a first electrode 131 is disposed on the first surface of the substrate 133 , and a second electrode 132 is disposed on the second surface of the substrate 133 . The first electrode 131 is electrically connected to a pad 134 and is led out through a bonding wire, so that the first chip 11 is electrically connected to the first electrode 131 .
[0038] For example, a metal plating process can be used to form the first electrode 131 and the second electrode 132 on the surface of the substrate 133. By coating the surface of the substrate 133, the metal plating can be patterned by a manufacturing process, so that the size, position, and shape of the first electrode 131 and the second electrode 132 when used as capacitor plates can be accurately determined to facilitate signal coupling and transmission. As another optional implementation, the first electrode 131 and the second electrode 132 are electrode plates, and the electrode plates can be fixed to the surface of the substrate 133 using a non-conductive glue to form an isolation capacitor 13 provided in an embodiment of the present application. The shape and area of the first electrode 131 and the second electrode 132 can be set according to actual needs. In addition, according to different withstand voltage requirements, the insulation spacing between the first electrode 131 and the second electrode 132 can be flexibly adjusted, and the withstand voltage level of the capacitor can be improved by increasing the thickness of the insulating dielectric layer between the first electrode 131 and the second electrode 132.
[0039] The surface of the substrate 133 is provided with a pad 134 electrically connected to the electrode. Through the pad 134, the isolation capacitor 13 can be connected to the first chip 11 and the second chip 12 respectively by bonding wires to achieve signal coupling between the first chip 11 and the second chip 12. The pad 134 can be respectively provided on different sides of the surface of the substrate 133 (such as Figure 2 As shown), it can also be arranged on the same side of the surface of the substrate 133. In the case where the pads 134 are arranged on the same side of the surface of the substrate 133, for example, the pads 134 are all arranged on the first surface of the substrate 133, then, for the second electrode 132 arranged on the second surface of the substrate 133, a via hole can be arranged on the substrate 133, and the second electrode 132 can be electrically connected to a pad 134 arranged on the first surface by using a copper column.
[0040] like Figure 3 As shown, as another optional implementation, two electrodes are arranged inside the substrate 133 and are separated by a predetermined distance. According to different withstand voltage requirements, the insulation distance between the first electrode 131 and the second electrode 132 can be flexibly adjusted, and the withstand voltage level of the capacitor can be improved by increasing the thickness of the insulating dielectric layer between the first electrode 131 and the second electrode 132.
[0041] In the case where two electrodes are disposed inside the substrate 133 , each electrode may be led out to a pad 134 disposed on the surface of the substrate 133 through a metal wire.
[0042] Specifically, the first electrode 131 and the second electrode 132 are embedded in the substrate 133. By drilling holes in the substrate 133, the first electrode 131 and the second electrode 132 disposed inside the substrate 133 can be electrically connected to a pad 134 disposed on the surface of the substrate 133 using metal wires. In this way, the damage to the capacitor element caused by external factors can be reduced, and the service life of the capacitor element can be extended. In addition, the transmission delay and reflection loss of the circuit signal can be reduced, thereby improving the integrity and reliability of signal transmission.
[0043] As an optional implementation, Figure 4 As shown, the isolation capacitor 13 provided in the embodiment of the present application includes a first capacitor 135 and a second capacitor 136, and the first capacitor 135 and the second capacitor 136 respectively have two electrodes arranged at intervals, and the electrodes on the same side of the first capacitor 135 and the second capacitor 136 are located on the same plane. The signal modulation circuit 111 includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal are respectively connected to the first side electrodes of the first capacitor 135 and the second capacitor 136 through leads. The signal demodulation circuit 121 includes a first receiving terminal and a second receiving terminal, and the first receiving terminal and the second receiving terminal are respectively connected to the second side electrodes of the first capacitor 135 and the second capacitor 136 through leads.
[0044] Specifically, for the sake of convenience, in the embodiment of the present application, the capacitor formed by the first electrode 131 and the second electrode 132 is called the first capacitor 135, and the capacitor formed by the third electrode and the fourth electrode is called the second capacitor 136. The first electrode 131 and the third electrode are arranged on the first side (i.e., the first surface) of the substrate 133, and the second electrode 132 and the fourth electrode are arranged on the second side (i.e., the second surface) of the substrate 133. The first capacitor 135 and the second capacitor 136 can constitute a differential capacitor pair. When the first chip 11 outputs a differential carrier signal, the corresponding differential carrier signal is transmitted to the second chip 12 through the differential capacitor pair; when the second chip 12 detects the differential carrier signal, it is decoded and processed and output by the signal demodulation circuit 121. The first capacitor 135 and the second capacitor 136 constitute a differential capacitor pair, and the sizes of the first capacitor 135 and the second capacitor 136 are as close as possible, so that the differential mode signal can be maintained and the common mode signal will be suppressed.
[0045] As another optional implementation, a shielding protection layer 137 is provided outside the isolation capacitor 13 , and the shielding protection layer 137 at least covers two electrodes of the isolation capacitor 13 .
[0046] Specifically, Figure 5As shown, it shows a schematic diagram of the structure of a substrate 133 type high-voltage capacitor with a shielding protective layer 137. The electrodes constituting the capacitor are embedded in the substrate 133, and a shielding protective layer 137 is provided on the surface of the substrate 133 substantially parallel to the electrodes. It is easy to understand that the electrodes arranged inside the substrate 133 can be electrically connected to a pad 134 arranged on the surface of the substrate 133 by punching holes in the substrate 133 and using metal wires. The upper and lower shielding protective layers 137 can be connected by punching holes in the substrate 133 using copper pillars. The shielding protective layer 137 is made of metal material, which can shield electric field interference and improve the stability and anti-interference ability of the circuit.
[0047] As an optional implementation, the two electrodes of the isolation capacitor 13 are arranged inside the substrate 133, the shielding protection layer 137 is arranged on the surface of the substrate 133, and the area projected by the shielding protection layer 137 on the corresponding electrode is at least larger than the area of the corresponding electrode.
[0048] Specifically, the shielding protective layer 137 can completely cover the electrode, thereby ensuring that the shielding protective layer 137 can shield the capacitor from interference from the external electric field, thereby improving the stability and anti-interference ability of the circuit.
[0049] As an optional implementation method, in an embodiment of the present application, the spacing between any shielding protective layer and any capacitor plate is greater than the spacing between two electrodes that constitute the capacitor (for example, the spacing between the upper shielding protective layer and the upper electrode plate is greater than the spacing between the two electrodes that constitute the capacitor, and the spacing between the lower shielding protective layer and the lower electrode plate is greater than the spacing between the two electrodes that constitute the capacitor), thereby reducing the parasitic capacitance between the high-voltage isolation capacitor and the reference ground.
[0050] like Figure 6 As shown, the present application also provides a capacitively coupled digital isolator 100 with a shielding protection layer 137, Figure 4 The isolation capacitor 13 is similar to the isolation capacitor 13 provided, and the isolation capacitor 13 includes a first capacitor 135 and a second capacitor 136, and the first capacitor 135 and the second capacitor 136 respectively have two electrodes arranged at intervals, and the electrodes on the same side of the first capacitor 135 and the second capacitor 136 are located on the same plane. The signal modulation circuit 111 includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal are respectively connected to the first side electrodes of the first capacitor 135 and the second capacitor 136 through leads. The signal demodulation circuit 121 includes a first receiving terminal and a second receiving terminal, and the first receiving terminal and the second receiving terminal are respectively connected to the second side electrodes of the first capacitor 135 and the second capacitor 136 through leads.
[0051] In addition, the isolation capacitor 13 also includes a shielding protective layer 137 covering the first capacitor 135 and the second capacitor 136. The shielding protective layer 137 is arranged on the surface of the substrate 133 substantially parallel to the electrode, and the upper and lower shielding protective layers 137 are connected by punching holes in the substrate 133 using copper pillars. The shielding protective layer 137 is made of metal and can shield electric field interference. A pad 134 electrically connected to the shielding protective layer 137 is also provided on the surface of the substrate 133. The pad 134 electrically connected to the shielding protective layer 137 is connected to the reference ground of the first chip 11 through a bonding wire, thereby realizing electric field shielding of the isolation capacitor 13 and improving the anti-interference ability of the circuit.
[0052] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application.
Claims
1. A capacitively coupled digital isolator, characterized in that: include: A first chip is arranged on a first substrate and has a signal modulation circuit thereon; A second chip is arranged on the second substrate and has a signal demodulation circuit thereon; An isolation capacitor is an independent device, and is electrically connected to the first chip and the second chip through leads, wherein the isolation capacitor comprises two electrodes arranged at intervals and a substrate on which the two electrodes are placed.
2. The capacitively coupled digital isolator according to claim 1, characterized in that: The two electrodes at least include an overlapping area on the same projection plane, and the portion of the substrate sandwiched between the two electrodes constitutes a dielectric layer of the capacitor.
3. The capacitively coupled digital isolator according to claim 2, characterized in that: The two electrodes are respectively disposed on the opposite first surface and second surface of the substrate.
4. The capacitively coupled digital isolator according to claim 3, characterized in that: A pad electrically connected to the electrode is provided on the surface of the substrate on at least one side of the electrode.
5. The capacitively coupled digital isolator according to claim 2, characterized in that: The two electrodes are arranged inside the substrate and are spaced apart by a predetermined distance.
6. The capacitively coupled digital isolator according to claim 5, characterized in that: Each of the electrodes is led out to a pad arranged on the surface of the substrate through a metal wire.
7. The capacitively coupled digital isolator according to claim 1, characterized in that: The isolation capacitor includes a first capacitor and a second capacitor. The first capacitor and the second capacitor respectively have two electrodes arranged at an interval, and the electrodes on the same side of the first capacitor and the second capacitor are located on the same plane.
8. The capacitively coupled digital isolator according to claim 7, characterized in that: The signal modulation circuit includes a first output terminal and a second output terminal, and the first output terminal and the second output terminal are respectively connected to first side electrodes of the first capacitor and the second capacitor through leads.
9. The capacitively coupled digital isolator according to claim 7, characterized in that: The signal demodulation circuit includes a first receiving end and a second receiving end, and the first receiving end and the second receiving end are connected to the second side electrodes of the first capacitor and the second capacitor through leads, respectively.
10. The capacitively coupled digital isolator according to claim 1, characterized in that: The substrate is made of one or a combination of glass, glass fiber epoxy resin, polyimide or polytetrafluoroethylene.
11. The capacitively coupled digital isolator according to claim 1, characterized in that: A shielding protection layer is disposed outside the isolation capacitor, and the shielding protection layer at least covers two electrodes of the isolation capacitor.
12. The capacitively coupled digital isolator according to claim 11, characterized in that: The two electrodes of the isolation capacitor are arranged inside the substrate, the shielding protection layer is arranged on the surface of the substrate, and the area of the shielding protection layer projected on the corresponding electrode is at least larger than the area of the corresponding electrode.