SOC chip based on system-in-package technology
By adopting system-level packaging technology and efficient soldering technology in SOC chips, integrating a variety of chips and inductors, the problems of large size and high power consumption in the existing technology are solved, and a smaller and more efficient SOC chip design is achieved.
Patent Information
- Application Number
- CN202520391581.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2035-03-07
AI Technical Summary
It is difficult to develop a SOC chip with small size, low power consumption and high cost performance, especially in system-level packaging technology.
The SOC chip design based on system-level packaging technology is adopted, including FPGA chips, MCU chips, power chips, inductors and FLASH chips. It is equipped with efficiently through flip-fit welding technology and pressure welding technology to achieve compactness and efficient synergy of the chips.
The SOC chip size has been reduced by more than 80%, reducing the risk of connection loosening caused by electromagnetic interference and mechanical vibration, improving system functions and reliability, and reducing overall power consumption through precise power management.
Smart Images
Figure CN222885078U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of SOC chips, in particular to a SOC chip based on system-level packaging technology. Background Art
[0002] At present, electronic systems are gradually developing towards miniaturization, high performance and multi-functions. The system-in-package (SiP) technology of power sealing with field programmable gate array (FPGA) and microcontroller unit (MCU) has become a research hotspot. Based on this technology, how to develop a SOC chip (system-on-chip) with small size, low power consumption and high cost performance has become a major issue to be solved in the industry. Utility Model Content
[0003] The purpose of the utility model is to provide a SOC chip based on system-level packaging technology to solve at least one of the above technical problems existing in the prior art.
[0004] In order to solve the above technical problems, the utility model provides a SOC chip based on system-level packaging technology, which mainly includes internal components and a substrate; the internal components include an FPGA chip, an MCU chip, a power chip, an inductor and a FLASH (flash memory) chip;
[0005] The substrate is divided into four layers from top to bottom, namely a top wiring layer, a ground layer, a power supply layer and a bottom wiring layer;
[0006] The top wiring layer is used for signal interconnection between various internal components; at one end of the top wiring layer, a power chip, an inductor and a FLASH chip are arranged flatly, and at the other end, an MCU chip and an FPGA chip are arranged in a stacked manner;
[0007] The functional area of the power chip faces the substrate and is fixed to the first preset pad of the top wiring layer by welding through a ball grid array (BGA), so that the flip chip technology can be used for efficient mounting and the size of the power chip can be significantly reduced;
[0008] The inductor is directly welded and fixed on the preset pad of the top wiring layer;
[0009] The FLASH chip is fixed to the first preset solder joint of the top wiring layer by welding with a metal wire, so that it can be fixed by using a wire bonding technology;
[0010] The functional area of the MCU chip faces the substrate and is fixed to the second preset pad of the top wiring layer by welding through a ball grid array; the surface of the non-functional area of the MCU chip is insulated;
[0011] The area of the FPGA chip is larger than that of the MCU chip; the FPGA chip is located above the MCU chip and is fixed to the second preset solder joints of the top wiring layer by welding with metal wires; the second preset solder joints are evenly distributed around the second preset solder pads;
[0012] In this way, the double-layer layout method of stacking two chips can significantly save the layout area. In addition, during the manufacturing process, the MCU chip is first mounted by flip-chip welding technology to obtain a stable wafer-level chip scale package (WLCSP) piece, and then the FPGA chip is fixed by pressure welding technology, avoiding the tedious process of temporarily positioning the upper chip by padding the silicon wafer during welding in the traditional double-layer pressure welding process, thereby significantly improving the welding efficiency and quality;
[0013] An external ball grid array is provided outside the bottom wiring layer and is connected to the top wiring layer through a signal line, so that the SOC chip can be soldered to the external electronic system through the flip-chip soldering technology, thereby connecting with the external electronic system to realize the chip function; the soldering temperature of the solder balls in the external ball grid array is lower than the melting point temperature of various solder materials inside the SOC chip, so that as long as the chip mounting process temperature is controlled when the SOC chip is externally mounted, the solder joints inside the SOC chip will not melt, thereby avoiding quality problems such as open soldering.
[0014] In a feasible implementation manner, the solder balls in the external ball grid array are specifically solder balls with a soldering temperature of approximately 230° C.; and the solder balls inside the SOC chip are specifically solder balls with a melting point temperature of approximately 350° C.
[0015] In a feasible implementation manner, the FPGA chip adopts wafer-level packaging (WLP) to reduce the board layout area and improve the performance of the SOC chip.
[0016] In a feasible implementation, the MCU chip is packaged in WLCSP level packaging to reduce the board area occupied and improve the performance of the SOC chip.
[0017] In a feasible implementation, the MCU chip includes an ADC converter (analog-to-digital converter) and a DAC converter (digital-to-analog converter); the ADC converter adopts wafer-level packaging and has 8 channels; the DAC converter has 4 channels.
[0018] In a feasible implementation, the power chip is packaged in WLCSP level packaging to reduce the board area occupied and improve the performance of the SOC chip.
[0019] By adopting the above technical solution, the utility model has the following beneficial effects:
[0020] The utility model provides a SOC chip based on system-level packaging technology, which can reduce the overall size by more than 80% compared with the traditional printed circuit (PCB) board-level design, greatly reducing the volume of the SOC chip; the solution uses a multi-chip package design to enable the internal chips to work more efficiently together, wherein the MCU chip can focus on functions such as signal acquisition and conversion, and the FPGA chip can perform complex processing and calculations on these signals according to preset logic, thereby giving full play to the advantages of each internal chip and realizing more powerful system functions; the solution reduces the number of external connections between chips, reduces the risk of loose connections or poor contact caused by factors such as electromagnetic interference and mechanical vibration, and is beneficial to the working reliability and stability in harsh working conditions; the solution introduces a power chip in the package design, making the power management more accurate and efficient, and can dynamically allocate electric energy according to the actual working status and power consumption requirements of each internal chip, avoiding unnecessary energy waste, reducing the overall power consumption of the system (specifically up to 700mW or less), which is beneficial to extending the battery life of the external battery in high power consumption conditions. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0022] Figure 1 A three-dimensional diagram of the internal structure of a SOC chip based on system-level packaging technology provided by an embodiment of the utility model;
[0023] Figure 2 for Figure 1 Another angle view of
[0024] Figure 3 A front view of the appearance of a SOC chip based on system-level packaging technology provided by an embodiment of the utility model;
[0025] Figure 4 A schematic diagram of basic signal wiring of a SOC chip based on system-level packaging technology provided by an embodiment of the utility model;
[0026] Reference numerals:
[0027] 1-substrate; 2-FPGA chip; 3-MCU chip; 4-power chip; 5-inductor; 6-FLASH chip; 7-external ball grid array. DETAILED DESCRIPTION
[0028] The technical solution of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0029] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0030] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0031] The present invention will be further explained below in conjunction with specific implementation methods.
[0032] Embodiment 1:
[0033] like Figure 1-3 As shown, a SOC chip based on system-level packaging technology provided in this embodiment mainly includes internal components and a substrate 1; the internal components include an FPGA chip 2, an MCU chip 3, a power chip 4, an inductor 5 and a FLASH chip 6;
[0034] The substrate 1 is divided into four layers from top to bottom, namely, a top wiring layer, a ground layer, a power supply layer, and a bottom wiring layer;
[0035] The top wiring layer is used for signal interconnection between various internal components; at one end of the top wiring layer, a power chip 4, an inductor 5 and a FLASH chip 6 are arranged flatly, and at the other end, an MCU chip 3 and an FPGA chip 2 are arranged in a stacked manner;
[0036] The functional area of the power chip 4 faces the substrate 1 and is fixed to the first preset pad of the top wiring layer by welding through a ball grid array (BGA), so that the flip chip technology can be used for efficient mounting and the size of the power chip can be significantly reduced;
[0037] The inductor 5 is directly welded and fixed on the preset pad of the top wiring layer;
[0038] The FLASH chip 6 is fixed to the first preset solder joint of the top wiring layer by welding with a metal wire, so that it can be fixed by using a wire bonding technology;
[0039] The functional area of the MCU chip 3 faces the substrate 1 and is fixed to the second preset pad of the top wiring layer by welding through a ball grid array; the surface of the non-functional area of the MCU chip 3 is insulated;
[0040] The area of the FPGA chip 2 is larger than that of the MCU chip 3; the FPGA chip 2 is arranged above the MCU chip 3 and is fixed to the second preset solder joints of the top wiring layer by welding with metal wires; the second preset solder joints are evenly distributed around the second preset solder pads;
[0041] In this way, the double-layer layout method of stacking two chips (inverted pyramid) can significantly save the area occupied by the board. In addition, during the manufacturing process, the MCU chip 3 is first mounted by flip-chip welding technology to obtain a stable wafer-level chip scale package (WLCSP) piece. When welding the FPGA chip 2, a bare mold can be directly placed on the insulating surface (such as the surface of the plastic packaging material) of the MCU chip 3 for pressure welding, avoiding the process of placing a silicon wafer (for insulation, positioning, and preventing wire crossing, etc.) on the lower wafer when welding the upper chip in the traditional double-layer pressure welding process, thereby reducing the thickness of the SOC chip, shortening the pressure welding wire length of the FPGA chip 2, and effectively reducing the risk of wire collapse, thereby significantly improving welding efficiency, quality and cost;
[0042] An external ball grid array 7 is provided outside the bottom wiring layer and is connected to the top wiring layer through a signal line, so that the SOC chip can be soldered to the external electronic system through the flip-chip soldering technology, thereby connecting with the external electronic system to realize the chip function; the soldering temperature of the solder balls in the external ball grid array 7 is lower than the melting point temperature of various solder materials inside the SOC chip, so that as long as the chip mounting process temperature is controlled when the SOC chip is externally mounted, the solder joints inside the SOC chip will not melt, thereby avoiding quality problems such as open soldering.
[0043] Furthermore, the solder balls in the external ball grid array 7 are specifically solder balls with a soldering temperature of about 230° C.; and the solder balls inside the SOC chip are specifically solder balls with a melting point temperature of about 350° C.
[0044] Furthermore, the SOC chip further comprises a housing, which is arranged on a side of the substrate 1 away from the external ball grid array 7 and is used to protect internal components of the SOC chip.
[0045] Furthermore, the FPGA chip 2 adopts wafer-level packaging (WLP) to reduce the board area occupied and improve the performance of the SOC chip.
[0046] Preferably, the model of the FPGA chip 2 is EQ6HL9 (Zhongke Yihaiwei Company), and the specific parameters include: 40nm CMOS integrated circuit manufacturing process; 86400 4-input basic logic units (LUTs); 64 4.5Kbit on-chip storage units; 16 multipliers; and a built-in high-speed clock manager.
[0047] Furthermore, the MCU chip 3 adopts WLCSP level packaging to reduce the board area occupied and improve the performance of the SOC chip.
[0048] Furthermore, the MCU chip 3 includes an ADC converter (analog-to-digital converter) and a DAC converter (digital-to-analog converter); the ADC converter adopts wafer-level packaging and has 8 channels; the DAC converter has 4 channels.
[0049] Preferably, the model of the MCU chip 3 is LH32M3E46, and the specific parameters include: 32-bit ARM processor; maximum 72MHz operating frequency; 16 external interrupts; 4 analog comparators; 2.5V on-chip reference voltage; 4 general 16-bit timers; 3 SPI interfaces; 1 UART interface; 3 I2C interfaces; built-in temperature sensor.
[0050] Furthermore, the model of the FLASH chip 6 is 25Q40GW.
[0051] Furthermore, the power chip 4 adopts WLCSP level packaging to reduce the board area occupied and improve the performance of the SOC chip.
[0052] Preferably, the model of the power chip 4 is RK860, and the specific parameters include: input voltage 3.3V; output voltage 1.1V; output current 7A.
[0053] Furthermore, the model of the inductor 5 is FTC141207SR24MBCA.
[0054] Furthermore, the model of the substrate 1 is HL832NKA.
[0055] Furthermore, the length and width of the substrate 1 are 8 mm*8 mm to meet the miniaturization requirements.
[0056] Furthermore, if Figure 4 As shown, the GPIO pin of the MCU chip 3 is electrically connected to the EN pin (enable pin) of the power chip 4, so as to control the power output of the power chip 4;
[0057] The voltage selection (VSEL) output pin of the MCU chip 3 is electrically connected to the voltage selection input pin of the power chip 4, and is used to select the voltage selection register of the power chip 4: when the voltage selection register is set to a high level, the voltage selection register address is 0x00; otherwise, the voltage selection register address is 0x01; thus, by writing different values in the voltage selection register, different voltage values can be output;
[0058] The serial configuration pin of the FPGA chip 2 is electrically connected to the I2C pin of the power chip 4, and is used to configure the default register of the power chip 4; the power chip 4 can be used as a slave, and the FPGA chip 2 or the MCU chip 3 can be used as a host;
[0059] The SPI1 pin, SPI2 pin and SPI3 pin of the FPGA chip 2 are electrically connected to the SPI1 pin, SPI2 pin and SPI3 pin of the MCU chip 3 respectively, and are used for serial communication: the SPI1 channel and the SPI2 channel are used as transmission channels of the ADC converter to transmit ADC sampling data (16 bits, the SPI1 channel transmits the upper eight bits, and the SPI2 channel transmits the lower eight bits) to the FPGA chip 2; the SPI3 channel is used for SPI protocol data interaction between the FPGA chip 2 and the MCU chip 3, such as serial port receiving and sending data, 1553B data, temperature information and coordinate information, etc.;
[0060] The ADC_CNV control signal output pin of the FPGA chip 2 is electrically connected to the ADC_CNV control signal input pin of the MCU chip 3, so as to drive the MCU chip 3 to perform ADC sampling; the ADC_DONE signal output pin of the MCU chip 3 is electrically connected to the ADC_DONE signal input pin of the FPGA chip 2, so as to inform the FPGA chip 2 that the ADC data transmission has been completed;
[0061] The QSPI pin of the FPGA chip 2 is electrically connected to the QSPI pin of the FLASH chip 6, so as to quickly start the FPGA chip 2 (i.e., the FPGA chip 2 completes program loading);
[0062] The inductor 5 is used for (smoothing) filtering, and together with the power chip 4 and external resistors and capacitors, forms a BUCK circuit (step-down chopper) for converting the external input voltage (3.3V) into the operating voltage (1.1V) of the FPGA chip 2.
[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.
Claims
1. A SOC chip based on system-level packaging technology, characterized in that: It includes internal components and a substrate; the internal components include an FPGA chip, an MCU chip, a power chip, an inductor and a FLASH chip; The substrate is divided into four layers from top to bottom, namely a top wiring layer, a ground layer, a power supply layer and a bottom wiring layer; The top wiring layer is used for signal interconnection between various internal components; at one end of the top wiring layer, a power chip, an inductor and a FLASH chip are arranged flatly, and at the other end, an MCU chip and an FPGA chip are arranged in a stacked manner; The functional area of the power chip faces the substrate and is fixed to the first preset pad of the top wiring layer by welding through a ball grid array; The inductor is directly welded and fixed on the preset pad of the top wiring layer; The FLASH chip is fixed to the first preset solder joint of the top wiring layer by welding through a metal wire; The functional area of the MCU chip faces the substrate and is fixed to the second preset pad of the top wiring layer by welding through a ball grid array; the surface of the non-functional area of the MCU chip is insulated; The area of the FPGA chip is larger than that of the MCU chip; the FPGA chip is located above the MCU chip and is fixed to the second preset solder joints of the top wiring layer by welding with metal wires; the second preset solder joints are evenly distributed around the second preset solder pads; An external ball grid array is arranged outside the bottom wiring layer and is connected to the top wiring layer through a signal line; the welding temperature of the solder balls in the external ball grid array is lower than the melting point temperature of various solder materials inside the SOC chip.
2. The SOC chip according to claim 1, characterized in that: The solder balls in the external ball grid array are specifically solder balls with a soldering temperature below 230° C.; the solder balls inside the SOC chip are specifically solder balls with a melting point temperature above 350° C.
3. The SOC chip according to claim 1, characterized in that: The MCU chip includes an analog-to-digital converter and a digital-to-analog converter; the number of channels of the analog-to-digital converter is 8; the number of channels of the digital-to-analog converter is 4.
4. The SOC chip according to claim 1, characterized in that: The length and width of the substrate are 8mm*8mm.
5. The SOC chip according to claim 3, characterized in that: The GPIO pin of the MCU chip is electrically connected to the EN pin of the power chip, and is used to control the power output of the power chip.
6. The SOC chip according to claim 5, characterized in that: The voltage selection output pin of the MCU chip is electrically connected to the voltage selection input pin of the power chip.
7. The SOC chip according to claim 6, characterized in that: The serial configuration pin of the FPGA chip is electrically connected to the I2C pin of the power chip, and is used to configure the default register of the power chip.
8. The SOC chip according to claim 7, characterized in that: The SPI1 pin, SPI2 pin and SPI3 pin of the FPGA chip are electrically connected to the SPI1 pin, SPI2 pin and SPI3 pin of the MCU chip respectively for serial communication: The SPI1 channel and the SPI2 channel are used as transmission channels of the analog-to-digital converter to transmit the analog-to-digital converter sampling data to the FPGA chip; The SPI3 channel is used for SPI protocol data exchange between the FPGA chip and the MCU chip.
9. The SOC chip according to claim 8, characterized in that: The ADC_CNV control signal output pin of the FPGA chip is electrically connected to the ADC_CNV control signal input pin of the MCU chip, so as to drive the MCU chip to perform analog-to-digital converter data sampling; the ADC_DONE signal output pin of the MCU chip is electrically connected to the ADC_DONE signal input pin of the FPGA chip, so as to inform the FPGA chip that the analog-to-digital converter data transmission has been completed.
10. The SOC chip according to claim 9, characterized in that: The QSPI pin of the FPGA chip is electrically connected to the QSPI pin of the FLASH chip for quickly starting the FPGA chip.