Low-on-resistance planar gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

Abstract

The utility model provides a low-on-resistance planar gate silicon carbide VDMOS. The low-on-resistance planar gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side of the current equalizing region is connected to the upper side of the drift layer; the lower side surface of the P-type source region is connected to the upper side surface of the current equalizing region; the lower side surface of the P-type well region is connected to the current equalizing region, an N-type source region is arranged in the P-type well region, and the inner side surface of the P-type source region is connected to the outer side surface of the P-type well region and the outer side surface of the N-type source region; the low-resistance channel region sequentially passes through the P-type well region and the current sharing region, and the lower side surface of the low-resistance channel region is connected to the upper side surface of the drift layer; the lower side of the insulating dielectric layer is connected with the upper side of the P-type well region and the upper side of the low-resistance channel region; the source metal layer is respectively connected with the P-type source region and the N-type source region; the gate metal layer is connected to the insulating dielectric layer; the drain metal layer is connected to the silicon carbide substrate; the on-resistance of the device is effectively reduced, and the special P-type source region also improves the body diode follow current capability of the device.

Description

Technical Field

[0001] The utility model relates to a low-on-resistance planar gate silicon carbide VDMOS. Background Art

[0002] Silicon carbide power devices are widely used in electric vehicles, aerospace, power conversion and other fields. Existing silicon carbide VDMOS can achieve low on-resistance but cannot achieve high reliability. If the reliability is improved, the on-resistance will also increase. In power electronics applications, low on-resistance and high reliability are the eternal pursuit of devices; therefore, it is urgent to provide a low on-resistance and high reliability silicon carbide VDMOS. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a low on-resistance planar gate silicon carbide VDMOS, which adopts a planar gate structure to ensure high gate reliability, and the designed low-resistance structure effectively reduces the on-resistance of the device. The special P-type source region also improves the body diode freewheeling capability of the device.

[0004] The utility model is implemented as follows: a low on-resistance planar gate silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;

[0007] A current balancing region, wherein the lower side of the current balancing region is connected to the upper side of the drift layer;

[0008] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the current balancing region;

[0009] A P-type well region, wherein the lower side of the P-type well region is connected to the current balancing region, an N-type source region is provided in the P-type well region, and the inner side of the P-type source region is connected to the outer side of the P-type well region and the outer side of the N-type source region;

[0010] A low-resistance channel region, wherein the low-resistance channel region sequentially passes through the P-type well region and the current balancing region, and the lower side of the low-resistance channel region is connected to the upper side of the drift layer;

[0011] An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is connected to the upper side of the P-type well region and the upper side of the low-resistance channel region;

[0012] A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively;

[0013] A gate metal layer connected to the insulating dielectric layer;

[0014] and a drain metal layer connected to the silicon carbide substrate.

[0015] The advantages of the utility model are:

[0016] 1. The device adopts a planar gate device structure and has the characteristics of high gate reliability;

[0017] Second, the device constructs an N-type low-resistance channel and an N-type current-balanced region to reduce the on-resistance of the device, achieving comprehensive high performance of high gate reliability and low on-resistance;

[0018] 3. The P-type source region of the device is extended from the device and source contact area to the same thickness as the P-type well region, which can reduce the body diode on-resistance of the device;

[0019] 4. The doping concentration relationship between the N-type low-resistance channel and the N-type current equalizing region of the device can extend the current from the N-type low-resistance channel to the N-type current equalizing region at the edge of the device, thereby making the current more evenly distributed in the device structure and avoiding device reliability problems caused by current concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0021] Figure 1 The utility model is a schematic diagram of a low on-resistance planar gate silicon carbide VDMOS.

[0022] Figure 2 The utility model is a flow chart of a method for preparing a low on-resistance planar gate silicon carbide VDMOS.

[0023] Figure 3 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 1 .

[0024] Figure 4 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 2 .

[0025] Figure 5 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 3 .

[0026] Figure 6 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 4 .

[0027] Figure 7 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 5 .

[0028] Figure 8 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 6 .

[0029] Fig. 9 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 7 .

[0030] Fig.10 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 8 .

[0031] Fig.11 This is a cross-sectional view of the process of a low on-resistance planar gate silicon carbide VDMOS of the utility model. Figure 9 . DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] like Figure 1 As shown, the embodiment of the present application provides a low on-resistance planar gate silicon carbide VDMOS, including:

[0038] Silicon carbide substrate 101,

[0039] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;

[0040] A current balancing region 103, wherein the lower side of the current balancing region 103 is connected to the upper side of the drift layer 102;

[0041] A P-type source region 104, wherein the lower side of the P-type source region 104 is connected to the upper side of the current balancing region 103;

[0042] A P-type well region 105, wherein the lower side of the P-type well region 105 is connected to the current balancing region 103, an N-type source region 1051 is provided in the P-type well region 105, and the inner side of the P-type source region 104 is connected to the outer side of the P-type well region 105 and the outer side of the N-type source region 1051;

[0043] A low-resistance channel region 106, wherein the low-resistance channel region 106 sequentially passes through the P-type well region 105 and the current balancing region 103, and the lower side of the low-resistance channel region 106 is connected to the upper side of the drift layer 102;

[0044] An insulating dielectric layer 107, wherein the lower side of the insulating dielectric layer 107 is connected to the upper side of the P-type well region 105 and the upper side of the low-resistance channel region 106;

[0045] A source metal layer 108 , wherein the source metal layer 108 is connected to the P-type source region 104 and the N-type source region 1051 ;

[0046] A gate metal layer 109 , wherein the gate metal layer 109 is connected to the insulating dielectric layer 107 ;

[0047] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the silicon carbide substrate 101 .

[0048] like Figures 2 to 11 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0049] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing on the silicon carbide substrate 101 to form a drift layer 102;

[0050] Step 2: forming a barrier layer a on the upper part of the drift layer 102, etching the barrier layer a to form a through hole, and forming a current equalizing region 103 in the drift layer 102 by ion implantation, wherein the ion implantation energy is 200-300 kev;

[0051] Step 3, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and forming a P-type well region 105 in the drift layer 102 by ion implantation, with the ion implantation energy being 10-200kev;

[0052] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and form a P-type source region 104 in the drift layer 102 by ion implantation, with the ion implantation energy being 10-200kev;

[0053] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and form an N-type source region 1051 in the P-type well region 105 by ion implantation, with the ion implantation energy being 10-100 keV;

[0054] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and form a low-resistance channel region 106 in the drift layer 102 by ion implantation, with the ion implantation energy being 10-300kev;

[0055] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and depositing to form an insulating dielectric layer 107;

[0056] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 109;

[0057] Step 9: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form a source metal layer 108, remove the barrier layer a, and complete the preparation.

[0058] The doping concentration of the silicon carbide substrate 101 is 2e18cm -3 The doping concentration of the drift layer 102 is 2e17cm -3 The doping concentration of the current balancing region 103 is 1e18 cm -3 The doping concentration of the low resistance channel region 106 is 6e17cm -3 The doping concentration of the P-type source region 104 is 2e18cm -3 The doping concentration of the P-type well region 105 is 1e17 cm -3 The doping concentration of the N-type source region 1051 is 2e18cm -3 ; The insulating dielectric layer 107 is silicon dioxide; the gate metal layer 109, the source metal layer 108 and the drain metal 110 are all Al. The silicon carbide substrate 101 is N-type, and the thickness of the silicon carbide substrate 101 is 1μm; the drift layer 102 is N-type, and the thickness of the drift layer 102 is 10-20μm, the current equalizing region 103 is N-type, and the thickness of the current equalizing region 103 is 300nm, the low-resistance channel region 106 is N-type, and the thickness of the low-resistance channel region 106 is 900nm; the thickness of the P-type source region 104 is 600nm, the thickness of the N-type source region 1051 is 300nm, the thickness of the P-type well region 105 is 600nm, the thickness of the source metal layer 108 is 300nm, the thickness of the insulating dielectric layer 107 is 20nm, the thickness of the gate metal layer 109 is 280nm, and the device withstand voltage is 800-1200V;

[0059] The concentration of the N-type silicon carbide substrate 101 is to form a low-resistance ohmic contact with the drain metal layer 110 to reduce the on-resistance of the device. Its thickness is based on the design conditions of the device epitaxial thickness (N-type drift layer 102) to ensure support and improve process stability. The thickness and doping concentration of the N-type drift layer 102 are a compromise between on-resistance and withstand voltage. The P-type source region 104 is designed to reduce the on-resistance of the device body diode and improve the freewheeling capability of the body diode. The N-type equalizing current region 103 and the N-type low-resistance channel region 106 are designed to reduce the on-resistance of the device. Their concentration, thickness and position relationship are to achieve the electrons from the N-type source region 1051 entering the N-type low-resistance channel region 106 through the inverted P-type well region 105. When entering the N-type equalizing current region 103, the lateral resistance value is smaller and the lateral diffusion of the current is larger, so as to avoid the current from being concentrated in the middle area of ​​the device and improve the reliability of the device. The gate design is to ensure the gate control capability of the device.

[0060] When the device is turned off, the gate is at zero voltage, the drain is under high voltage, and the space charge region constructed by the N-type drift layer 102, the P-type well region 105 and the P-type source region 104 is under high voltage. When the device is turned on, the source is connected to a relatively high potential (about 0.1V) gate and a positive voltage is applied. The P-type well region 105 directly below the gate (the side of the P-type well region 105 where the N-type source region 1051 is close to the N-type low-resistance channel region 106) is inverted, forming a channel from the N-type source region 1051 to the N-type low-resistance channel region 106. Electron channel, electrons diffuse from the N-type source region 1051 through the inverted P-type well region 105 to the N-type low-resistance channel region 106 to the N-type current sharing region 103. In the N-type current sharing region 103, the device conductive channel is a whole lateral structure. When no positive voltage is applied to the device gate and a positive voltage is applied to the source, the pn junction diode composed of the source metal layer 108-P-type source region 104-N-type current sharing region 103-N-type drift layer 102-N-type silicon carbide substrate 101-drain metal layer 110 continues current.

[0061] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A low on-resistance planar gate silicon carbide VDMOS, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A current balancing region, wherein the lower side of the current balancing region is connected to the upper side of the drift layer; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the current balancing region; A P-type well region, wherein the lower side of the P-type well region is connected to the current balancing region, an N-type source region is provided in the P-type well region, and the inner side of the P-type source region is connected to the outer side of the P-type well region and the outer side of the N-type source region; A low-resistance channel region, wherein the low-resistance channel region sequentially passes through the P-type well region and the current balancing region, and the lower side of the low-resistance channel region is connected to the upper side of the drift layer; An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is connected to the upper side of the P-type well region and the upper side of the low-resistance channel region; A source metal layer, the source metal layer is connected to the P-type source region and the N-type source region respectively; A gate metal layer connected to the insulating dielectric layer; and a drain metal layer connected to the silicon carbide substrate.

2. A low on-resistance planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the flow-averaging region is 300 nm.

3. A low on-resistance planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the low resistance channel region is 900 nm.

4. A low on-resistance planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating dielectric layer is 20 nm.

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