Switching circuit, chip and electronic equipment
By adding a drive module and clamp module to the switching module of the switching circuit, the performance degradation caused by high on-impedance and parasitic capacitance is solved, and lower on-resistance and more stable current is achieved.
Patent Information
- Application Number
- CN202421358314.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-13
- Publication Date
- 2025-05-20
- Estimated Expiration
- 2034-06-13
AI Technical Summary
The switching circuit has a high on-impedance and parasitic capacitance when on-conducting, resulting in a degradation in performance.
A switching circuit is designed to increase the driving capability to the control terminal by adding a first drive module between the first end and the control terminal of the switch module, and reduce the on-resistance. At the same time, a first clamping module is provided at the control end of the switch module to avoid the potential being coupled to the high voltage, ensure that the output voltage of the drive module rises normally, and avoid current spikes.
It effectively reduces the on-resistance of the switching circuit, improves the performance degradation caused by parasitic capacitance, and improves the overall performance.
Smart Images
Figure CN222888076U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of electronic circuits, and particularly relates to a switching circuit, a chip, and an electronic device. Background Art
[0002] A switching circuit is an electronic circuit, usually composed of some electrical components, and is used to control the on / off of the loop where it is located.
[0003] However, since the switching circuit is composed of some electrical components, there will inevitably be a corresponding on-resistance when it is conducting; and due to the parasitic capacitance caused by the electrical components, the performance of the switching circuit will be reduced. Summary of the Utility Model
[0004] In view of the above problems, embodiments of this application provide a switching circuit, a chip, and an electronic device to alleviate the technical problems of high on-resistance and performance degradation caused by parasitic capacitance.
[0005] In a first aspect, an embodiment of this application provides a switching circuit, which includes a switching module, a first driving module, and a first clamping module. The first end of the switching module is the input end of the switching circuit, and the second end of the switching module is the output end of the switching circuit; the input end of the first driving module is connected to the first end of the switching module, and the output end of the first driving module is connected to the control end of the switching module; the first clamping module is connected between the control end of the switching module and the ground terminal.
[0006] In a second aspect, an embodiment of this application further provides a chip, which includes the above-mentioned switching circuit.
[0007] In a third aspect, an embodiment of this application further provides an electronic device, which includes a device main body and the above-mentioned chip or switching circuit provided on the device main body.
[0008] The switching circuit, chip, and electronic device provided by the embodiments of this application can improve the driving ability of the control end of the switching module by adding a first driving module between the first end and the control end of the switching module, thereby reducing the on-resistance of the switching module, and further reducing the on-resistance of the switching circuit; when a high voltage is coupled to the control end of the switching module through the parasitic capacitance at the second end of the switching module, the first clamping module provided at the control end of the switching module can be used to prevent the potential of the control end of the switching module from being coupled to the high voltage, so that the output voltage of the first driving module can be normally lifted, thereby avoiding the occurrence of a current spike flowing through the switching module, and further improving the performance degradation problem caused by parasitic capacitance.
[0009] These aspects or other aspects of this application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0011] Figure 1 Shows the first principle block diagram of the switching circuit provided by the embodiment of the present application.
[0012] Figure 2 Shows the first circuit schematic diagram of the switching module.
[0013] Figure 3 Shows the second circuit schematic diagram of the switching module.
[0014] Figure 4 Shows the second principle block diagram of the switching circuit provided by the embodiment of the present application.
[0015] Figure 5 Shows the circuit schematic diagram of the second clamping module.
[0016] Figure 6 Shows the third principle block diagram of the switching circuit provided by the embodiment of the present application.
[0017] Figure 7 Shows the principle block diagram of the current limiting module.
[0018] Figure 8 Shows the circuit schematic diagram of the current limiting module.
[0019] Figure 9 Shows the fourth principle block diagram of the switching circuit provided by the embodiment of the present application.
[0020] Figure 10 Shows the principle block diagram of the switching module.
[0021] Figure 11 Shows the circuit schematic diagram of the switching module.
[0022] Figure 12 Shows the principle block diagram of the first driving module.
[0023] Figure 13 Shows the principle block diagram of the first clamping module.
[0024] Figure 14 Shows the circuit schematic diagram of the first clamping module.
[0025] Figure 15The circuit schematic diagram of the switching circuit provided by the embodiment of the present application is shown.
[0026] Figure 16 The structural diagram of the chip provided by the embodiment of the present application is shown.
[0027] Figure 17 The first principle block diagram of the chip provided by the embodiment of the present application is shown.
[0028] Figure 18 The second principle block diagram of the chip provided by the embodiment of the present application is shown.
[0029] Figure 19 The principle block diagram of the protection module is shown.
[0030] Figure 20 The principle block diagram of the logic processing module is shown.
[0031] Figure 21 The circuit schematic diagram of the logic processing module is shown.
[0032] Figure 22 The structural diagram of the electronic device provided by the embodiment of the present application is shown.
[0033] Figure 23 The circuit schematic diagram of the electronic device provided by the embodiment of the present application is shown. Detailed implementation manners
[0034] The following details the implementation manners of the present application. The examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below by referring to the accompanying drawings are exemplary only for explaining the present application and should not be construed as a limitation to the present application.
[0035] In order to enable those skilled in the art of the present technology to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.
[0036] In the embodiments of the present application, it should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0037] Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.
[0038] In the description of the embodiments of the present application, words such as "example" or "for example" are used to give examples, explanations or descriptions. Any embodiment or design described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0039] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and there is no limitation on which ones are included. For example, including at least one of A, B and C, then what is included can be A, B, C, A and B, A and C, B and C, or A, B and C.
[0040] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the front and rear associated objects.
[0041] It should be pointed out that "connection" in the embodiments of the present application can be understood as electrical connection. The connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0042] In the embodiments of the present application, the first pole / first end of each transistor is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetric in structure, there may be no difference between the source and the drain in structure. That is to say, there may be no difference between the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application in structure. Exemplarily, when the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; Exemplarily, when the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.
[0043] In the circuit structure provided by the embodiments of the present application, nodes such as the first node and the second node do not represent actually existing components, but represent the convergence points of relevant couplings in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.
[0044] Figure 1 Fig. 1 shows a first principle block diagram of a switching circuit 100 provided by an embodiment of the present application. The switching circuit 100 includes a switching module 10, a first driving module 20, and a first clamping module 30. By adding the first driving module 20 between the first end and the control end of the switching module 10, the driving ability of the control end of the switching module 10 can be improved, thereby reducing the on-resistance of the switching module 10, and further reducing the on-resistance of the switching circuit 100; When a high voltage is coupled to the control end of the switching module 10 through the parasitic capacitance at the second end of the switching module 10, the first clamping module 30 provided at the control end of the switching module 10 can be used to prevent the potential of the control end of the switching module 10 from being coupled to the high voltage, so that the output voltage of the first driving module 20 can be normally lifted, thereby avoiding the current flowing through the switching module 10 from having a spike, and further improving the performance degradation problem caused by the parasitic capacitance.
[0045] An embodiment of the present application provides a switching circuit 100. Please refer to Figures 1 to 15 , as Figure 1 shown, the switching circuit 100 includes a switching module 10, a first driving module 20, and a first clamping module 30. The first end of the switching module 10 is the input terminal (VIN) of the switching circuit 100, and the second end of the switching module 10 is the output terminal (VOUT) of the switching circuit 100. The input end of the first driving module 20 is connected to the first end of the switching module 10, and the output end of the first driving module 20 is connected to the control end of the switching module 10. The first clamping module 30 is connected between the control end of the switching module 10 and the ground terminal GND.
[0046] It can be understood that for the switching circuit 100 provided by the embodiments of the present application, by adding a first driving module 20 between the first end and the control end of the switching module 10, the driving ability of the control end of the switching module 10 can be improved, thereby reducing the on-resistance of the switching module 10, and further reducing the on-resistance of the switching circuit 100; when a high voltage is coupled to the control end of the switching module 10 through the parasitic capacitance at the second end of the switching module 10, the first clamping module 30 provided at the control end of the switching module 10 can be used to prevent the potential of the control end of the switching module 10 from being coupled to the high voltage, so that the output voltage of the first driving module 20 can be normally lifted, thereby avoiding the current flowing through the switching module 10 from having a spike, and further improving the performance degradation problem caused by the parasitic capacitance.
[0047] In one embodiment, as Figure 2 shown, the switching module 10 includes a first transistor M1. The first pole of the first transistor M1 is the second end of the switching module 10. The second pole of the first transistor M1 is connected to the input end of the first driving module 20, and the control pole of the first transistor M1 is connected to the output end of the first driving module 20.
[0048] It should be noted that in this embodiment, the first transistor M1 can be a field effect transistor, a thin film transistor, or a bipolar junction transistor.
[0049] In one embodiment, as Figure 3 shown, the first transistor M1 is a laterally diffused metal oxide semiconductor field effect transistor. The source of the laterally diffused metal oxide semiconductor field effect transistor is connected to the input end of the first driving module 20. The gate of the laterally diffused metal oxide semiconductor field effect transistor is connected to the output end of the first driving module 20. The drain of the laterally diffused metal oxide semiconductor field effect transistor is the second end of the switching module 10. The P-type substrate (VSUB) of the laterally diffused metal oxide semiconductor field effect transistor is connected to the ground terminal GND, and the N-type buried layer (NBL) of the laterally diffused metal oxide semiconductor field effect transistor is connected to the source of the laterally diffused metal oxide semiconductor field effect transistor.
[0050] It should be noted that the laterally diffused metal oxide semiconductor field effect transistor is also called LDMOS, and its breakdown voltage parameter can be selected as needed, for example, 40V. Since the gate, source, and the substrate of the source (referred to as the source substrate) of the LDMOS cannot withstand high voltages, and there is a risk that the drain is short-circuited to a high voltage, and it will also rise to a very high voltage during large surges and electrostatic discharges (ESD), therefore, in order to improve the breakdown voltage performance of the LDMOS, in this embodiment, the source and the drain are swapped in position to make the output of the switching module 10 withstand high voltages, and the N-type buried layer is connected to the source with a higher voltage.
[0051] In one embodiment, as Figure 4 shown, the switching circuit 100 further includes a second clamping module 40. One end of the second clamping module 40 is connected to the P-well lead-out terminal (BULK) of the laterally diffused metal oxide semiconductor field effect transistor, and the other end of the second clamping module 40 is connected to the ground terminal GND.
[0052] It should be noted that for the P-well lead-out terminal, if it is directly grounded, due to the body bias effect, in order to meet the impedance requirements of the switching circuit 100, its area will be greatly increased. If it is directly connected to the drain, it may be raised to a high voltage due to short circuits, surges or ESD conditions, and the source substrate cannot withstand high voltages and will be damaged. Therefore, the second clamping module 40 is added to clamp the voltage of the P-well lead-out terminal at a lower fixed voltage under high voltage conditions, so that it can not only meet the impedance requirements of the switching circuit 100, but also does not require a larger area, and can also avoid damage to the source substrate.
[0053] In one embodiment, as Figure 5 shown, the second clamping module 40 includes a third Zener diode D1. The cathode of the third Zener diode D1 is connected to the P-well lead-out terminal of the laterally diffused metal oxide semiconductor field effect transistor and the drain of the laterally diffused metal oxide semiconductor field effect transistor, and the anode of the third Zener diode D1 is connected to the ground terminal GND.
[0054] It should be noted that the third Zener diode D1 can be a Zener diode, which can clamp the voltage of the P-well lead-out terminal at a lower fixed voltage under high voltage conditions, for example, about 5.75V.
[0055] In one embodiment, as Figure 6 shown, the switching circuit 100 further includes a current limiting module 50. The current limiting module 50 is connected to the cathode of the third Zener diode D1, the P-well lead-out terminal of the laterally diffused metal oxide semiconductor field effect transistor, and the drain of the laterally diffused metal oxide semiconductor field effect transistor.
[0056] It should be noted that the clamping function of the Zener diode fails when the current is large. Therefore, the added current limiting module 50 in this embodiment can prevent the clamping function of the third Zener diode D1 from failing.
[0057] In one embodiment, as Figure 7 shown, the current limiting module 50 includes a first current limiting unit 51 and a second current limiting unit 52. The first current limiting unit 51 is connected between the cathode of the third Zener diode D1 and the P-well lead-out terminal of the laterally diffused metal oxide semiconductor field effect transistor; the second current limiting unit 52 is connected between the cathode of the third Zener diode D1 and the drain of the laterally diffused metal oxide semiconductor field effect transistor.
[0058] It should be noted that the first current limiting unit 51 is used to limit the current flowing through the P-well lead-out terminal, and the second current limiting unit 52 is used to limit the current flowing through the drain. Thus, the current flowing through the third Zener diode D1 can be limited, thereby preventing the clamping function of the third Zener diode D1 from failing when the current is large.
[0059] In one embodiment, as Figure 8 shown, the first current limiting unit 51 includes a first resistor R1. One end of the first resistor R1 is connected to the cathode of the third Zener diode D1, and the other end of the first resistor R1 is connected to the P-well lead-out terminal of the laterally diffused metal oxide semiconductor field effect transistor; the second current limiting unit 52 includes a second resistor R2. One end of the second resistor R2 is connected to the cathode of the third Zener diode D1, and the other end of the second resistor R2 is connected to the drain of the laterally diffused metal oxide semiconductor field effect transistor.
[0060] It should be noted that in order to further reduce the high voltage risk brought by the drain, which may cause the third Zener diode D1 to withstand a large current, the resistance value of the second resistor R2 can be set to be greater than that of the first resistor R1.
[0061] In one embodiment, as Figure 9 shown, the switch circuit 100 further includes a switching module 60. The switching module 60 is connected between one end of the first current limiting unit 51 and the cathode of the third Zener diode D1.
[0062] It should be noted that when the first resistor R1 and the second resistor R2 are added, a parasitic bipolar junction transistor (BJT) will be formed between the source substrate and the drain. Since the second resistor R2 is a large resistor, a spontaneous latch-up effect may be caused due to the avalanche multiplication effect, resulting in a leakage situation. Therefore, the switching module 60 is added, which is used to switch the potential of the P-well lead-out terminal between the potential of the ground terminal GND and the cathode potential of the third Zener diode D1, which can avoid the body bias effect and improve the leakage situation.
[0063] In one embodiment, asFigure 10 As shown, the switching module 60 includes a first switching unit 61 and a second switching unit 62. The first switching unit 61 is connected between one end of the first current limiting unit 51 and the cathode of the third Zener diode D1; the second switching unit 62 is connected between one end of the first current limiting unit 51 and the ground terminal GND.
[0064] It should be noted that when the first switching unit 61 is disconnected and the second switching unit 62 is turned on, the P-type well lead-out terminal can be connected to the ground terminal GND, which can ensure that there is no leakage path. When the first switching unit 61 is turned on and the second switching unit 62 is disconnected, the P-type well lead-out terminal can be connected to the drain through the second resistor R2, which can ensure that there is no body bias effect.
[0065] In one embodiment, as Figure 11 shown, the first switching unit 61 includes a second transistor M2. The first pole of the second transistor M2 is connected to one end of the first current limiting unit 51, the second pole of the second transistor M2 is connected to the cathode of the third Zener diode D1, and the control pole of the second transistor M2 is connected to the first switch enable signal SW_EN; the second switching unit 62 includes a third transistor M3. The first pole of the third transistor M3 is connected to the ground terminal GND, the second pole of the third transistor M3 is connected to one end of the first current limiting unit 51, and the control pole of the third transistor M3 is connected to the first switch enable signal SW_EN; wherein, the channel type of the second transistor M2 is different from that of the third transistor M3.
[0066] It should be noted that since the channel types of the second transistor M2 and the third transistor M3 are different, the same first switch enable signal SW_EN can be used to control the on and off of the second transistor M2 and the third transistor M3. Among them, the second transistor M2 can be a P-channel transistor, and the third transistor M3 can be an N-channel transistor; in this embodiment, the second transistor M2 is an N-channel transistor and the third transistor M3 is a P-channel transistor for illustration.
[0067] When the first transistor M1 is turned on, the first switch enable signal SW_EN is at a high potential (enabled), the second transistor M2 is turned on, the third transistor M3 is turned off, and the P-type well lead-out terminal is connected to the second resistor R2, which can ensure no body bias effect. When the first transistor M1 is turned off, when the first switch enable signal SW_EN is at a low potential (enabled off, which may be that the VCONN function is not enabled, or is triggered to be forcibly turned off due to short circuit, overvoltage, overheating protection, etc.), the P-type well lead-out terminal is connected to the ground to ensure no leakage path.
[0068] In one embodiment, as Figure 12As shown, the first driving module 20 includes a first voltage multiplier charge pump 21 and a soft start unit 22. The input end of the first voltage multiplier charge pump 21 is connected to the first end of the switching module 10; the input end of the soft start unit 22 is connected to the output end of the first voltage multiplier charge pump 21, and the output end of the soft start unit 22 is connected to the control end of the switching module 10.
[0069] It should be noted that the first voltage multiplier charge pump 21 is used to raise the potential of the first end of the switching module 10 by several times the original, so as to increase the potential of the control end of the switching module 10, improve the driving ability of the control end of the switching module 10, and further reduce the on-resistance of the switching module 10. The soft start unit 22 is used to control the output voltage of the first driving module 20 to gradually rise, so as to control the potential of the control end of the switching module 10 to gradually rise, to prevent the current flowing through the switching module 10 from having a spike. Exemplarily, the first voltage multiplier charge pump 21 can be a voltage doubler charge pump.
[0070] In one embodiment, as Figure 13 shown, the first clamping module 30 includes a first clamping unit 31 and a second clamping unit 32. The first clamping unit 31 is connected between the control end of the switching module 10 and the ground terminal GND; the second clamping unit 32 is connected between the first clamping unit 31 and the ground terminal GND.
[0071] It should be noted that in other embodiments, the second clamping unit 32 can also be connected between the first clamping unit 31 and the control end of the switching module 10. There is a parasitic capacitance between the control end of the switching module 10 and the second end of the switching module 10. Therefore, a high voltage may be coupled to the control end of the switching module 10 through this parasitic capacitance from the second end of the switching module 10, making the output voltage of the first voltage multiplier charge pump 21 unable to rise normally. In view of this, in this embodiment, the potential of the control end of the switching module 10 is clamped by the series-connected first clamping unit 31 and second clamping unit 32, which can avoid affecting the normal rise of the output voltage of the first voltage multiplier charge pump 21.
[0072] In one embodiment, as Figure 14 shown, the first clamping unit 31 includes a first Zener diode D2, and the cathode of the first Zener diode D2 is connected to the control end of the switching module 10. The second clamping unit 32 includes a second Zener diode D3, the cathode of the second Zener diode D3 is connected to the anode of the first Zener diode D2, and the anode of the second Zener diode D3 is connected to the ground terminal GND.
[0073] It should be noted that both the first Zener diode D2 and the second Zener diode D3 are Zener diodes. By using two series-connected Zener diodes, the normal rise of the potential of the control end of the switching module 10 can be avoided from being affected by high voltage.
[0074] Figure 15 The circuit schematic diagram of the switching circuit 100 provided by the embodiment of the present application is shown. The first driving module 20 raises the source potential of the first transistor M1 to multiple times the original value and outputs a driving voltage to control the gradual rise of the gate potential of the first transistor M1. The series-connected first Zener diode D2 and second Zener diode D3 can prevent the normal rise of the gate potential from being affected when the gate potential of the first transistor M1 is at a high voltage.
[0075] The first resistor R1 and the second resistor R2 can prevent the third Zener diode D1 from failing to perform the clamping function when the current is large. The second transistor M2 and the third transistor M3 can switch the P-type well lead to be connected to the second resistor R2 or the ground terminal GND to ensure no body bias effect and no leakage. In this way, the reliability of the switching circuit 100 is improved.
[0076] In one embodiment, the embodiment of the present application further provides a chip 200, as Figure 16 shown. The chip 200 includes the above-mentioned switching circuit 100. The chip 200 is also called an integrated circuit (IC). The chip 200 can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip.
[0077] It can be understood that since the chip 200 provided by the embodiment of the present application includes the above-mentioned switching circuit 100, the driving ability of the control end of the switching module 10 can also be improved by adding the first driving module 20 between the first end and the control end of the switching module 10, so that the on-resistance of the switching module 10 can be reduced, and further the on-resistance of the switching circuit 100 can be reduced; when a high voltage is coupled to the control end of the switching module 10 through the parasitic capacitance at the second end of the switching module 10, the first clamping module 30 provided at the control end of the switching module 10 can be used to prevent the potential of the control end of the switching module 10 from being coupled to the high voltage, so that the output voltage of the first driving module 20 can be normally raised, thereby avoiding the current flowing through the switching module 10 from having a spike, and further improving the performance degradation problem caused by the parasitic capacitance.
[0078] It should be noted that the above chip 200 can be Figure 23 the physical layer integrated circuit (PHY) in
[0079] In one embodiment, as Figure 17As shown, the chip 200 further includes a system power supply terminal SYS_5V and a plurality of interface circuits 210. Each interface circuit 210 includes a first configuration channel 211 and a second configuration channel 212. Among them, a switching circuit 100 is connected between the system power supply terminal SYS_5V and the input end of the first configuration channel 211, and another switching circuit 100 is connected between the system power supply terminal SYS_5V and the input end of the second configuration channel 212.
[0080] It should be noted that in the USB Type-C PD (Power Delivery) application, each interface circuit 210 can be a Type-C interface. The first configuration channel 211 can be the CC1 channel in the Type-C interface, and the second configuration channel 212 can be the CC2 channel in the Type-C interface.
[0081] PD is an energy transfer protocol that allows for fast and efficient energy exchange between devices. In the PD application, the switching circuit 100 needs to be designed in combination with the CC channel to ensure its high reliability such as surge resistance, ESD protection, or leakage prevention.
[0082] In this embodiment, setting a plurality of interface circuits 210 can provide multiple Type-C interfaces to ensure the scalability of the device.
[0083] In one embodiment, as Figure 18 shown, the chip 200 further includes a protection module 220 and a logic processing module 230. The protection module 220 is connected to the switching circuit 100, and the logic processing module 230 is connected to the protection module 220.
[0084] It should be noted that the protection module 220 can provide electrical protection for the switching circuit 100 to further improve reliability. The logic processing module 230 can process the interrupt signal output by the protection module 220 and then output it to the control module 310 to reduce the number of pins used by the control module 310.
[0085] In one embodiment, as Figure 19 shown, the protection module 220 includes a plurality of overvoltage protection units 221, a plurality of overcurrent protection units 222, a plurality of short-circuit protection units 223, and an over-temperature protection unit 224. Each overvoltage protection unit 221 is connected to the output end of a switching circuit 100. Each overcurrent protection unit 222 is connected to a switching circuit 100. Each short-circuit protection unit 223 is connected to a switching circuit 100. The over-temperature protection unit 224 is used to provide temperature protection for the switching circuit 100.
[0086] It should be noted that the protection module 220 can perform at least one of voltage protection, current protection, and temperature protection on the switch circuit 100.
[0087] In one embodiment, as Figure 20 shown, the logic processing module 230 includes a first logic processing unit 231 and a second logic processing unit 232. The first logic processing unit 231 is connected to a plurality of overvoltage protection units 221; the second logic processing unit 232 is connected to a plurality of overcurrent protection units 222 and a plurality of short-circuit protection units 223.
[0088] It should be noted that the first logic processing unit 231 can combine a plurality of interrupt signals output by the plurality of overvoltage protection units 221 into one interrupt signal, thereby saving the number of pins used by the control module 310. The second logic processing unit 232 can combine a plurality of interrupt signals output by the plurality of overcurrent protection units 222 and the plurality of short-circuit protection units 223 into one interrupt signal, thereby saving the number of pins used by the control module 310.
[0089] In one embodiment, as Figure 21 shown, the first logic processing unit 231 includes a first OR gate OR1, and each input terminal of the first OR gate OR1 is connected to a plurality of overvoltage protection units 221; the second logic processing unit 232 includes a second OR gate OR2, and each input terminal of the second OR gate OR2 is connected to a plurality of overcurrent protection units 222 and a plurality of short-circuit protection units 223.
[0090] It should be noted that the first OR gate OR1 and the second OR gate OR2 can ensure that each protection signal output by each protection unit can be correctly output.
[0091] In one embodiment, as Figure 22 shown, the embodiment of the present application further provides an electronic device 300. The electronic device 300 includes a device body and the above-mentioned chip 200 or switch circuit 100 provided on the device body. The electronic device 300 can be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) expansion dock, a stylus, a true wireless earphone, a car center screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart floor sweeper, and a smart light.
[0092] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned chip 200 or the switch circuit 100, the driving ability of the control end of the switch module 10 can also be improved by adding a first driving module 20 between the first end and the control end of the switch module 10, so as to reduce the on-resistance of the switch module 10, and further reduce the on-resistance of the switch circuit 100; when a high voltage is coupled to the control end of the switch module 10 through the parasitic capacitance at the second end of the switch module 10, the first clamping module 30 provided at the control end of the switch module 10 can be used to prevent the potential of the control end of the switch module 10 from being coupled to the high voltage, so that the output voltage of the first driving module 20 can be normally lifted, thereby avoiding the current flowing through the switch module 10 from having a spike, and further improving the performance degradation problem caused by the parasitic capacitance.
[0093] It should be noted that the above-mentioned electronic device 300 may further include a control module 310 and a Type-C module 320. The control module 310 may be a micro control unit (MCU).
[0094] In the USB Type-C PD application, the CC port is mainly responsible for PD communication, used to determine the correct or incorrect insertion of the device, handshake between devices, etc. This part of the function is usually controlled and completed by the MCU.
[0095] There are two CC ports, CC1 and CC2, on each Type-C interface. One of the two CC ports may also be used as the power supply VCONN of the E-Marker chip 200 on the cable. The E-Marker chip 200 is a simple USB PD controller embedded in the cable, which can respond to the USB PD instructions of the DFP / Source end and provide the basic electrical characteristics of the cable at the same time, such as current capacity, function, manufacturer identification ID, etc. The cable chip 200 is required in the USB Type-C cable with a load current capacity exceeding 3A or the full-function USB Type-C, such as the case of supporting USB 3.1 high-speed communication.
[0096] Among them, since the CC port may be short-circuited with VBUS during actual use, a high voltage may also appear at the CC port during large ESD or surge, and the VCONN switch itself also has requirements for overcurrent, so a protection module 220 is designed at the corresponding place in the circuit to prevent the circuit from being damaged.
[0097] Among them, the power supply terminal SYS_5V may include a first voltage terminal VCONN_1 and a second voltage terminal VCONN_2. The switches VCONN_SW1_P1, VCONN_SW2_P1, VCONN_SW1_P2, and VCONN_SW2_P2 are all one of the above-mentioned switch circuits 100. The power supply terminal SYS_5V can serve as the input terminal of the switch circuit 100.
[0098] Among them, the nodes CC1_P1_IN, CC2_P1_IN, CC1_P2_IN, and CC2_P2_IN can all serve as the input terminals of a configuration channel. The nodes CC1_P1_OUT, CC2_P1_OUT, CC1_P2_OUT, and CC2_P2_OUT can all serve as the output terminals of a configuration channel. A switch is also connected between the input terminal and the output terminal of each channel, such as switches CC1_P1_SW, CC2_P1_SW, CC1_P2_SW, and CC2_P2_SW. The control terminals of these switches are also connected to a voltage doubler charge pump and are controlled to be turned on and off by the control module 310.
[0099] OCP is the overcurrent protection unit 222. SCP is the short-circuit protection unit 223. OCP&SCP1, OCP&SCP2, OCP&SCP3, and OCP&SCP4 respectively output interruption signals INT1_1, INT1_2, INT1_3, and INT1_4. After passing through an OR gate, an interruption signal INT1 is generated and output to the control module 310. If any of the switch circuits 100 experiences overcurrent or short-circuit conditions, the control module 310 can receive the corresponding interruption signal.
[0100] The overvoltage protection units 221, namely OVP1 - OVP4, respectively output interruption signals INT2_1, INT2_2, INT2_3, and INT2_4. After passing through an OR gate, an interruption signal INT2 is generated and output to the control module 310. If any of the switch circuits 100 experiences overvoltage conditions, the control module 310 can receive the corresponding interruption signal.
[0101] OTP is the overtemperature protection unit 224, which outputs an interruption signal INT3 and outputs it to the control module 310. If the switch circuit 100 experiences overtemperature conditions, the control module 310 can receive the corresponding interruption signal.
[0102] The control module 310 can control the on and off of these switches in the PHY with reference to the interruption signal INT1, the interruption signal INT2, and the interruption signal INT3.
[0103] An eMark IC is provided in the Type-C module 320. Its Vcom1 terminal and Vcom2 terminal are both connected to a ground resistance Ra, and its Ccin terminal is connected to a ground resistance Rd.
[0104] The MCU is responsible for functions such as device access and plug - in detection of the Type - C CC port. The PHY is responsible for interface protection and the switching functions of these switches. The power supply of the power supply terminal SYS_5V comes from the system 5V voltage, and two Type - C interfaces are controlled respectively. When the CC channel is enabled, the switches CC1_P1_SW, CC2_P1_SW, CC1_P2_SW, and CC2_P2_SW are turned on, and the CC channel can perform normal communication detection.
[0105] When the VCONN channel is enabled, a certain VCONN switch (switch circuit 100) of the two CC ports is turned on to supply power to the Type - C. An over - voltage protection circuit (OVP) with a comparator structure is used at the common end of the VCONN switch and the CC switch to protect both the CC switch and the VCONN switch simultaneously. When the CC port is short - circuited to the high - voltage VBUS, on the one hand, the CC switch and the VCONN switch are turned off, and on the other hand, an interrupt signal is given. The four interrupt signals INT2_1~INT2_4 generate an interrupt signal INT2 after an OR logic operation and are sent to the MCU through the GPIO. Among them, the CC switch is the switches CC1_P1_SW, CC2_P1_SW, CC1_P2_SW, and CC2_P2_SW.
[0106] Since the VCONN switch has certain requirements for the magnitude of the current, a current - type over - current protection (OCP) and short - circuit protection (SCP) scheme is adopted inside the VCONN switch to limit the current within the required range. When the current is over - current, if the current exceeds the OCP threshold, the current is limited, and when the current exceeds the SCP threshold, the VCONN switch is directly turned off. Four interrupt signals INT1_1~INT1_4 also generate an interrupt signal INT1 after an OR logic operation and are sent to the MCU through the GPIO.
[0107] In addition, this architecture also integrates an over - temperature protection (OTP) circuit, which generates an interrupt signal INT3 through the GPIO to the MCU when the temperature exceeds the limit value.
[0108] The above is only a preferred embodiment of the present application and does not impose any form of limitation on the present application. Although the present application has been disclosed above with a preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to it as equivalent embodiments with equivalent changes within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modification, equivalent change, and modification made to the above - mentioned embodiment based on the technical essence of the present application still fall within the scope of the technical solution of the present application.
Claims
1. A switching circuit, characterized in that: The switch circuit comprises: A switch module, wherein a first end of the switch module is an input end of the switch circuit, and a second end of the switch module is an output end of the switch circuit; A first driving module, wherein an input end of the first driving module is connected to a first end of the switch module, and an output end of the first driving module is connected to a control end of the switch module; A first clamping module is connected between the control end and the ground end of the switch module.
2. The switch circuit according to claim 1, characterized in that: The switch module comprises a first transistor, the first electrode of the first transistor is the second end of the switch module, the second electrode of the first transistor is connected to the input end of the first driving module, and the control electrode of the first transistor is connected to the output end of the first driving module.
3. The switch circuit according to claim 2, characterized in that: The first transistor is a laterally diffused metal oxide semiconductor field effect transistor, a source of the laterally diffused metal oxide semiconductor field effect transistor is connected to the input end of the first driving module, a gate of the laterally diffused metal oxide semiconductor field effect transistor is connected to the output end of the first driving module, a drain of the laterally diffused metal oxide semiconductor field effect transistor is the second end of the switch module, a P-type substrate of the laterally diffused metal oxide semiconductor field effect transistor is connected to the ground end, and an N-type buried layer of the laterally diffused metal oxide semiconductor field effect transistor is connected to the source of the laterally diffused metal oxide semiconductor field effect transistor.
4. The switch circuit according to claim 3, characterized in that: The switch circuit further comprises a second clamping module, one end of which is connected to the P-type well lead-out end of the LDMOS field effect transistor, and the other end of which is connected to the ground end.
5. The switch circuit according to claim 4, characterized in that: The second clamping module includes a third Zener tube, a cathode of the third Zener tube is connected to the P-type well lead-out terminal of the LDMOS field effect transistor, and an anode of the third Zener tube is connected to the ground terminal.
6. The switch circuit according to claim 5, characterized in that: The switch circuit further comprises a current limiting module, which is connected to the cathode of the third Zener tube, the P-type well lead-out terminal of the LDMOS field effect tube, and the drain of the LDMOS field effect tube.
7. The switch circuit according to claim 6, characterized in that: The current limiting module comprises: A first current limiting unit, wherein the first current limiting unit is connected between the cathode of the third Zener tube and the P-type well lead-out terminal of the LDMOS field effect tube; A second current limiting unit is connected between the cathode of the third Zener tube and the drain of the LDMOS field effect tube.
8. The switch circuit according to claim 7, characterized in that: The switch circuit further includes a switching module connected between one end of the first current limiting unit and the cathode of the third Zener tube.
9. The switch circuit according to claim 8, characterized in that: The switching module comprises: A first switching unit, wherein the first switching unit is connected between one end of the first current limiting unit and the cathode of the third Zener tube; A second switching unit, wherein the second switching unit is connected between one end of the first current limiting unit and a ground end.
10. The switch circuit according to claim 9, characterized in that: The first switching unit includes a second transistor, a first electrode of the second transistor is connected to one end of the first current limiting unit, a second electrode of the second transistor is connected to the cathode of the third Zener tube, and a control electrode of the second transistor is connected to the first switch enable signal; The second switching unit includes a third transistor, a first electrode of the third transistor is connected to the ground terminal, a second electrode of the third transistor is connected to one end of the first current limiting unit, and a control electrode of the third transistor is connected to the first switch enable signal; The channel type of the second transistor is different from the channel type of the third transistor.
11. The switch circuit according to claim 1, characterized in that: The first driving module comprises: a first voltage doubling charge pump, wherein an input end of the first voltage doubling charge pump is connected to a first end of the switch module; A soft start unit, wherein the input end of the soft start unit is connected to the output end of the first voltage doubling charge pump, and the output end of the soft start unit is connected to the control end of the switch module.
12. The switch circuit according to claim 11, characterized in that: The first clamping module comprises: A first clamping unit, wherein the first clamping unit is connected between the control end of the switch module and the ground end; A second clamping unit, wherein the second clamping unit is connected between the first clamping unit and the control end of the switch module or the ground end.
13. The switch circuit according to claim 12, characterized in that: The first clamping unit comprises a first Zener tube, and a cathode of the first Zener tube is connected to a control end of the switch module; The second clamping unit includes a second Zener tube, a cathode of the second Zener tube is connected to an anode of the first Zener tube, and an anode of the second Zener tube is connected to the ground terminal.
14. A chip, characterized in that: The chip comprises the switch circuit according to any one of claims 1 to 13.
15. The chip according to claim 14, characterized in that: The chip further comprises: System power supply end; A plurality of interface circuits, each of the interface circuits comprising a first configuration channel and a second configuration channel; Among them, one of the switch circuits is connected between the system power supply end and the input end of the first configuration channel, and the other switch circuit is connected between the system power supply end and the input end of the second configuration channel.
16. The chip according to claim 15, characterized in that The chip further comprises: A protection module, wherein the protection module is connected to the switch circuit; A logic processing module is connected to the protection module.
17. The chip according to claim 16, characterized in that: The protection module comprises: A plurality of overvoltage protection units, each of which is connected to an output end of the switch circuit; A plurality of overcurrent protection units, each of which is connected to one of the switch circuits; A plurality of short-circuit protection units, each of which is connected to one of the switch circuits; An over-temperature protection unit is used to perform temperature protection on the switch circuit.
18. The chip according to claim 17, characterized in that: The logic processing module includes: A first logic processing unit, wherein the first logic processing unit is connected to the plurality of overvoltage protection units; A second logic processing unit, wherein the second logic processing unit is connected to the multiple overcurrent protection units and the multiple short-circuit protection units.
19. The chip according to claim 18, characterized in that: The first logic processing unit comprises a first OR gate, each input end of the first OR gate is connected to the plurality of overvoltage protection units; The second logic processing unit includes a second OR gate, and each input end of the second OR gate is connected to the multiple overcurrent protection units and the multiple short-circuit protection units.
20. An electronic device, characterized in that: The electronic device comprises a device body and a chip according to any one of claims 14 to 19 disposed in the device body.