Semiconductor package

Abstract

The utility model provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes: a first element die; a second element die stacked on the first element die; and a plurality of first electrical connectors and a plurality of second electrical connectors disposed between the first and second device dies. A first pitch of the plurality of first electrical connectors is greater than a second pitch of the plurality of second electrical connectors. The first electrical connector and the second electrical connector respectively comprise a solder contact and a plurality of first metal layers which are formed by first metal materials and located on two opposite sides of the solder contact. Each second connecting piece further comprises at least one second metal layer made of a second metal material. Thus, solder contacts in each second electrical connector having a shorter pitch are in contact with a thinner first metal layer, which is a material source of an intermetallic compound that causes lateral indentation. Based on reducing the source of material that results in lateral indentation, severe necking or breakage of the second electrical connector having a shorter pitch may be effectively prevented.

Description

Technical Field

[0001] The utility model relates to a semiconductor package. Background Art

[0002] The semiconductor industry is committed to reducing the feature size and power consumption of various electronic components, while increasing the component density, wiring density and operating frequency of electronic components. These advanced electronic components require more area-saving packaging technology.

[0003] Three dimensional integrated circuit (3DIC) is a semiconductor package developed in recent years, in which multiple dies are packaged in a stacked form. 3DIC provides better integration density and other advantages, such as faster operation speed and greater bandwidth, due to the shortened spacing between dies. However, 3DIC still has some challenges to overcome. For example, the bumps used to connect the vertically separated dies in 3DIC may have low reliability issues, especially those with relatively short pitches. Utility Model Content

[0004] One aspect of the utility model provides a semiconductor package, comprising: a first component die; a second component die, stacked on the first component die; and a plurality of first electrical connectors and a plurality of second electrical connectors, arranged between the first component die and the second component die, wherein the first pitch of the plurality of first electrical connectors is greater than the second pitch of the plurality of second electrical connectors, the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and a plurality of first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material.

[0005] Another aspect of the present invention provides a semiconductor package, comprising: a first component die; a second component die stacked on the first component die; a first polymer layer disposed on the surface of the first component die; a second polymer layer disposed on the surface of the second component die and bonded to the first polymer layer; a plurality of first electrical connectors and a plurality of second electrical connectors extending through the first polymer layer and the second polymer layer, wherein the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and a plurality of first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material; a first encapsulation body disposed on the first component die and laterally encapsulating the second component die; and a second encapsulation body laterally encapsulating the first encapsulation body and the first component die.

[0006] Another aspect of the utility model provides a semiconductor package, comprising: a first package component; a second package component, which is spaced apart from the first package component in a vertical direction; and a plurality of first electrical connectors and a plurality of second electrical connectors, which are arranged between the first package component and the second package component and connect the first package component and the second package component to each other, wherein the first critical width of each first electrical connector is greater than the second critical width of each second electrical connector, the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and multiple first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material.

[0007] Based on the above, the solder joints in each electrical connector with a shorter width and a shorter pitch are in contact with a thinner first metal layer (composed of a first metal material), which is a material source of the intermetallic compound causing lateral shrinkage. Based on the reduction of the material source causing the lateral shrinkage, severe necking or fracture of the electrical connector with a shorter width and a shorter pitch can be effectively prevented. Therefore, the reliability of the electrical connector with a shorter width and a shorter pitch can be improved, and better communication can be ensured between the packaging components on the opposite sides of the electrical connector. Furthermore, during manufacturing, electrical connectors with different sizes and different stacking designs are formed separately. In this way, it can be ensured that the upper and lower halves of each electrical connector with a shorter width and a shorter pitch have sufficient thickness, and the connection failure (joint failure) of the electrical connector with a shorter width and a shorter pitch can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A It is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention.

[0010] Figure 1B It is schematically shown Figure 1A An enlarged cross-sectional view of the contact feature stack is shown.

[0011] Figure 2 According to some embodiments of the present invention, Figure 1A A flow chart of a method for forming individual bonding layers and combining such bonding layers during semiconductor packaging is shown.

[0012] FIG. 3A to FIG. 3FIt is depicted Figure 2 Schematic cross-sectional views of the structure at various stages of the method are shown.

[0013] Figure 4 According to some embodiments of the present invention, Figure 1A The flowchart of the overall process of semiconductor packaging is shown.

[0014] FIG. 5A to FIG. 5J It is depicted Figure 4 Schematic cross-sectional views of intermediate structures at various stages of the method are shown.

[0015] Figure 6 It is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention.

[0016] Figure 7 According to some embodiments of the present invention, Figure 6 A flow chart of a method of semiconductor packaging.

[0017] FIG. 8A to FIG. 8C It is depicted Figure 7 Schematic cross-sectional views of intermediate structures at various stages of the method are shown.

[0018] Fig.9A and Fig. 9B It is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention.

[0019] Fig.10 It is a schematic cross-sectional view of an electrical connector according to some alternative embodiments of the present invention.

[0020] Fig.11A and Fig. 11B They are respectively plan schematic diagrams of arrangements of electrical connectors according to some embodiments of the present invention.

[0021] Fig. 11C It is a plan view schematically showing the arrangement of electrical connectors according to other embodiments of the utility model.

[0022] Figures 12 to 16 They are respectively schematic cross-sectional views of semiconductor packages according to some embodiments of the present invention. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0024] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, for ease of description, terms such as "first," "second," "third," "fourth," and similar terms may be used herein to describe similar or different components or features shown in the figures, and may be used interchangeably depending on the order of presence or the context of description.

[0025] Figure 1A is a schematic cross-sectional view of a semiconductor package 100 according to some embodiments of the present invention.

[0026] Please refer to Figure 1A , the semiconductor package 100 includes device dies 110 and 120 having the same or different functions and electrically connected to each other. The device die 110 is stacked on the device die 120 in a face-to-back manner. In other words, the active side of the device die 110 faces the back side of the lower device die 120. In some embodiments, the size of the bottom device die 120 is larger than the size of the top device die 110.

[0027] The top device die 110 includes a semiconductor substrate 112, and an active component (not shown) is formed on the active side of the semiconductor substrate 112. In addition, the top device die 110 also includes a metallization layer 114 stacked on the active side of the semiconductor substrate 112, which is used to route the active component. The side of the metallization layer 114 facing away from the semiconductor substrate 112 can define the active side of the top device die 110 facing the bottom device die 120. On the other hand, the side of the semiconductor substrate 112 facing away from the metallization layer 114 can define the back side of the top device die 110.

[0028] Similarly, the bottom device die 120 includes a semiconductor substrate 122, and an active component (not shown) may be formed on the active side of the semiconductor substrate 122. In addition, the bottom device die 120 includes a front side metallization layer 124 stacked on the active side of the semiconductor substrate 122 to route the active component. In addition, the bottom device die 120 includes a through substrate via 126 extending from the back side of the semiconductor substrate 122 through the semiconductor substrate 122, and includes a back side metallization layer 128, which covers the back side of the semiconductor substrate 122 and is configured to route the through substrate via 126. The back side of the bottom device die 120 facing the top device die 110 may be defined by the side of the back side metallization layer 128 facing away from the semiconductor substrate 122. On the other hand, the active side of the bottom device die 120 may be defined by the side of the front side metallization layer 124 facing away from the semiconductor substrate 122.

[0029] The top device die 110 and the bottom device die 120 are bonded to each other by polymer-to-polymer bonding and solder-to-solder connection. In detail, the bonding layer 130 along the active side of the top device die 110 includes a polymer layer 132 and a contact feature 134 filled in the opening of the polymer layer 132, and another bonding layer 132 along the back side of the bottom device die 120 includes a polymer layer 136 and a contact feature 138 filled in the opening of the polymer layer 136. The polymer-to-polymer bonding refers to the upper polymer layer 132 being bonded to the lower polymer layer 136. In addition, the solder-to-solder connection refers to the upper contact feature 134 being connected to the lower contact feature 138, respectively. According to this bonding method, the stacking of the contact structures 134, 138 forms an electrical connection, which serves as a vertical conductive path extending between the top device die 110 and the bottom device die 120. Since the upper polymer layer 132 may be patterned during the singulation of the top device die 110, the sidewalls of the upper polymer layer 132 may be substantially coplanar with the sidewalls of the metallization layer 114 and the semiconductor substrate 112 of the top device die 110. Similarly, the lower polymer layer 136 may be patterned during the singulation of the bottom device die 120, so the sidewalls of the lower polymer layer 136 may be substantially coplanar with the sidewalls of the semiconductor substrate 122 and the backside metallization layer 128, and the semiconductor substrate 122 and the frontside metallization layer 124 of the bottom device die 120. As will be described with reference to Figure 1B To further illustrate, some of the electrical connectors, each including an upper contact feature 134 and an overlapping lower contact feature 138 , have a first critical width and a first pitch, while others of the electrical connectors have a second critical width and a second pitch.

[0030] In addition, the top device die 110 and the bottom device die 120 are encapsulated in the semiconductor package 100. Specifically, the encapsulant 140 is formed on the lower polymer layer 136 and laterally encapsulates the top device die 110 and the upper bonding layer 130 lining the active side of the top device die 110. The encapsulant 140 may be patterned when singulating the bottom device die 120 so that the sidewalls of the encapsulant 140 may be substantially coplanar with the sidewalls of the bottom device die 120 (i.e., the sidewalls of the semiconductor substrate 122, the front metallization layer 124, and the back metallization layer 128) and the sidewalls of the lower polymer layer 136. Furthermore, the encapsulant 142 further laterally encapsulates the top device die 110, the bottom device die 120, and the bonding layer 130 extending therebetween that have been encapsulated by the encapsulant 140. In this manner, the encapsulation 140 surrounding the top component die 110 , the polymer layers 132 , 136 of the bonding layer 130 , and the bottom component die 120 laterally contacts the encapsulation 142 .

[0031] Furthermore, the bonded device die 110, 120 are further wired to connect to external components. Specifically, a bottom rewiring structure 144 may be formed along the bottom side of the encapsulation body 142 and the active side of the bottom device die 120, which includes a stack of dielectric layers 146 and conductive features 148 distributed in the stack of dielectric layers 146. The conductive features 148 are designed to wire the bottom device die 120 outward to the other side of the bottom rewiring structure 144. Conductive bumps 150 are disposed on the side of the bottom rewiring structure 144 facing away from the bottom device die 120, and may serve as package input / output (I / O) terminals for contacting components outside the semiconductor package 100. In some embodiments, the conductive features 148 in the bottom rewiring structure 144 are connected to the conductive features in the front metallization layer 124 of the bottom device die 120 via contact structures 152 in a dielectric layer 154 extending along one side of the front metallization layer 124. In these embodiments, the sidewalls of the dielectric layer 154 may be substantially coplanar with the sidewalls of the front metallization layer 124 , the semiconductor substrate 122 , and the back metallization layer 128 of the bottom device die 120 , and may laterally contact the encapsulation body 142 .

[0032] In other embodiments, the device dies 110 and 120 bonded to each other are further routed to the side of the package 142 facing away from the bottom rewiring structure 144. In these embodiments, the package through-holes 156 may be disposed on the bottom rewiring structure 144 around the device dies 110 and 120 bonded to each other, and extend through the package 142 to the top side of the package 142. In this way, the conductive features 148 in the bottom rewiring structure 144 may be routed to the top side of the package 142 along the vertical conductive paths established by the package through-holes 156. In addition, a top rewiring structure 158 including one or more dielectric layers 160 and conductive features 162 distributed in the dielectric layers 160 may be disposed along the top side of the packages 140 and 142 and the back side of the top device die 110, wherein the conductive features 162 are configured to route the package through-holes 156 outward. In some embodiments, the encapsulation body 140 and the top device die 110 are in contact with the top redistribution structure 158 via the adhesive layer 164. In these embodiments, the sidewall of the adhesive layer 164 may be substantially coplanar with the sidewall of the encapsulation body 140 and may laterally contact the encapsulation body 142.

[0033] According to some embodiments, the package component 166 is stacked on the top rewiring structure 158, and the conductive bump 168 disposed therebetween is configured to establish an electrical connection between the package component 166 and the conductive feature 162 in the top rewiring structure 158, so that the device dies 110 and 120 bonded to each other can be connected to the package component 166 via the bottom rewiring structure 144, the package through-hole 156, the top rewiring structure 158, and the conductive bump 168. As an example, the package component 166 may include a circuit substrate 170, a stack of device dies 172 attached to the circuit substrate 170, and an encapsulation body 174 encapsulating the device dies 172. The device dies 172 may be connected to the conductive feature 176 in the circuit substrate 170 via a bonding wire 178, and may be wired to the conductive bump 168 via the bonding wire 178 and the conductive feature 176 in the circuit substrate 170. However, referring to Figure 1A The described embodiments are not limited to the detailed features of the packaging assembly 166. The packaging assembly 166 may also be provided as another type of packaging component.

[0034] As described above, the device dies 110, 120 in the semiconductor package 100 are stacked in a vertical direction rather than arranged side by side. Furthermore, the stacking of the contact features 134, 138 between the device dies 110, 120 can provide the shortest conductive path between the device dies 110, 120. Among other advantages, as will be further described below, the electrical connection formed by the stacking of the contact features 134, 138 can be ensured to have better reliability.

[0035] Figure 1B It is schematically shown Figure 1A An enlarged cross-sectional view of the stack of contact features 134 , 138 is shown.

[0036] The electrical connectors 180, each having an upper portion provided by one of the contact structures 134 and a lower portion provided by one of the contact structures 138, are formed in the polymer layers 132 and 136 of the bonding layer 130. The first group of electrical connectors 180 (referred to as electrical connectors 180a) are formed to have a first pitch P 180a With the first critical width W 180a1 (shortest width), and the second group of electrical connectors 180 (referred to as electrical connectors 180b) are formed to have a second pitch P 180b With the second critical width W 180b1 (Shortest width). First pitch P 180a Greater than the second pitch P 180b , and the first critical width W 108a1 Greater than the second critical width W 180b1 As an example, the first pitch P 180aThe second pitch P may be in the range of 50 μm to 150 μm; 180b The first critical width W may be in the range of 5 μm to 25 μm; 180a1 may be in the range of 35 μm to 85 μm; and the second critical width W 180b1 The electrical connectors 180a and 180b may be designed to have the above-mentioned size differences based on the different types of signals transmitted. For example, the electrical connector 180a with a larger pitch and a larger critical width may be configured to transmit some signals including power and ground signals, while the electrical connector 180b with a smaller pitch and a smaller critical width may be configured to realize signal communication between the device dies 110 and 120.

[0037] Based on the size difference, the electrical connectors 180a and 180b are designed to have different stacking combinations (or stacking designs). In some embodiments, the upper and lower halves of each of the electrical connectors 180a and 180b are formed as the same stacking design and are symmetrical (in terms of stacking design) relative to the interface between the upper and lower halves. As an example, the contact feature 134 as the upper half of each electrical connector 180a and the contact feature 138 as the lower half of each electrical connector 180a may respectively include a stack of seed layers 182a and 184a, a metal layer 186a grown from the seed layers 182a and 184a, and a solder joint 188a covering the metal layer 186a. Furthermore, in each electrical connector 180a, the solder joint 188a of the upper half, the metal layer 186a and the seed layer 184a, 182a and the solder joint 188a of the lower half, the metal layer 186a and the seed layer 184a, 182a are arranged in sequence from the interface between the upper and lower halves outward. Therefore, the electrical connector 180a is symmetrical with respect to the interface between the upper and lower halves (in terms of stacking design). On the other hand, the contact feature 134 as the upper half of each electrical connector 180b and the contact feature 138 as the lower half of each electrical connector 180b can respectively include a stack of seed layers 182b, 184b, a metal layer 186b grown from the seed layers 182b, 184b, and a solder joint 188b covering the metal layer 186b. In addition, in each electrical connector 180b, the solder joints 188b, metal layer 186b and seed layers 184b, 182b of the upper half and the solder joints 188b, metal layer 186b and seed layers 184b, 182b of the lower half are arranged in order from the interface between the upper and lower halves outward. Therefore, the electrical connector 180b is also symmetrical with respect to the interface between the upper and lower halves (in terms of stacking design).

[0038] In this example, the metal layer 186a in each electrical connector 180a may be composed of a first metal material. In addition, the metal layer 186b in the upper half or lower half of each electrical connector 180b may include a pair of first metal layers 186b1 composed of a first metal material, and may include a second metal layer 186b2 composed of a second metal material and sandwiched between the first metal layers 186b1. The first metal material is different from the second metal material. For example, the first metal material may include copper, and the second metal material may include nickel, cobalt, iron or a combination thereof. Intermetallic compounds may be easily formed at the interface between each solder joint 188a / 188b and the covering metal layer 186a / 186b1 composed of the first metal material, and extend inward from the peripheral area of ​​each electrical connector 180a / 180b. As a result, lateral concavity may be generated at the junction of this interface and the side wall of each electrical connector 180a / 180b, and the electrical connector 180b may be broken or severely necked due to the formation of the electrical connector 180b with a shorter critical width. By further providing a metal layer (i.e., metal layer 186b2) composed of a second metal material in the electrical connector 180b, the metal layer 186b1 composed of the first metal material and contacting the solder joint 188b may have a smaller thickness (compared to the thickness of the metal layer 186a in the electrical connector 180a). In this way, the electrical connector 180b may have less material source for forming the intermetallic compound. Accordingly, the lateral concavity problem of the electrical connector 180b caused by the formation of the intermetallic compound can be effectively suppressed. In other words, the problem of breaking or severely necking the electrical connector 180b can be effectively avoided, and the communication between the component dies 110 and 120 can be ensured to be more reliable.

[0039] As described above, despite being made of the same material (first metal material), metal layer 186b1 is thinner than metal layer 186a. In some embodiments, metal layer 186b2 is also thinner than metal layer 186a. As an example, the thickness of metal layer 186a may be in the range of 8 μm to 12 μm; the thickness of metal layer 186b1 may be in the range of 1 μm to 5 μm; and the thickness of metal layer 186b2 may be in the range of 3 μm to 6 μm.

[0040] According to some embodiments, the upper and lower halves of each electrical connector 180a / 180b may have slightly different pattern widths. For example, the contact features 138 provided as the lower half of each electrical connector 180a are formed to have a first critical width W 180a1 , and the contact features 134 provided as the upper half of an electrical connector 180a are formed to be slightly larger than the first critical width W 180a1 Width W 180a2Similarly, the contact features 138 provided as the lower half of each electrical connector 180b are formed to have a second critical width W 180b1 , and the contact features 134 provided as the upper half of an electrical connector 180b are formed to be slightly larger than the second critical width W 180b1 Width W 180b2 By designing each electrical connector 180a / 180b to be slightly wider at the upper half than at the lower half, a greater tolerance can be provided in terms of overlay accuracy when joining the upper and lower halves, and the upper and lower halves can be ensured to be joined to each other with a sufficient contact area.

[0041] Furthermore, as described above, the contact structure 134 providing the upper half of one of the electrical connectors 180a, 180b is filled in the opening of the polymer layer 132, and the contact structure 138 providing the lower half of one of the electrical connectors 180a, 180b is filled in the opening of the polymer layer 136. In this way, the solder joints 188a, 188b of the electrical connectors 180a, 180b are confined in the polymer layers 132, 136 to avoid lateral protrusion during possible heat treatment in the process. Therefore, it is possible to effectively avoid the adjacent electrical connectors 180a, 180b from undesirably contacting each other (especially for the electrical connectors 180b with a shorter pitch).

[0042] Figure 2 is a flow chart of a method for forming individual bonding layers 130 and combining such bonding layers 130 according to some embodiments of the present invention. FIG. 3A to FIG. 3F It is depicted Figure 2 Schematic cross-sectional views of the structure at various stages of the method are shown.

[0043] Initially, the bonding layers 130 are formed on the device dies 110 and 120, respectively. Although the bonding layers 130 on the device dies 110 and 120 are shown to be formed simultaneously in a series of process steps, it should be understood that these bonding layers 130 can also be formed at different time points. In other words, these bonding layers 130 can be formed at the same time, or the formation of one bonding layer 130 can be after the formation of another bonding layer 130.

[0044] Please refer to Figure 2 and Figure 3A At step S200, a stack of initial seed layers 300 and 302 is formed on each of the device die 110 and the device die 120. Currently, the initial seed layers 300 and 302 can completely cover the device die 110 and 120. In subsequent steps, the initial seed layers 300 and 302 will be patterned into seed layers 182a and 184a and seed layers 182b and 184b on each of the device die 110 and 120.

[0045] Please refer to Figure 2 and Figure 3B At step S202, a metal layer 186b and solder joints 188b are formed on the initial seed layers 300 and 302. A mask pattern (not shown) having openings may be formed in advance on the stack of initial seed layers 300 and 302. In this way, the metal layer 186b and solder joints 188b on each of the device dies 110 and 120 are defined in the openings of the mask pattern. After the metal layer 186b and solder joints 188b are formed, the mask pattern may be removed. In some embodiments, the metal layer 186b and solder joints 188b are formed on each of the device dies 110 and 120 by a series of plating processes.

[0046] Please refer to Figure 2 and Figure 3C , at step S204, a metal layer 186a and a solder joint 188a are formed on the initial seed layers 300, 302. A mask pattern (not shown) having openings may be formed in advance on the initial seed layers 300, 302 of each of the device dies 110, 120, and these mask patterns cover the metal layer 186b and the solder joint 186b on the device dies 110, 120. In this way, the metal layer 186a and the solder joint 188a are defined in the openings of the mask pattern on each of the device dies 110, 120. After the metal layer 186a and the solder joint 188a are formed, the mask pattern may be removed. In some embodiments, the metal layer 186a and the solder joint 188a are formed on each of the device dies 110, 120 by a series of plating processes.

[0047] Please refer to Figure 2 and Figure 3D At step S206, the initial seed layer 300, 302 on each of the device die 110, 120 is patterned. Specifically, on each of the device die 110, 120, the portion of the initial seed layer 300, 302 that is not shielded by the stack of the metal layer 186a and the solder joint 188a and the stack of the metal layer 186b and the solder joint 188b is removed, and the remaining portion of the initial seed layer 300, 304 forms the seed layer 182a, 184a and the seed layer 182b, 184b. At this point, the contact feature 134 that is provided as the upper half of one of the electrical connectors 180a, 180b is formed on the device die 110, and the contact feature 138 that is provided as the lower half of one of the electrical connectors 180a, 180b is formed on the device die 120.

[0048] Please refer to Figure 2 and Figure 3EAt step S208, polymer layers 132 and 136 are formed on the device die 110 and 120, respectively. The polymer layer 132 laterally surrounds the contact feature 134 on the device die 110, and the polymer layer 136 laterally surrounds the contact feature 138 on the device die 120. According to some embodiments, the polymer layer 132 on the device die 110 is formed to a height higher than the contact feature 134, and is etched back to expose the solder joints 188a, 188b of the contact feature 134. As a result, a recess RS is defined on the bonding surface of the bonding layer 130 including the contact structure 134 and the polymer layer 132. In addition, the polymer layer 136 on the device die 120 is thinned so that the solder joints 188a, 188b of the contact structure 138 protrude from the top surface of the polymer layer 136, and a protrusion structure PR is defined on the bonding surface of the bonding layer 130 including the contact structure 138 and the polymer layer 136.

[0049] Please refer to Figure 2 and Figure 3F At step S210, the bonding layer 130 on the component die 110 is bonded to the bonding layer 130 on the component die 120. One of the component die 110, 120 may be turned over and placed on the other in advance. As a result, the polymer layers 132, 136 may contact each other, and the protruding structures PR protruding from the polymer layer 136 may be respectively inserted into the recesses RS recessed from the polymer layer 132. Subsequently, a heat treatment is performed. In this way, the polymer layers 132, 136 are bonded to each other, and the solder joints 188a, 188b defining the protruding structures PR are bonded to the solder joints 188a, 188b exposed in the recess RS. Furthermore, another heat treatment may be performed subsequently to reflow the solder joints 188a, 188b so that the solder joints 188a, 188b may completely fill the recess RS.

[0050] As described above, on each of the component dies 110, 120, the metal layer 186b of the electrical connector 180b and the solder joint 188b are formed before the metal layer 186a of the solder joint 180a and the solder joint 188a. However, in other embodiments, the metal layer 186b of the electrical connector 180b and the solder joint 188b on each of the component dies 110, 120 are formed after the metal layer 186a of the electrical connector 180a and the solder joint 188a. In any case, the metal layer 186b and the solder joint 188b on each of the component dies 110, 120 are formed by a first series of plating processes, while the metal layer 186a and the solder joint 188a on each of the component dies 110, 120 are formed by a second series of plating processes before or after the first series of plating processes. Because the electrical connector 180b is designed to have a shorter critical width (compared to the electrical connector 180a), the current density provided during the first series of plating processes may be lower than the current density provided during the second series of plating processes. To compensate for this difference in current density, the process time of the first series of plating processes may be adjusted to be longer than the process time of the second series of plating processes so that the height of the contact features 134, 138 including the metal layer 186b and the solder joint 188b will not be too lower than the contact features 134, 138 including the metal layer 186a and the solder joint 188a. If the metal layers 186a, 186b and the solder joints 188a, 188b are formed on each of the device dies 110, 120 by a series of plating processes, the contact features 134, 138 including the metal layer 186b and the solder joint 188b may be too short than the contact features 134, 138 including the metal layer 186a and the solder joint 188a, and these too short contact features 134, 138 may not be able to contact each other during the bonding step. In other words, by forming the contact features 134 / 138 of both the electrical connectors 180a, 180b by a different series of plating processes on each of the device dies 110, 120, the electrical connectors 180a, 180b (especially the electrical connector 180b) can be ensured to have good reliability.

[0051] Figure 4 According to some embodiments of the present invention, Figure 1A FIG. 1 is a flow chart of an overall process of semiconductor package 100 . FIG. 5A to FIG. 5J It is depicted Figure 4 Schematic cross-sectional views of intermediate structures at various stages of the method are shown.

[0052] Please refer to Figure 4 , Figure 5A and Figure 5B In step S400, a device die 120 in wafer form and covered with a bonding layer 130 is provided. Figure 5A As shown, a series of processes are performed to form a front side metallization layer 124 on the active side of the semiconductor substrate 122, a through-substrate via 126 extending from the active side of the semiconductor substrate 122 into the semiconductor substrate 122, and a contact structure 152 and a dielectric layer 154 on the outermost metallization layer 124. Figure 5B As shown, the obtained structure is flipped over and attached to the carrier substrate 500 via the adhesive layer 502. Subsequently, the semiconductor substrate 122 is thinned from the back side of the semiconductor substrate 122 to expose the substrate through hole 126, and a back side metallization layer 128 is formed on the back side of the semiconductor substrate 122. Afterwards, a bonding layer 130 is formed on the back side metallization layer 128, and this bonding layer 130 can be made by referring to FIG. 3A to FIG. 3E The process described is used to form.

[0053] Please refer to Figure 4 and Figure 5C In step S402, a device die 110 in chip form and covered with another bonding layer 130 is provided. Initially, the device die 110 may be formed by referring to FIG. 3A to FIG. 3E The bonding layer 130 is formed on the element die 110 in a wafer state by the described process. Subsequently, the element die 110 in a wafer state and covered with the bonding layer 130 can be attached to the tape 504 connected to the frame 506 and singulated. Thus, the element die 110 in a chip state and covered with the bonding layer 130 is obtained.

[0054] Please refer to Figure 4 and Figure 5D At step S404, the element dies 110 and 120 are bonded to each other. The element die 110 in a chip state may be picked up in advance and placed on the element die 120 in a wafer state so that the bonding layer 130 covering the element die 110 contacts the bonding layer 130 covering the element die 120. After the placement, the reference Figure 3F As a result, the polymer layers 132 and 136 of the bonding layer 130 are bonded to each other, and the contact features 134 of one bonding layer 130 are bonded to the contact features 138 of the other bonding layer 130. Thus, the device dies 110 and 120 are bonded to each other via the bonding layer 130.

[0055] Please refer to Figure 4 and Figure 5E At step S406, an encapsulation body 140 is formed on the bonding layer 130 lining the device die 120 in a wafer state. As a result, the encapsulation body 140 laterally encapsulates the device die 110 bonded to the device die 120 and laterally contacts the bonding layer 130 lining the device die 110.

[0056] Please refer to Figure 4 and Fig. 5F In step S408, the carrier substrate 500 is removed and the current package structure is singulated. Figure 5E The package structure shown is turned over and attached to the tape 508 connected to the frame 510. Subsequently, the carrier substrate 500 and the adhesive layer 502 can be separated from the device die 120. In addition, the current package structure on the tape 508 can be singulated. As a result, the device die 120 in a chip state is obtained, and the bonding layer 130 and the encapsulation body 140 are cut along with the device die 120.

[0057] Please refer to Figure 4 and Figure 5G At step S410, a redistribution structure 158 is formed on another carrier substrate 512, and an encapsulation through-hole 156 is formed on the redistribution structure 158. Some of the encapsulation through-holes 156 are sufficiently spaced apart so that the spacing between these encapsulation through-holes 156 can accommodate Fig. 5F The package structure is shown on tape 508.

[0058] Please refer to Figure 4 and Figure 5H , at step S412, Fig. 5F The package structure shown on the tape 508 is picked up and placed on the redistribution structure 158 between the package through-holes 156. Specifically, the package structure is oriented so that the device die 110 and the package 140 face the redistribution structure 158. The adhesive layer 164 may be located between the package structure and the redistribution structure 158 to enhance the adhesion of the redistribution structure 158 to the device die 110 and the package 140. Thereafter, at step S414, the encapsulation 142 is formed on the redistribution structure 158 to laterally encapsulate the package through-holes 156 on the redistribution structure 158 and the package structure.

[0059] Please refer to Figure 4 and Fig.5I In step S416, a redistribution structure 144 and a conductive bump 150 are formed on the encapsulation body 142. Figure 5J In step S418, the carrier substrate 512 is separated from the current package structure. Fig.5I The package structure is flipped over and attached to a tape (not shown). Afterwards, the carrier substrate 512 is separated from the redistribution structure 158 .

[0060] In the subsequent step S420, the current package structure is singulated. In addition, in step S422, the package component 166 can be attached to the singulated package structure by means of the conductive bumps 168 to obtain Figure 1A A semiconductor package 100 is shown.

[0061] As described above, the device die 110 is bonded to the device die 120 in a face-to-back manner. However, in other embodiments, the device die 110 is bonded to the device die 120 in a face-to-face manner.

[0062] Figure 6 is a schematic cross-sectional view of a semiconductor package 600 according to some embodiments of the present invention.

[0063] The semiconductor package 600 is similar to the reference Figure 1A and Figure 1B The semiconductor package 100 described above is different from the semiconductor package 600 in that the device dies 110 and 120 are bonded to each other in a face-to-face manner. Figure 6 As shown, one bonding layer 130 extends along the active side of the device die 110 (i.e., the side of the metallization layer 114 facing away from the semiconductor substrate 112), and another bonding layer 130 extends along the active side of the device die 120 (the side of the front metallization layer 124 facing away from the semiconductor substrate 122). In this way, the bottom rewiring structure 144 contacts the back side of the device die 120. According to some embodiments, an insulating layer 602 is formed along the back side of the device die 120, and a conductive feature 604 in the insulating layer 602 serves as a contact structure for the through-substrate via 126 of the device die 120 extending through the semiconductor substrate 122.

[0064] Figure 7 is a flow chart of a method for forming a semiconductor package 600 according to some embodiments of the present invention. FIG. 8A to FIG. 8C It is depicted Figure 7 Schematic cross-sectional views of intermediate structures at various stages of the method are shown.

[0065] The process for forming the semiconductor package 600 is similar to that of Figure 4 and FIG. 5A to FIG. 5J The processes are as described, except for the differences described further below.

[0066] like Fig. 8A As shown, at step S400 of providing a device die 120 in a wafer state and covered with a bonding layer 130, the bonding layer 130 is formed on the front side metallization layer 124 of the device die 120. In addition, the back side metallization layer 128 may not be formed, and a carrier substrate carrying the device die 120 is not required.

[0067] After performing die bonding in step S404 and encapsulation in step S406, Figure 8BThe obtained wafer-state package structure is attached to a carrier substrate 800 at step S700 shown. Specifically, the package structure can be attached to the carrier substrate 800 via the semiconductor substrate 112 of the device die 110 and the encapsulation body 140. In addition, an adhesive layer 802 can be disposed therebetween to strengthen the adhesion between the carrier substrate 800 and each of the semiconductor substrate 112 and the encapsulation body 140. After the attachment, the back side of the semiconductor substrate 122 of the device die 120 can be exposed, and the semiconductor substrate 122 can be thinned to reveal the through-substrate via 126. At step S702, an insulating layer 602 and a conductive feature 604 are further formed on the back side of the semiconductor substrate 122, so that the conductive feature 604 can serve as a contact structure for the through-substrate via 126.

[0068] Please refer to Figure 7 and Figure 8C At step S704, the carrier substrate 800 is separated from the current package structure. In the example including the adhesive layer 802, the adhesive layer 802 can be removed along with the carrier substrate 800. At the next step S706, the current package structure is singulated. As a result, the obtained device die 120 is in a chip state, and the bonding layer 130 and the insulating layer 602 lining the device die 120 and the encapsulation body 140 surrounding the device die 110 are cut along the device die 120. Although not shown, during singulation, the package structure can be attached to the tape via the insulating layer 602.

[0069] In step S410, the redistribution structure 158 and the package through-hole 156 have been provided on another carrier substrate 512. The singulated package structure obtained in step S706 can be completed through a series of steps S412, S414, S416, S418, and S420. Figure 6 Fabrication of semiconductor package 600 is shown.

[0070] In addition to the orientation of the device dies 110, 120, the manner in which the electrical connectors 180a, 180b are encapsulated may also vary. In the above-described embodiment, the electrical connectors 180a, 180b are encapsulated by the polymer layers 132, 136 lining the bonding sides of the device dies 110, 120. In other embodiments, the electrical connectors 180a, 180b may be encapsulated by an underfill.

[0071] Fig.9A and Fig. 9B 2 is a schematic cross-sectional view of semiconductor packages 900a and 900b according to some embodiments of the present invention.

[0072] Fig.9A The semiconductor package 900a shown is similar in structure to the reference Figure 1Aand Figure 1B The semiconductor package 100 is described, except that the electrical connectors 180a, 180b in the semiconductor package 900a are surrounded by the underfill 902. In addition, the process for forming the semiconductor package 900a is similar to the process for forming the semiconductor package 100, except for the formation of the bonding mechanism between the device dies 110, 120. Figure 2 and FIG. 3A to FIG. 3F In the described process, the formation of the bonding mechanism between the device dies 110 and 120 in the semiconductor package 900a may include forming the contact feature 134 on the device die 110 by using different series of plating processes, and also includes forming the contact feature 138 on the device die 120 by using different series of plating processes. Subsequently, the contact structure 134 is bonded to the contact structure 138 by using a soldering flux to form the electrical connectors 180a and 180b. Afterwards, the underfill 902 may be formed around the electrical connectors 180a and 180b. At this point, the device dies 110 and 120 are bonded to each other.

[0073] on the other hand, Fig. 9B The semiconductor package 900b shown is similar in structure to the reference Figure 6 The semiconductor package 600 is described, but the electrical connectors 180a, 180b in the semiconductor package 900b are surrounded by the underfill 902. Figure 7 The described process may be used to form a semiconductor package 900b, but may be referred to as Fig.9A The described approach changes the formation method of the bonding mechanism between the device dies 110 , 120 .

[0074] As long as it does not violate the spirit and scope of the utility model, more changes can be applied. As mentioned above, the electrical connectors 180a and 180b can have a symmetrical stacking design respectively. Alternatively, the electrical connector 180b can have an asymmetrical stacking design, while the electrical connector 180a can maintain a symmetrical stacking design.

[0075] Fig.10 It is a cross-sectional schematic diagram of electrical connectors 180a and 180b according to some alternative embodiments of the present invention.

[0076] Please refer to Fig.10In some alternative embodiments, each electrical connector 180b has an asymmetric stack design. Specifically, in these alternative embodiments, the stack design of the contact features 134 provided as the upper half of each electrical connector 180b is different from the stack design of the contact features 138 provided as the lower half of each electrical connector 180b. For example, each contact structure 134 as the upper half of each electrical connector 180b may include a thick single first metal layer 186b1 disposed between the seed layers 182b, 184b and the solder joint 188b, while each contact structure 138 as the lower half of each electrical connector 180b may include two first metal layers 186b1 disposed between the seed layers 182b, 184b and the solder joint 188b and a second metal layer 186b2 sandwiched between the two first metal layers 186b1. Although not shown, as another example, each contact structure 134 serving as the upper half of an electrical connector 180b may include two first metal layers 186b1 disposed between the seed layers 182b, 184b and the solder joint 188b and a second metal layer 186b2 sandwiched between the two first metal layers 186b1, and each contact structure 138 serving as the lower half of an electrical connector 180b may include a thick single first metal layer 186b1 disposed between the seed layers 182b, 184b and the solder joint 188b.

[0077] On the other hand, the electrical connector 180a may have a symmetrical stacking design, as shown in FIG. Figure 1B See Fig.10 The described electrical connectors 180 a and 180 b may be used in any semiconductor package described in the present invention.

[0078] Furthermore, the electrical connectors 180a, 180b in each semiconductor package described in the present invention can be arranged in a variety of configurations. Several configurations of the electrical connectors 180a, 180b will be described below. However, it should be understood that the present invention is not limited to these exemplary configurations of the electrical connectors 180a, 180b.

[0079] Fig.11A and Fig. 11B They are respectively schematic plan views of arrangements of electrical connectors 180a and 180b according to some embodiments of the present invention.

[0080] The electrical connector 180a and the electrical connector 180b are distributed in adjacent areas. Fig.11A As shown, according to some embodiments, the electrical connector 180b with a shorter pitch and a shorter critical width surrounds the electrical connector 180a with a larger pitch and a larger critical width. For example, multiple arrays of electrical connectors 180b are arranged along both sides of the array of electrical connectors 180a. Fig. 11BAs shown, according to other embodiments, the electrical connectors 180b with shorter pitches and shorter critical widths are distributed in an island-like manner among the electrical connectors 180a with larger pitches and larger critical widths (only a single island-like distribution is shown).

[0081] Fig. 11C It is a plan view schematically showing the arrangement of the electrical connectors 180a and 180b according to other embodiments of the present invention.

[0082] Please refer to Fig. 11C According to some other embodiments, the electrical connector 180a is arranged in the regions Ra1 and Ra2, while the electrical connector 180b is arranged in the regions Rb1, Rb2, and Rb3 that are dispersed in the regions Ra1 and Ra2. In terms of pitch and critical width, the electrical connector 180a in the region Ra1 is different from the electrical connector 180a in the region Ra2. Similarly, the electrical connector 180b in the regions Rb1, Rb2, and Rb3 may differ in pitch and critical width. Nevertheless, even the shortest pitch and critical width of the electrical connector 180a are still greater than the maximum pitch and critical width of the electrical connector 180b, respectively. Fig. 11C In the example shown, region Ra2 surrounds region Ra1, and regions Rb1, Rb2, Rb3 are interspersed in regions Ra1, Ra2. Some of regions Rb1, Rb2, Rb3 further extend across the interface between regions Ra1, Ra2.

[0083] Next, more various semiconductor packages to which the electrical connectors 180 a , 180 b are applicable will be described.

[0084] Figures 12 to 16 They are respectively schematic cross-sectional views of semiconductor packages according to some embodiments of the present invention.

[0085] Please refer to Fig.12 The electrical connectors 180a and 180b are applied to a multi-chip module (MCM) semiconductor package 1200. The semiconductor package 1200 includes a package assembly 1202, which is Figure 6 The sub-package structure shown includes device dies 110 and 120 oriented in a face-to-face manner, a bonding layer 130 between the device dies 110 and 120, and an encapsulation body 140 that laterally surrounds the device die 110 and one of the bonding layers 130 lining the device die 110. The package component 1202 is further attached to the package substrate 1204 via conductive bumps 1206. In some embodiments, the conductive bumps 1206 are encapsulated in an underfill 1208 filled between the package component 1202 and the package substrate 1204.

[0086] In addition, another package component 1210 is also attached to the package substrate 1204, and the package components 1202 and 1210 are arranged side by side on the package substrate 1204. As an example, the package component 1210 may include a stack of device dies (not shown). Conductive bumps 1212 may be used to connect the package component 1210 to the package substrate 1204, and bottom filler 1214 may be filled between the package component 1210 and the package substrate 1204 to seal the conductive bumps 1212.

[0087] The wiring unit 1216 in the package substrate 1204 can establish a conductive path for interconnecting the package components 1202 and 1210 and for wiring the package components 1202 and 1210 to the other side of the package substrate 1204. As I / O terminals of the semiconductor package 1200, conductive bumps 1218 can be disposed on the side of the package substrate 1204 facing away from the package components 1202 and 1210. In some embodiments, passive components 1220 can be mounted to the side of the package substrate 1204 facing away from the package components 1202 and 1210 and located between adjacent conductive bumps 1218.

[0088] Some variations may be applied to semiconductor package 1200. For example, package component 1202 may be Figure 1A The sub-package assembly shown in FIG. 1 includes device dies 110 and 120 oriented in a face-to-back manner, a bonding layer 130 located between the device dies 110 and 120, and an encapsulation body 140 that laterally surrounds the device dies 110 and one of the bonding layers 130 lining the device dies 110. In addition, similar to Fig.9A or Fig. 9B The electrical connectors 180a, 180b shown in the figure can be encapsulated by the bottom filler as an alternative. Furthermore, the electrical connectors 180a, 180b can be formed into a symmetrical stacking design, as shown in FIG. Figure 1B As an alternative, as described in Fig.10 As described above, the electrical connector 180a can be formed to have an asymmetric stacking design, while the electrical connector 180b can be formed to have a symmetric stacking design. In addition, the electrical connectors 180a and 180b can be arranged in a variety of configurations, such as with reference to FIG. 11A to FIG. 11C Described configuration method.

[0089] Please refer to Fig.13, the electrical connectors 180a, 180b can be applied in the semiconductor package 1300. The semiconductor package 1200 is a 2.5D semiconductor package, in which a plurality of device dies 1310 are laterally encapsulated by the encapsulation body 1320 and attached to the interposer 1330. The conductive features formed in the interposer 1330 are configured to bridge the device dies 1310 and route the device dies 1310 to the other side of the interposer 1310. Similar to the reference Figure 1A The device die 110 described, each device die 1310 may include a semiconductor substrate 1312 and a metallization layer 1314 (only one is shown) stacked on an active side of the semiconductor substrate 1312. In some embodiments, an insulating layer 1316 is further formed on the metallization layer 1314 in each device die 1310.

[0090] In addition, the interposer 1330 located below the device die 1310 includes a substrate 1332 (e.g., a semiconductor substrate); a metallization layer 1334 (only one is shown) stacked on the side of the substrate 1332 facing the device die 1310; and a substrate through-hole 1336 penetrating the substrate 1332. In some embodiments, an insulating layer 1338 further covers the metallization layer 1334. Furthermore, in some embodiments, a conductive feature 1340 is disposed on the other side of the substrate 1332 as a contact structure for the substrate through-hole 1336, and an insulating layer 1342 is formed around the conductive feature 1340.

[0091] The electrical connectors 180a and 180b extend along a vertical direction between the metallization layer 1334 of the interposer 1330 and the metallization layer 1314 of each device die 1310. In an embodiment where the active side of each device die 1310 is covered by the insulating layer 1316, the electrical connectors 180a and 180b may extend through the insulating layer 1316, respectively. Similarly, in an embodiment where the interposer 1330 further includes an insulating layer 1338 covering the metallization layer 1334, the electrical connectors 180a and 180b may extend through the insulating layer 1338 to contact the metallization layer 1334.

[0092] According to some embodiments, the electrical connectors 180a, 180b are located in the bonding layer 1350, wherein the bonding layer 1350 is similar to the reference Figure 1A and Figure 1BThe illustrated bonding layer 130. In these embodiments, the polymer layer 1352 of the upper bonding layer 1350 covers the metallization layer 1314 of a device die 1310, and the polymer layer 1354 of the lower bonding layer 1350 covers the metallization layer 1334 of the interposer 1330. The polymer layers 1352 are bonded to the polymer layers 1354, respectively, and the electrical connectors 180a, 180b extend through the polymer layers 1352 and portions of the polymer layers 1354 bonded to the polymer layers 1352 to establish a conductive path between the device die 1310 and the interposer 1330.

[0093] In other embodiments, the electrical connectors 180a and 180b extending between the interposer 1330 and each device die 1310 are encapsulated by a bottom filler (not shown) instead of the polymer layers 1352 and 1354. Furthermore, the electrical connectors 180a and 180b can be formed to have a symmetrical stacking design, as shown in FIG. Figure 1B As an alternative, as described in Fig.10 As described above, the electrical connector 180a can be formed to have an asymmetric stacking design, while the electrical connector 180b can be formed to have a symmetric stacking design. In addition, the electrical connectors 180a and 180b can be arranged in a variety of configurations, such as with reference to FIG. 11A to FIG. 11C Described configuration method.

[0094] In some embodiments, the interposer 1330 is further attached to the package substrate 1360 via the conductive bumps 1362. Furthermore, the conductive bumps 1364 may be disposed on a side of the package substrate 1360 facing away from the interposer 1330 and may serve as I / O terminals of the semiconductor package 1300.

[0095] Please refer to Fig.14 , the electrical connectors 180a, 180b are applied to a semiconductor package 1400. The semiconductor package 1400 includes component dies 1410 arranged side by side and an encapsulation body 1420 that laterally encapsulates the component dies 1410. Figure 1A The device die 110 described, each device die 1410 may include a semiconductor substrate 1412 and a metallization layer 1414 (only one is shown) stacked on an active side of the semiconductor substrate 1412. In some embodiments, an insulating layer 1416 is further formed on the metallization layer 1414 in each device die 1410.

[0096] In addition, the device die 1410 is bonded to a bridge die 1430 disposed below the device die 1410 and extending across the gap between the device die 1410. The bridge die 1430 includes a substrate 1432 (e.g., a semiconductor substrate) and a metallization layer 1434 (only one is shown) stacked on a side of the substrate 1432 facing the device die 1410. The device die 1410 can communicate with each other through lateral conductive paths established in the metallization layer 1434. In some embodiments, the device die 1410 is respectively routed to the other side of the bridge die 1430 via the metallization layer 1434 and the substrate through-hole 1436 passing through the substrate 1432. In addition, according to some embodiments, an insulating layer 1438 is further formed on the metallization layer 1434.

[0097] The electrical connectors 180a and 180b extend along a vertical direction between the metallization layer 1434 of the bridge die 1430 and the metallization layer 1414 of each device die 1410. In the embodiment where the insulating layer 1416 covers the active side of each device die 1410, the electrical connectors 180a and 180b can extend through the insulating layer 1416, respectively. Similarly, in the embodiment where the bridge die 1430 further includes an insulating layer 1438 covering the metallization layer 1434, the electrical connectors 180a and 180b can extend through the insulating layer 1438 to the metallization layer 1434.

[0098] According to some embodiments, the electrical connectors 180a, 180b are located in a bonding layer 1450, wherein the bonding layer 1450 is similar to the reference Figure 1A and Figure 1B The illustrated bonding layer 130. In these embodiments, the polymer layer 1452 of the upper bonding layer 1450 covers the metallization layer 1414 of the device die 1410, and the polymer layer 1454 of the lower bonding layer 1450 covers the metallization layer 1434 of the bridge die 1430. The polymer layers 1452 are respectively bonded to the polymer layers 1434, and the electrical connectors 180a, 180b extend through the polymer layers 1452 and some portions of the polymer layers 1454 bonded to the polymer layers 1452 to establish a conductive path between each device die 1410 and the bridge die 1430.

[0099] It should be understood that the electrical connectors 180a and 180b can be formed into a symmetrical stacked design, as shown in FIG. Figure 1B As an alternative, as described in Fig.10 As described above, the electrical connector 180a can be formed to have an asymmetric stacking design, while the electrical connector 180b can be formed to have a symmetric stacking design. In addition, the electrical connectors 180a and 180b can be arranged in a variety of configurations, such as with reference to FIG. 11A to FIG. 11C Described configuration method.

[0100] Another encapsulant 1460 may laterally encapsulate the bridging die 1430 and the bonding layer 1450 covering the bridging die 1430, and may contact the upper encapsulant 1420 laterally encapsulating the device die 1410 and the covered bonding layer 1450. According to some embodiments, an encapsulant through-hole 1462 is further formed around the bridging die 1430 and passes through the encapsulant 1460 laterally contacting the bridging die 1430 and the covered bonding layer 1450. In these embodiments, a contact feature 1456 may be further formed in the polymer layer 1452 of the bonding layer 1450 covering the device die 1410, and positioned corresponding to the position of the encapsulant through-hole 1462. In this way, the device die 1410 can be routed to the other side of the package 1460 not only through the electrical connectors 180 a , 180 b and the bridge die 1410 , but also through the contact features 1456 and the package through-holes 1462 .

[0101] In some embodiments, the redistribution structure 1470 is further formed on the side of the package 1460 facing away from the device die 1410 to route the substrate through via 1436 and the package through via 1462 of the bridge die 1430. Furthermore, a conductive bump 1472 may be formed on the other side of the redistribution structure 1470 to serve as an I / O terminal of the semiconductor package 1400.

[0102] Please refer to Fig.15 , the electrical connectors 180a, 180b can be applied to a fan-out semiconductor package 1500. The semiconductor package 1500 includes device dies 1510 arranged side by side, and includes an encapsulation body 1520 that laterally encapsulates the device dies 1510. Each device die 1510 may include a semiconductor substrate 1512, and includes active components and metallization layers (neither of which are shown) formed on an active side of the semiconductor substrate 1512. Furthermore, a columnar contact structure 1514 and an insulating layer 1516 surrounding the columnar contact structure 1514 may be provided on the metallization layer (not shown) of each device die 1510, and the encapsulation body 1520 may surround the columnar contact structure 1514 and the insulating layer 1516.

[0103] A redistribution structure 1530 is disposed along one side of the encapsulation structure including the device die 1510 and the encapsulation body 1520. The columnar contact structure 1514 is exposed at the side of the encapsulation structure so that the conductive features 1532 dispersed in the redistribution structure 1530 can be electrically connected to the columnar contact structure 1514 and can be configured to route the columnar contact structure 1514 to the opposite side of the redistribution structure 1530 in a fan-out manner.

[0104] The bridge die 1540 is attached to a side of the redistribution structure 1530 facing away from the device die 1510 via a first group of electrical connections 180a, 180b and may overlap the device die 1510. The bridge die 1540 may include a substrate 1542 (e.g., a semiconductor substrate) and a metallization layer 1544 (only one of which is shown) stacked on the substrate 1542. The first group of electrical connections 180a, 180b extends vertically between the metallization layer 1544 of the bridge die 1540 and the redistribution structure 1530. In this way, the bridge die 1540 can be electrically connected to the pillar contact structure 1514 of the device die 1510 via the first group of electrical connections 180a, 180b and the conductive features 1532 in the redistribution structure 1530, and the device die 1510 can communicate with each other via the lateral conductive paths established in the metallization layer 1544 of the bridge die 1540. In some embodiments, the bridge die 1540 further includes an insulating layer 1546 covering the metallization layer 1544. In these embodiments, the first group of electrical connections 180a, 180b can pass through the insulating layer 1546 to contact the metallization layer 1544.

[0105] In addition, the passive device die 1550 may also be attached to the side of the redistribution structure 1530 facing away from the device die 1510, and may overlap one of the device die 1510. The second group of electrical connectors 180a, 180b may be used to connect the passive device die 1550 to the redistribution structure 1530. The passive device die 1550 may include a substrate 1552 (e.g., a semiconductor substrate) and metallization layers 1554 (only one of which is shown) stacked on the substrate 1552, and the second group of electrical connectors 180a, 180b may extend vertically between the metallization layers 1554 of the passive device die 1550 and the redistribution structure 1530. Thus, the passive device die 1550 can be connected to the pillar contact structure 1514 of one of the device dies 1510 via the second group of electrical connectors 180a, 180b and the conductive features 1532 in the redistribution structure 1530. In some embodiments, the passive device die 1550 further includes an insulating layer 1556 covering the metallization layer 1554. In these embodiments, the second group of electrical connectors 180a, 180b can pass through the insulating layer 1556 to contact the metallization layer 1554.

[0106] According to some embodiments, each group of electrical connectors 180a, 180b is located in a bonding layer 1560, wherein the bonding layer 1560 is similar to the reference Figure 1A and Figure 1BThe illustrated bonding layer 130. In these embodiments, the polymer layer 1562 of one of the upper bonding layers 1560 covers the side of the redistribution structure 1530 facing the bridge die 1540 and the passive device die 1550, and the polymer layer 1564 of the lower bonding layer 1560 covers the metallization layers 1544, 1554 of the bridge die 1540 and the passive device die 1550. The polymer layers 1564 are respectively bonded to the polymer layers 1562, and the electrical connectors 180a, 180b extend through the polymer layers 1564 and some portions of the polymer layers 1562 bonded to the polymer layers 1564 to establish a conductive path between the redistribution structure 1530 to each of the bridge die 1540 and the passive device die 1550.

[0107] In the embodiment where the electrical connectors 180a, 180b are located in the bonding layer 1560, the conductive bumps 1570 as the I / O terminals of the semiconductor package 1500 may be formed on the polymer layer 1562 covering the redistribution structure 1530, and connected to the redistribution structure 1530 via the contact structures 1566 further formed in the polymer layer 1562. The conductive bumps 1570 may be arranged around the bridge die 1540 and the passive device die 1550 and between the bridge die 1540 and the passive device die 1550. In addition, the conductive bumps 1570 may be larger in height / thickness than the bridge die 1540 and the passive device die 1550.

[0108] It should be understood that the electrical connectors 180a and 180b can be formed into a symmetrical stacked design, as shown in FIG. Figure 1B As an alternative, as described in Fig.10 As described above, the electrical connector 180a can be formed to have an asymmetric stacking design, while the electrical connector 180b can be formed to have a symmetric stacking design. In addition, the electrical connectors 180a and 180b can be arranged in a variety of configurations, such as with reference to FIG. 11A to FIG. 11C Described configuration method.

[0109] Please refer to Fig.16 The electrical connectors 180a and 180b can be applied to a more complex semiconductor package 1600. The semiconductor package 1600 includes a device die 1602 and a bridge die 1604 arranged at a first height. Each bridge die 1604 can be located between adjacent device die 1602, and the encapsulation body 1606 laterally encapsulates the device die 1602 and the bridge die 1604.

[0110] In addition, the semiconductor package 1600 further includes a device die 1608 at a second height, wherein the second height is lower than the first height. The bridging die 1604 at the first height can be respectively positioned to overlap the adjacent device die 1608 at the second height, and the adjacent device die 1608 at the second height can be bridged to each other by the overlapping bridging die 1604. In addition, another encapsulation body 1610 laterally encapsulates the device die 1608 at the second height. Furthermore, the encapsulation body through hole 1612 can be disposed around the device die 1608 and penetrate the encapsulation body 1610.

[0111] The device chips 1602 and 1608 may be similar to the reference Figure 1A The device die 110 described in reference Fig.13 Each component chip 1310 described, refer to Fig.14 Each component die 1410 described or referred to Fig.15 The component die 1510 described above. In addition, the bridge die 1604 can be similar to the reference Fig.14 The bridging die 1430 described or referred to Fig.15 The bridge die 1540 is depicted. For the sake of brevity, the details of the device die 1602, 1608 and the bridge die 1604 are not repeated unless they are related to other components.

[0112] The redistribution structure 1614 covers the device die 1608, the encapsulation 1610, and the encapsulation through-hole 1612 at the second height, and extends below the device die 1602, the bridge die 1604, and the encapsulation 1606 at the first height. The conductive features in the redistribution structure 1614 can be designed to route the device die 1608 and the encapsulation through-hole 1612 at the second height. The electrical connectors 180a, 180b can stand on the redistribution structure 1614 and connect the device die 1602 and the bridge die 1604 at the first height to the conductive features in the redistribution structure 1614. In this way, the device die 1602 at the first height can be electrically connected to the device die 1608 and the encapsulation through-hole 1612 at the second height via the electrical connectors 180a, 180b and the conductive features in the redistribution structure 1614. In addition, the device die 1608 at the second height can also be electrically connected to the bridge die 1604 at the first height via the electrical connections 180 a , 180 b and the conductive features in the redistribution structure 1614 .

[0113] According to some embodiments, the electrical connectors 180a, 180b are located in the bonding layers 1616, 1618, wherein the bonding layers 1616, 1618 are similar to those of reference Figure 1A and Figure 1BThe illustrated bonding layer 130. In these embodiments, the polymer layer 1620 of the bonding layer 1616 covers the device die 1602 and the bridge die 1604, respectively, and is laterally encapsulated by the encapsulation body 1606. In addition, the polymer layer 1622 of the bonding layer 1618 extends on the redistribution structure 1614. The polymer layer 1620 is respectively bonded to the polymer layer 1622, and the electrical connectors 180a, 180b extend through the polymer layer 1620 and some portions of the polymer layer 1622 bonded to the polymer layer 1620 to establish a conductive path between the redistribution structure 1614 and each of the device die 1602 and the bridge die 1604.

[0114] In other embodiments, the electrical connectors 180a and 180b extend between the redistribution structure 1614 and each device die 1602 and the bridge die 1604, and are encapsulated by the bottom filler (rather than being encapsulated by the polymer layers 1620 and 1622). Furthermore, the electrical connectors 180a and 180b can be formed into a symmetrical stacking design, as shown in FIG. Figure 1B As an alternative, as described in Fig.10 As described above, the electrical connector 180a can be formed to have an asymmetric stacking design, while the electrical connector 180b can be formed to have a symmetric stacking design. In addition, the electrical connectors 180a and 180b can be arranged in a variety of configurations, such as with reference to FIG. 11A to FIG. 11C Described configuration method.

[0115] In order to connect the device die 1608 and the encapsulation through-via 1612 at the second height to the conductive bump 1624 (and the passive device die 1626) at a third height lower than the second height, a redistribution structure 1628 is formed along the bottom side of the encapsulation structure including the device die 1608, the encapsulation 1610, and the encapsulation through-via 1612. The device die 1608 can be attached to the redistribution structure 1628 via the conductive bump 1630, and the encapsulation through-via 1612 can stand on the redistribution structure 1628. The conductive features in the redistribution structure 1628 route the conductive bump 1630 and the encapsulation through-via 1612 to the conductive bump 1624 (and the passive device die 1626) at the other side of the redistribution structure 1628. In this way, the device die 1602 at the first height can be routed to the conductive bump 1624 via the electrical connections 180a, 180b, the redistribution structure 1614, the package through-hole 1612, and the redistribution structure 1628. In addition, the device die 1608 at the second height can be connected to the conductive bump 1624 (and the passive device die 1626) via the redistribution structure 1614, the package through-hole 1612, and the redistribution structure 1628.

[0116] In some embodiments, at least one device die 1608 at the second height is provided with a through-substrate via 1632. In these embodiments, the device die 1602 at the first height can be routed to the conductive bump 1624 (and the passive device die 1626) via the electrical connectors 180a, 180b, the redistribution structure 1614, the through-substrate via 1632 in the device die 1608, and the additional conductive path established by the redistribution structure 1628. In addition, the device die 1608 at the second height can be connected to the conductive bump 1624 (and the passive device die 1626) via the additional conductive path established by the through-substrate via 1632 and the redistribution structure 1628.

[0117] Furthermore, in some embodiments, the encapsulation structure including the device die 1602, the bridge die 1604 and the encapsulation body 1606 at the first height is attached to the overlying heat dissipation substrate 1634, such as a semiconductor substrate. The bonding layer 1636 may extend between the encapsulation structure and the heat dissipation substrate 1634 to enhance the bonding between the two.

[0118] In summary, electrical connectors with different sizes and different stacking designs are used to transmit various signals between vertically spaced package components. Specifically, the electrical connectors of the first group have a first critical width and a first pitch, and include a first metal layer composed of a first metal material and a solder joint disposed between the first metal layers. Compared to the electrical connectors of the first group, the electrical connectors of the second group have a second critical width and a second pitch (smaller than the first critical width and the first pitch, respectively), and further include a second metal layer composed of a second metal material. In this way, the solder joints in each electrical connector with a shorter width and a shorter pitch contact the thinner first metal layer (composed of the first metal material), which is the material source of the intermetallic compound causing lateral shrinkage. Based on the reduction of the material source causing lateral shrinkage, severe necking or fracture of the electrical connector with a shorter width and a shorter pitch can be effectively prevented. Therefore, the reliability of the electrical connector with a shorter width and a shorter pitch can be improved, and better communication between the package components on the opposite sides of the electrical connector can be ensured. Furthermore, during the manufacturing process, the electrical connectors with different sizes and different stacking designs are formed separately, so that the upper and lower halves of each electrical connector with shorter width and shorter pitch can be ensured to have sufficient thickness, thereby effectively avoiding the joint failure of the electrical connector with shorter width and shorter pitch.

[0119] It should be understood that other features and processes may also be included. For example, a test structure may be included to help verify and test the 3D package (or 3DIC). The test structure may, for example, include a test pad formed in a redistribution layer or on a substrate, which is used to implement the testing of the 3D package (or 3DIC), the use of probes and / or probe cards, and the like. Verification tests may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be combined with verification techniques including intermediate verification of known good dies to improve yield and reduce costs.

[0120] One aspect of the utility model provides a semiconductor package, comprising: a first component die; a second component die, stacked on the first component die; and a plurality of first electrical connectors and a plurality of second electrical connectors, arranged between the first component die and the second component die, wherein the first pitch of the plurality of first electrical connectors is greater than the second pitch of the plurality of second electrical connectors, the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and a plurality of first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material.

[0121] In some embodiments, the at least one second metal layer in each second connector includes two second metal layers extending between two adjacent layers of the multilayer first metal layers on one side of the solder joint, and the multilayer first metal layers in each second electrical connector are thinner than each first metal layer in each first electrical connector. In some embodiments, the at least one second metal layer in each second connector includes a single second metal layer extending between two adjacent layers of the multilayer first metal layers on one side of the solder joint, and the plurality of the multilayer first metal layers in each second electrical connector on the side of the solder joint are thinner than each first metal layer in each first connector. In some embodiments, the first metal material includes copper, and the second metal material includes nickel, cobalt, iron, or a combination thereof. In some embodiments, each of the plurality of first electrical connectors and the plurality of second electrical connectors further includes a multilayer seed layer at opposite ends. In some embodiments, the semiconductor package further comprises: a first polymer layer extending along the surface of the first component die; and a second polymer layer extending along the surface of the second component die and bonded to the first polymer layer, wherein the plurality of first electrical connectors and the plurality of second electrical connectors extend through the first polymer layer and the second polymer layer. In some embodiments, the semiconductor package further comprises: a bottom filler filled between the first component die and the second component die and laterally surrounding the plurality of first electrical connectors and the plurality of second electrical connectors. In some embodiments, each of the plurality of first connectors and the plurality of second electrical connectors has an upper half and a lower half narrower than the upper half. In some embodiments, the first critical width of each first electrical connector is greater than the second critical width of each second electrical connector. In some embodiments, the plurality of second electrical connectors are arranged around the array of the plurality of first electrical connectors. In some embodiments, the plurality of second electrical connectors are surrounded by the plurality of first electrical connectors.

[0122] Another aspect of the present invention provides a semiconductor package, comprising: a first component die; a second component die stacked on the first component die; a first polymer layer disposed on the surface of the first component die; a second polymer layer disposed on the surface of the second component die and bonded to the first polymer layer; a plurality of first electrical connectors and a plurality of second electrical connectors extending through the first polymer layer and the second polymer layer, wherein the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and a plurality of first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material; a first encapsulation body disposed on the first component die and laterally encapsulating the second component die; and a second encapsulation body laterally encapsulating the first encapsulation body and the first component die.

[0123] In some embodiments, the first component die comprises: a semiconductor substrate; a multi-layer front metallization layer extending along the active side of the semiconductor substrate; a multi-layer back metallization layer extending along the back side of the semiconductor substrate; and a plurality of substrate through-holes extending through the semiconductor substrate, wherein the plurality of first electrical connectors and the plurality of second electrical connectors are located on the multi-layer back metallization layer. In some embodiments, the first component die comprises: a semiconductor substrate; a multi-layer front metallization layer extending along the active side of the semiconductor substrate; and a plurality of substrate through-holes extending through at least a portion of the semiconductor substrate, wherein the plurality of first electrical connectors and the plurality of second electrical connectors are located on the multi-layer front metallization layer. In some embodiments, the semiconductor package further comprises: a first redistribution structure extending below the second encapsulation body and the first component die; and a plurality of conductive bumps disposed on the bottom side of the first redistribution structure. In some embodiments, the semiconductor package further includes: a plurality of package through-holes, which are erected on the first redistribution structure and located around the first package and the first component die, and pass through at least a portion of the second package; and a second redistribution structure, which extends over the second package, the package through-holes, the first package and the second component die.

[0124] Another aspect of the utility model provides a semiconductor package, comprising: a first package component; a second package component, which is spaced apart from the first package component in a vertical direction; and a plurality of first electrical connectors and a plurality of second electrical connectors, which are arranged between the first package component and the second package component and connect the first package component and the second package component to each other, wherein the first critical width of each first electrical connector is greater than the second critical width of each second electrical connector, the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and multiple first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material.

[0125] In some embodiments, a first pitch of the plurality of first electrical connectors is greater than a second pitch of the plurality of second electrical connectors. In some embodiments, the first package component is a component die, and the second package component is another component die, an interposer, a bridge die, or a rewiring structure. In some embodiments, the first package component is a bridge die or a passive component die, and the second package component is a rewiring structure.

[0126] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, characterized in that: include: a first component die; a second component die, stacked on the first component die; as well as A plurality of first electrical connectors and a plurality of second electrical connectors are disposed between the first component grain and the second component grain, wherein a first pitch of the plurality of first electrical connectors is greater than a second pitch of the plurality of second electrical connectors, the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and a plurality of first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material.

2. The semiconductor package according to claim 1, wherein: The at least one second metal layer in each second connecting member includes two second metal layers respectively extending between two adjacent ones of the multiple layers of first metal layers on one side of the solder joint, and the multiple layers of first metal layers in each second electrical connecting member are respectively thinner than each first metal layer in each first electrical connecting member.

3. The semiconductor package according to claim 1, wherein: The at least one second metal layer in each second connecting member includes a single second metal layer extending between two adjacent ones of the multiple layers of first metal layers located on one side of the solder joint, and multiple ones of the multiple layers of first metal layers in each second electrical connecting member located on the side of the solder joint are respectively thinner than each first metal layer in each first connecting member.

4. The semiconductor package according to claim 1, wherein: Also includes: a first polymer layer extending along a surface of the first component die; and The second polymer layer extends along the surface of the second device die and is bonded to the first polymer layer, wherein the plurality of first electrical connections and the plurality of second electrical connections extend through the first polymer layer and the second polymer layer.

5. The semiconductor package according to claim 1, wherein: Also includes: The bottom filling member is filled between the first component die and the second component die and laterally surrounds the first electrical connection members and the second electrical connection members.

6. The semiconductor package according to claim 1, wherein: Each of the plurality of first electrical connectors and the plurality of second electrical connectors has an upper half and a lower half narrower than the upper half. 7 . The semiconductor package of claim 1 , wherein a first critical width of each of the first electrical connectors is greater than a second critical width of each of the second electrical connectors.

8. A semiconductor package, characterized in that: include: a first component die; A second component die is stacked on the first component die; A first polymer layer is disposed on the surface of the first component die; A second polymer layer is disposed on the surface of the second element die and bonded to the first polymer layer; A plurality of first electrical connectors and a plurality of second electrical connectors extending through the first polymer layer and the second polymer layer, wherein the plurality of first electrical connectors and the plurality of second electrical connectors respectively include a solder joint and a plurality of first metal layers composed of a first metal material located on opposite sides of the solder joint, and each second connector further includes at least one second metal layer composed of a second metal material; A first encapsulation body is disposed on the first component die and laterally encapsulates the second component die; as well as The second encapsulation body laterally encapsulates the first encapsulation body and the first component die.

9. A semiconductor package, characterized in that: include: a first packaging component; a second packaging component, spaced apart from the first packaging component in a vertical direction; as well as A plurality of first electrical connectors and a plurality of second electrical connectors are arranged between the first packaging component and the second packaging component and connect the first packaging component and the second packaging component to each other, wherein the first critical width of each first electrical connector is greater than the second critical width of each second electrical connector, the plurality of first electrical connectors and the plurality of second electrical connectors respectively include solder joints and multiple first metal layers composed of a first metal material located on opposite sides of the solder joints, and each second connector further includes at least one second metal layer composed of a second metal material.

Images