Chip test fixture
By designing chip test fixtures, using the combination of adapter and positioning components, the problems of high testing costs and complex operation in the prior art are solved, and the reuse of adapter and simplification of test operations are achieved.
Patent Information
- Application Number
- CN202421655802.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-07-12
AI Technical Summary
In the prior art, when testing BGA packaged memory, it is necessary to use non-reusable adapters, resulting in high testing costs and complex operation.
A chip test fixture is designed, including adapters and positioning components. The adapter is provided with a conductive terminal set in the thickness direction of its own, and the positioning assembly realizes positioning and connection between the chip to be tested and the packaging substrate through the pairing of the first positioning member and the second positioning member.
The reuse of adapters is realized, testing operations are simplified, and testing costs and technical difficulties are reduced.
Smart Images
Figure CN222913721U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of encapsulated chip testing, and particularly relates to a chip testing fixture. Background Art
[0002] Due to the rapid development of integration technology, BGA (Ball Grid Array) packaging with a smaller volume has been proposed. Compared with traditional packaged memory, the memory using this packaging design has a higher memory capacity under the same volume. When testing BGA-packaged memory, since the memory pins of the BGA package are directly soldered to the PCB board, it is not feasible to directly lead out the signals from the pins for testing. Existing technologies usually use an interposer as an intermediate medium between the PCB board and the memory chip to lead the signals to be tested to the interposer, thereby realizing the signal transmission between the memory chip and the PCB board.
[0003] However, the interposer used in the existing technology needs to be soldered to the PCB board first, and then the memory chip is soldered to the interposer. The interposer cannot be reused, and the testing cost is relatively high. Moreover, during the soldering process, operations such as ball planting are required. These soldering operations are not successful at one time and need to be repeated multiple times to connect the signal channels between the memory chip, the interposer, and the PCB board. The operation is complex and the technical difficulty is relatively high. Summary of the Utility Model
[0004] The embodiments of this application provide a chip testing fixture to reduce the testing cost and the technical difficulty of testing.
[0005] The embodiments of this application provide a chip testing fixture, which includes: an interposer, the interposer includes a first surface layer and a second surface layer that are oppositely arranged along the thickness direction of the interposer itself and are exposed to the outside. The first surface layer is provided with a first conductive terminal group, and the second surface layer is provided with a second conductive terminal group. One of the first conductive terminal group and the second conductive terminal group is correspondingly arranged with the first solder joint of the chip to be tested, and the other is correspondingly arranged with the second solder joint of the packaging substrate; and a positioning component, including a separately arranged first positioning member and a second positioning member; the first positioning member can be connected to the packaging substrate, the first positioning member includes a first connecting portion and a first clamping groove, and the first clamping groove is used for clamping the interposer; the second positioning member includes a second connecting portion and a second clamping groove, and the second clamping groove can clamp the chip to be tested; wherein, in the testing state, the first positioning member and the second positioning member are paired through the first connecting portion and the second connecting portion to position the interposer between the chip to be tested and the packaging substrate, and enable one of the first conductive terminal group and the second conductive terminal group to be correspondingly connected to the first solder joint, and the other to be correspondingly connected to the second solder joint.
[0006] Optionally, the first connection portion and the second connection portion are both connection holes; in a test state, the first connection portion and the second connection portion are arranged opposite to each other along the thickness direction so that the first positioning member and the second positioning member are matched.
[0007] Optionally, the adapter includes a third connection portion, the third connection portion penetrates the adapter along the thickness direction, and in a test state, the first connection portion, the third connection portion and the second connection portion are arranged opposite to each other in sequence along the thickness direction.
[0008] Optionally, the first positioning member and the adapter are connected by a first fixing member passed through the first connecting part and the third connecting part, and the adapter and the second positioning member are connected by a second fixing member passed through the second connecting part and the third connecting part; or the first positioning member, the adapter and the second positioning member are connected by a third fixing member passed through the first connecting part, the second connecting part and the third connecting part at the same time.
[0009] Optionally, a clamping portion and a recess are provided on one side of the adapter away from the second positioning member in the thickness direction, the recess is arranged around at least part of the circumference of the clamping portion, the clamping portion is clamped in the first clamping groove, and the first positioning member is at least partially accommodated in the recess.
[0010] Optionally, the first clamping slot matches at least a portion of the chip to be tested so that the first clamping slot can clamp the chip to be tested; and / or the second clamping slot matches at least a portion of the chip to be tested so that the second clamping slot can clamp the chip to be tested.
[0011] Optionally, the first positioning member includes a first beam, a second beam and a third beam, the first beam and the second beam are respectively connected to two ends of the third beam and are arranged parallel to the third beam, and a first positioning groove is formed between the first beam, the second beam and the third beam.
[0012] Optionally, the second positioning member further includes a limiting portion, which is disposed on a side of the second clamping slot away from the adapter along the thickness direction and is used to limit the chip to be tested clamped in the second clamping slot along the thickness direction.
[0013] Optionally, the first conductive terminal group includes a first signal terminal, the second conductive terminal group includes a second signal terminal, and the first signal terminal and the second signal terminal are connected by a signal line; the adapter also includes a test terminal, the test terminal is arranged on one of the first surface layer and the second surface layer, and is connected to the signal line.
[0014] Optionally, the first positioning member and the second positioning member are both insulating members.
[0015] The chip test fixture provided by the embodiment of the present application includes an adapter and a positioning component. The first surface layer and the second surface layer of the adapter along its thickness direction are respectively provided with a first conductive terminal group and a second conductive terminal group, and the first conductive terminal group and the second conductive terminal group are respectively arranged corresponding to the first solder joints of the chip to be tested and the second solder joints of the packaging substrate. The positioning component includes a separately arranged first positioning member and a second positioning member. The first positioning member can be connected to the packaging substrate and includes a first connecting portion and a first clamping groove capable of clamping the adapter, and the positioning between the adapter and the packaging substrate can be realized through the first positioning member. The second positioning member includes a second connecting portion and a second clamping groove capable of clamping the chip to be tested. In the test state, the first positioning member and the second positioning member are paired through the first connecting portion and the second connecting portion, so that the adapter is positioned between the chip to be tested and the packaging substrate, and one of the first conductive terminal group and the second conductive terminal group is correspondingly connected to the first solder joints of the chip to be tested, and the other is correspondingly connected to the second solder joints of the packaging substrate. By providing conductive terminal groups on both the first surface layer and the second surface layer of the adapter, and realizing the corresponding connection between the solder joints of the packaging substrate and the solder joints of the chip to be tested through the pairing of the first positioning member and the second positioning member, the chip test fixture provided by the embodiment of the present application, the packaging substrate and the chip to be tested only need to be assembled to test the chip to be tested, without the need to weld the adapter, realizing the reuse of the adapter, simplifying the test operation, and reducing the test cost and test difficulty. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0017] Figure 1 FIG. is a schematic structural diagram of a chip test fixture provided by an embodiment of the present application.
[0018] Figure 2 is Figure 1 a schematic exploded structural diagram of the provided chip test fixture.
[0019] Figure 3 is Figure 1 a schematic structural diagram of the provided chip test fixture assembled with the chip to be tested and the packaging substrate in the test state.
[0020] Figure 4 is Figure 1 a schematic exploded structural diagram of the provided chip test fixture, the chip to be tested and the packaging substrate.
[0021] Figure 5 isFigure 1 Exploded structure schematic diagram of the provided chip test fixture, the chip to be tested, and the packaging substrate in another orientation.
[0022] Figure 6 is Figure 1 Cross-sectional structure schematic diagram of the chip test fixture, the chip to be tested, and the packaging substrate after assembly.
[0023] Figure 7 Insertion loss simulation diagram of the signal transmission route without stubs and the existing signal transmission route with stubs provided by the embodiments of the present application.
[0024] Figure 8 Time-domain reflection simulation diagram of the signal transmission route without stubs and the existing signal transmission route with stubs provided by the embodiments of the present application. Detailed implementation manners
[0025] The embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solutions of the present application more clearly, and thus are only examples and cannot be used to limit the protection scope of the present application.
[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above accompanying drawings are intended to cover non-exclusive inclusion.
[0027] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order, or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality" is more than two, unless otherwise specifically and clearly defined.
[0028] Referring to "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.
[0029] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, m and / or n can represent three situations: m exists alone, m and n exist simultaneously, and n exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.
[0030] In the description of the embodiments of the present application, the term "plurality" refers to two or more (including two).
[0031] In the description of the embodiments of the present application, the orientation or positional relationship indicated by technical terms such as "vertical", "horizontal", "top", "bottom", "inner", "outer", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.
[0032] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.
[0033] In the embodiments of the present application, "parallel" includes not only the case of absolute parallelism, but also the case of approximately parallelism conventionally recognized in engineering; at the same time, "perpendicular" also includes not only the case of absolute perpendicularity, but also the case of approximately perpendicularity conventionally recognized in engineering. Exemplarily, if the included angle between two directions is 85° - 90°, the two directions can be considered perpendicular; if the included angle between two directions is 0° - 5°, the two directions can be considered parallel.
[0034] The embodiments will be described in detail below with reference to the drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0035] Figure 1 is a schematic structural diagram of a chip test fixture provided by an embodiment of the present application, Figure 2 is Figure 1 a schematic exploded view of the chip test fixture provided, Figure 3 is Figure 1 a schematic structural diagram of the chip test fixture assembled with the chip to be tested and the packaging substrate in the test state, Figure 4 isFigure 1 Exploded structural schematic diagram of the provided chip test fixture, the chip to be tested, and the packaging substrate Figure 5 is Figure 1 Exploded structural schematic diagram of the provided chip test fixture, the chip to be tested, and the packaging substrate from another perspective. Referring to Figures 1 to 5 , the chip test fixture 1 provided in the embodiment of the present application includes an adapter 10 and a positioning component 20.
[0036] The adapter 10 includes a first surface layer 11 and a second surface layer 12 that are oppositely arranged along the thickness direction X of itself and exposed to the outside. The first surface layer 11 is provided with a first conductive terminal group 13, and the second surface layer 12 is provided with a second conductive terminal group 14. One of the first conductive terminal group 13 and the second conductive terminal group 14 is correspondingly arranged with the first solder joint 201 of the chip 2 to be tested, and the other is correspondingly arranged with the second solder joint 301 of the packaging substrate 3. The positioning component 20 includes a separately provided first positioning member 21 and a second positioning member 22. The first positioning member 21 can be connected to the packaging substrate 3. The first positioning member 21 includes a first connecting portion 211 and a first clamping groove 212, and the first clamping groove 212 is used for clamping the adapter 10. The second positioning member 22 includes a second connecting portion 221 and a second clamping groove 222, and the second clamping groove 222 can clamp the chip 2 to be tested. Wherein, in the test state, the first positioning member 21 and the second positioning member 22 are paired through the first connecting portion 211 and the second connecting portion 221 to position the adapter 10 between the chip 2 to be tested and the packaging substrate 3, and to enable one of the first conductive terminal group 13 and the second conductive terminal group 14 to be correspondingly connected to the first solder joint 201, and the other to be correspondingly connected to the second solder joint 301.
[0037] The first surface layer 11 and the second surface layer 12 are respectively two surface layers exposed to the outside in the thickness direction of the adapter 10 itself. Exemplarily, the first surface layer 11 and the second surface layer 12 can be respectively the top layer (top layer) and the bottom layer (bottom layer) of the adapter 10. The adapter 10 may further include other layers sandwiched between the first surface layer 11 and the second surface layer 12 along its thickness direction.
[0038] The "corresponding arrangement" in the embodiment of the present application means that parameters such as the quantity, arrangement method, and spacing are correspondingly the same, so that when the packaging substrate 3 and the chip 2 to be tested are respectively on both sides of the thickness direction of the adapter 10, one of the first conductive terminal group 13 and the second conductive terminal group 14 can be correspondingly connected to the first solder joint 201 one by one, and the other can be correspondingly connected to the second solder joint 301 one by one.
[0039] The first conductive terminal group 13 may include a plurality of first conductive terminals, and the second conductive terminal group 14 may include a plurality of second conductive terminals. Correspondingly, there are a plurality of first solder joints 201 on the chip 2 to be tested, and a plurality of second solder joints 301 on the packaging substrate 3. The arrangement of the plurality of first conductive terminals is the same as that of one of the first solder joints 201 and the second solder joints 301, and the arrangement of the plurality of second conductive terminals is the same as that of the other of the first solder joints 201 and the second solder joints 301.
[0040] It can be understood that the first solder joints 201 on the chip 2 to be tested are arranged corresponding to the second solder joints 301 on the packaging substrate 3, and the first solder joints 201 and the second solder joints 301 can be connected in a one-to-one correspondence. Therefore, the arrangement of the first solder joints 201 and the second solder joints 301 is the same. Correspondingly, the arrangement of the plurality of first conductive terminals and the arrangement of the plurality of second conductive terminals are also the same.
[0041] The first conductive terminal group 13 can be formed by reflow soldering with conductive silicone rubber on the first surface layer 11. The second conductive terminal group 14 can be formed by reflow soldering with conductive silicone rubber on the second surface layer 12.
[0042] Optionally, the chip 2 to be tested can adopt ball grid array packaging (also known as BGA packaging), and the first solder joints 201, the second solder joints 301, the plurality of first conductive terminals and the plurality of second conductive terminals are all arranged in an array.
[0043] Optionally, the chip 2 to be tested can be a memory chip with BGA packaging. The packaging substrate 3 can be a PCB circuit board.
[0044] In the non-test state, the first positioning member 21 and the second positioning member 22 can be independently arranged respectively. In the test state, the first positioning member 21 is connected to the packaging substrate 3, and the chip 2 to be tested is clamped on the second positioning member 22. The first positioning member 21 and the second positioning member 22 are paired through the first connecting portion 211 and the second connecting portion 221 to form a positioning assembly 20 with a positioning function. After the first positioning member 21 and the second positioning member 22 are paired, the relative positional relationship among the adapter 10, the first positioning member 21 and the second positioning member 22 is uniquely determined, so that one of the first conductive terminal group 13 and the second conductive terminal group 14 is connected corresponding to the first solder joints 201 of the chip 2 to be tested clamped on the second positioning member 22, and the other is connected corresponding to the second solder joints 301 of the packaging substrate 3 connected to the first positioning member 21.
[0045] The chip test fixture 1 provided by the embodiment of the present application includes an adapter 10 and a positioning component 20. The first surface layer 11 and the second surface layer 12 of the adapter 10 along its own thickness direction X are respectively provided with a first conductive terminal group 13 and a second conductive terminal group 14, and the first conductive terminal group 13 and the second conductive terminal group 14 are respectively arranged corresponding to the first solder joint 201 of the chip 2 to be tested and the second solder joint 301 of the packaging substrate 3. The positioning component 20 includes a separately arranged first positioning member 21 and a second positioning member 22. The first positioning member 21 can be connected to the packaging substrate 3 for use, and includes a first connecting portion 211 and a first clamping groove 212 capable of clamping the adapter 10. The positioning between the adapter 10 and the packaging substrate 3 can be realized through the first positioning member 21. The second positioning member 22 includes a second connecting portion 221 and a second clamping groove 222 capable of clamping the chip 2 to be tested. In the test state, the first positioning member 21 and the second positioning member 22 are paired through the first connecting portion 211 and the second connecting portion 221, so that the adapter 10 is positioned between the chip 2 to be tested and the packaging substrate 3, and one of the first conductive terminal group 13 and the second conductive terminal group 14 is correspondingly connected to the first solder joint 201 of the chip 2 to be tested, and the other is correspondingly connected to the second solder joint 301 of the packaging substrate 3. By providing conductive terminal groups on both the first surface layer 11 and the second surface layer 12 of the adapter 10 and realizing the corresponding connection between the solder joints of the packaging substrate 3 and the solder joints of the chip 2 to be tested through the pairing of the first positioning member 21 and the second positioning member 22, only the chip test fixture 1, the packaging substrate 3 and the chip 2 to be tested provided by the embodiment of the present application need to be assembled to test the chip 2 to be tested, without welding the adapter 10, realizing the reuse of the adapter 10, simplifying the test operation, and reducing the test cost and test difficulty.
[0046] In some embodiments, both the first connecting portion 211 and the second connecting portion 221 are connecting holes. In the test state, the first connecting portion 211 and the second connecting portion 221 are arranged opposite to each other along the thickness direction X, so that the first positioning member 21 and the second positioning member 22 are paired.
[0047] When pairing the first positioning member 21 and the second positioning member 22, the first connecting portion 211 and the second connecting portion 221 can be aligned along the thickness direction X, and the operation is simple.
[0048] Further, the first connecting portion 211 and the second connecting portion 221 can be set as connecting holes with special shapes. Through the matching of the connecting hole shapes, the first positioning member 21 and the second positioning member 22 can be positioned more precisely, thereby improving the pairing effect between the first positioning member 21 and the second positioning member 22. Exemplarily, the first connecting portion 211 and the second connecting portion 221 can be set as triangular, quadrilateral, elliptical and other shapes. Of course, in some embodiments, the first connecting portion 211 and the second connecting portion 221 can also be circular connecting holes.
[0049] The first connecting portion 211 can penetrate the first positioning member 21 along the thickness direction of the first positioning member 21, and the second connecting portion 221 can penetrate the second positioning member 22 along the thickness direction of the second positioning member 22, so as to facilitate the alignment operation of the first connecting portion 211 and the second connecting portion 221. The thickness directions of the first positioning member 21 and the second positioning member 22 are the same as the thickness direction of the adapter 10, both being the thickness direction X.
[0050] The number of the first connecting portion 211 and the second connecting portion 221 can be one each, or can be multiple each. The numbers of the first connecting portion 211 and the second connecting portion 221 correspond to each other.
[0051] In some embodiments, the adapter 10 includes a third connecting portion 15. The third connecting portion 15 penetrates the adapter 10 along the thickness direction X. In the test state, the first connecting portion 211, the third connecting portion 15 and the second connecting portion 221 are sequentially arranged opposite to each other along the thickness direction X.
[0052] When pairing the first positioning member 21 and the second positioning member 22, first snap the adapter 10 into the first clamping groove 212 of the first positioning member 21. Then align the third connecting portion 15 of the adapter 10 with the first connecting portion 211 of the first positioning member 21 along the thickness direction X. Finally, install the second positioning member 22 on the side of the adapter 10 away from the first positioning member 21, and align the second connecting portion 221 of the second positioning member 22 with the third connecting portion 15 of the adapter 10 along the thickness direction X. The first connecting portion 211 and the second connecting portion 221 can be indirectly aligned through the third connecting portion 15.
[0053] In the embodiment of the present application, by providing the third connecting portion 15 on the adapter 10, the first connecting portion 211 and the second connecting portion 221 can be indirectly aligned through the third connecting portion 15, which is convenient for positioning the adapter 10 after the pairing of the first positioning member 21 and the second positioning member 22 is completed.
[0054] The third connection portion 15 may be a connection hole that penetrates the adapter 10 along the thickness direction X. The connection hole shape of the third connection portion 15 is the same as that of the first connection portion 211 and the second connection portion 221 , so as to more accurately position the adapter 10 .
[0055] The number of the third connection parts 15 may be one or more, and the number of the third connection parts 15 is the same as the number of the first connection parts 211 and the second connection parts 221 .
[0056] In some embodiments, the first positioning member 21 and the adapter 10 are connected by a first fixing member passing through the first connecting portion 211 and the third connecting portion 15 , and the adapter 10 and the second positioning member 22 are connected by a second fixing member passing through the second connecting portion 221 and the third connecting portion 15 .
[0057] During the test, after the third connection portion 15 of the adapter 10 is aligned with the first connection portion 211 of the first positioning member 21 along the thickness direction X, the adapter 10 and the first positioning member 21 can be fixedly connected by the first fixing member to prevent the adapter 10 and the first positioning member 21 from being misaligned during the subsequent assembly process. After the second connection portion 221 of the second positioning member 22 is aligned with the third connection portion 15 of the adapter 10 along the thickness direction X, the adapter 10 and the second positioning member 22 can be fixedly connected by the second fixing member to prevent the adapter 10 and the second positioning member 22 from being misaligned during the test, thereby ensuring the smooth progress of the test and facilitating the improvement of the test efficiency.
[0058] In other embodiments, the first positioning member 21, the adapter 10 and the second positioning member 22 are also connected to the housing through a third fixing member that is simultaneously inserted into the first connection portion 211, the second connection portion 221 and the third connection portion 15. That is, after the first connection portion 211, the third connection portion 15 and the second connection portion 221 are aligned in sequence along the thickness direction X, the third fixing member is inserted into the first connection portion 211, the second connection portion 221 and the third connection portion 15, and the first connection portion 211, the second connection portion 221 and the third connection portion 15 are simultaneously fixedly connected, which can also prevent the adapter 10 and the first positioning member 21, and the adapter 10 and the second positioning member 22 from being misaligned during the test process, ensuring the smooth progress of the test and helping to improve the test efficiency.
[0059] The first fixing member, the second fixing member and the third fixing member can all be fasteners such as screws and bolts.
[0060] In some embodiments, a clamping portion 16 and a recess 17 are provided on the side of the adapter 10 away from the second positioning member 22 along the thickness direction X, and the recess 17 is arranged around at least part of the circumference of the clamping portion 16. The clamping portion 16 is clamped in the first clamping groove 212, and the first positioning member 21 is at least partially accommodated in the recess 17.
[0061] The shape of the first clamping slot 212 matches the shape of the clamping portion 16, so as to reduce the relative movement of the adapter 10 and the first positioning member 21 in at least some other directions perpendicular to the thickness direction X after the clamping portion 16 is clamped in the first clamping slot 212, thereby improving the positioning effect of the first positioning member 21 on the adapter 10.
[0062] Exemplarily, the first clamping slot 212 can be a square slot, and the clamping portion 16 can be a square body. They have a plurality of mating interfaces perpendicular to each other, and the clamping effect of the adapter 10 is better.
[0063] The first positioning member 21 is at least partially received in the recess 17, and the first positioning member 21 can be abutted against the clamping portion 16, so as to position the adapter 10 in the abutting direction of the two, thereby improving the positioning accuracy of the adapter 10.
[0064] In some embodiments, the first positioning member 21 may include a first beam 215, a second beam 213 and a third beam 214. The first beam 215 and the second beam 213 are respectively connected to both ends of the third beam 214 and are arranged in parallel with respect to the third beam 214. A first clamping slot 212 is formed by enclosing between the first beam 215, the second beam 213 and the third beam 214.
[0065] The first beam 215 and the second beam 213 are arranged oppositely along the first direction Y. The first beam 215 and the second beam 213 both extend along the second direction Z. The first direction Y, the second direction Z and the thickness direction X are perpendicular to each other in pairs. The third beam 214 is connected between the ends of the first beam 215 and the second beam 213 along the second direction Z, so as to form a first clamping slot 212 by enclosing between the first beam 215, the second beam 213 and the third beam 214. The first connecting portion 211 can be arranged on the third beam 214.
[0066] The first beam 215, the second beam 213 and the third beam 214 are connected to form a substantially U-shaped structure, and a first clamping slot 212 is formed inside the U-shaped structure. The first clamping slot 212 is substantially square.
[0067] The clamping portion 16 can be arranged on the side of the adapter 10 facing the second layer along the thickness direction X, and at least some of the second conductive terminals in the second conductive terminal group 14 can be distributed on the clamping portion 16.
[0068] The shape of the concave portion 17 matches that of the first positioning member 21. The first positioning member 21 can be entirely received within the concave portion 17. The depth of the clamping portion 16 in the thickness direction X can be the same as the depth of the first clamping groove 212 in the thickness direction X, and the depth of the concave portion 17 in the thickness direction X is the same as the height of the first positioning member 21 in the thickness direction X. Thus, when the clamping portion 16 is clamped into the first clamping groove 212, the side of the clamping portion 16 facing the encapsulation substrate 3 in the thickness direction X can be flush with the side of the first positioning member 21 facing the encapsulation substrate 3 in the thickness direction X, so as to ensure that the second conductive terminal on the clamping portion 16 can be exposed outside the first positioning member 21, so that after the first positioning member 21 is connected to the encapsulation substrate 3, the second conductive terminal on the clamping portion 16 can be correspondingly connected to the second solder joint 301 of the encapsulation substrate 3.
[0069] In some embodiments, the first clamping groove 212 matches at least a partial section of the chip 2 to be tested, so that the first clamping groove 212 can clamp the chip 2 to be tested.
[0070] The shapes and dimensions of the first clamping groove 212 and at least a partial section of the chip 2 to be tested are consistent. Exemplarily, partial sections of the first clamping groove 212 and the chip 2 to be tested along the second direction Z are both square, and the width dimensions of this partial section of the first clamping groove 212 and the chip 2 to be tested along the first direction Y are the same.
[0071] In some embodiments, the second clamping groove 222 matches at least a partial section of the chip 2 to be tested, so that the second clamping groove 222 can clamp the chip 2 to be tested.
[0072] The shapes and dimensions of the second clamping groove 222 and at least a partial section of the chip 2 to be tested are consistent. Exemplarily, partial sections of the second clamping groove 222 and the chip 2 to be tested along the second direction Z are both square, and the width dimensions of this partial section of the second clamping groove 222 and the chip 2 to be tested along the first direction Y are the same.
[0073] When it is necessary to test the chip 2 to be tested, in the state where the chip 2 to be tested is connected to the encapsulation substrate 3, the first positioning member 21 can be connected to the encapsulation substrate 3, and the chip 2 to be tested is clamped into the first clamping groove 212. The position of the first positioning member 21 on the encapsulation substrate 3 is determined by the clamping between the first clamping groove 212 and the chip 2 to be tested, realizing the positioning between the first positioning member 21 and the encapsulation substrate 3.
[0074] Then, the chip to be tested 2 is removed from the package substrate 3, and the adapter 10 is assembled to the first positioning member 21. During assembly, the clamping portion 16 of the adapter 10 is first clamped in the first clamping groove 212 of the first positioning member 21, and then the third connection portion 15 on the adapter 10 and the first connection portion 211 on the first positioning member 21 are aligned along the thickness direction X, so that the adapter 10 and the first positioning member 21 are positioned.
[0075] Finally, the second positioning member 22 is matched with the first positioning member 21. During the matching, the second connection portion 221 on the second positioning member 22 is aligned with the first connection portion 211 on the first positioning member 21, or the second connection portion 221 is aligned with the third connection portion 15 on the adapter 10.
[0076] Optionally, the chip to be tested 2 removed from the package substrate 3 can be directly clamped in the second clamping groove 222 of the second positioning member 22, and the second positioning member 22 clamped with the chip to be tested 2 is matched with the first positioning member 21. Optionally, the chip to be tested 2 removed from the package substrate 3 can also be clamped in the second clamping groove 222 of the second positioning member 22 after the first positioning member 21 and the second positioning member 22 are matched.
[0077] The connection method between the first positioning member 21 and the packaging substrate 3 includes, but is not limited to, bonding, screw connection, clamping, etc.
[0078] In some embodiments, the second positioning member 22 also includes a limiting portion 223, which is arranged on the side of the second clamping slot 222 away from the adapter 10 along the thickness direction X, and is used to limit the chip to be tested 2 clamped in the second clamping slot 222 along the thickness direction X, thereby limiting the chip to be tested 2 from escaping from the second clamping slot 222 along the thickness direction X, thereby improving the installation stability of the chip to be tested 2 and improving the test efficiency.
[0079] The second positioning member 22 may include a fourth beam 224, a fifth beam 225 and a sixth beam 226, wherein the fourth beam 224 and the fifth beam 225 are arranged opposite to each other along the first direction Y, and the fourth beam 224 and the fifth beam 225 are both extended along the second direction Z, and the first direction Y, the second direction Z and the thickness direction X are perpendicular to each other. The sixth beam 226 is connected between the ends of the fourth beam 224 and the fifth beam 225 along the second direction Z. That is, the second positioning member 22 is generally in a U-shaped structure, and the second positioning groove 222 defined therein is generally a square groove. The second connecting portion 221 may be arranged on the sixth beam 226.
[0080] The limiting portion 223 may extend from at least one of the fourth beam 224, the fifth beam 225, and the sixth beam 226 toward the second locking groove 222. The number of the limiting portion 223 may be one or more.
[0081] Exemplarily, the limiting portion 223 can be disposed at the connection corners between the fourth beam 224 and the sixth beam 226, and at the connection corners between the fifth beam 225 and the sixth beam 226. The limiting portion 223 has higher structural strength and is not easily damaged.
[0082] Figure 6 Yes Figure 1 FIG. is a schematic cross-sectional structure diagram of the chip test fixture after being assembled with the chip to be tested and the packaging substrate. In some embodiments, the first conductive terminal group 13 includes a first signal terminal 131, the second conductive terminal group 14 includes a second signal terminal 141, and the first signal terminal 131 and the second signal terminal 141 are connected by a signal line 40. The adapter 10 further includes a test terminal 18, and the test terminal 18 is disposed on one of the first surface layer 11 and the second surface layer 12 and is connected to the signal line 40.
[0083] The first signal terminal 131 and the second signal terminal 141 can be distributed adjacent to the edge of the adapter 10 to shorten the length of the signal line 40 connected between the first signal terminal 131 and the second signal terminal 141, making the structure more concise.
[0084] The signal line 40 can be disposed inside the adapter 10 or on the first surface layer 11 and the second surface layer 12 of the adapter 10. Optionally, the adapter 10 further includes a routing hole 19, the hole wall of the routing hole 19 is made of a conductive material, and the signal line 40 is connected to the hole wall of the routing hole 19.
[0085] It can be understood that the signal line 40 can be encapsulated inside the adapter 10 or exposed on the first surface layer 11 and the second surface layer 12 of the adapter 10.
[0086] The test terminal 18 on the adapter 10 can cover the routing hole 19 along the thickness direction X. When the signal line is connected to the routing hole 19, it is electrically connected to the test terminal 18. Exemplarily, the test signal can go from the first solder joint 201 of the chip to be tested 2 to the first conductive terminal group 13 on the first surface layer 11 of the adapter, pass through a section of the signal line and then reach the test terminal 18, then the signal flows through the routing hole 19 to the second conductive terminal group 14 on the second surface layer 12 of the adapter, and finally reaches the second solder joint 301 of the packaging substrate 3, forming a complete path, without generating stubs, reducing the signal distortion caused by reflection, and improving the integrity of the test signal.
[0087] It should be noted that the drawings in the embodiments of the present application are only schematic diagrams for easy understanding, and the shapes or sizes of the components in the drawings may be the effects after adjustment or magnification. For example, Figure 6 the first solder joint 201 in is not protruding from the surface of the chip to be tested 2, but is flush with the surface of the chip to be tested 2. Another example is that the second solder joint 301 is not protruding from the surface of the packaging substrate 3, but is flush with the surface of the packaging substrate 3, etc.
[0088] In the embodiments of the present application, taking the tested chip 2 as a memory chip as an example, simulations are carried out on the signal line 40 with stubs (prior art) and the signal transmission route without stubs (the chip test fixture provided by the embodiments of the present application), and the insertion loss between the signal port of the memory chip and the signal port of the package substrate is obtained in both cases. Figure 7 It is the insertion loss simulation diagram of the signal transmission route without stubs provided by the embodiments of the present application and the existing signal transmission route with stubs. Figure 8 It is the time-domain reflection simulation diagram of the signal transmission route without stubs provided by the embodiments of the present application and the existing signal transmission route with stubs. Figure 7 In [the figure], the abscissa is the frequency band, the ordinate is the insertion loss, the solid curve is the test curve of the chip test fixture provided by the embodiments of the present application, and the dashed curve is the test curve of the existing chip test fixture with stubs. Figure 8 In [the figure], the abscissa is the time, the ordinate is the time-domain reflection (also called TDR), the solid curve is the test curve of the chip test fixture provided by the embodiments of the present application, and the dashed curve is the test curve of the existing chip test fixture with stubs.
[0089] Referring to Figure 7 and Figure 8 , in the frequency band from 0 GHz to 10 GHz, the insertion loss of the signal transmission route without stubs is better than that with stubs. By simulating the TDR of the signal transmission routes with and without stubs, the TDR of the signal transmission route without stubs is better than that with stubs; the TDR of both the signal transmission route without stubs and the case with stubs stabilizes at 50 Ω after 0.4 ns; but before 0.4 ns, the TDR of both changes near 50 Ω; compared with the case with stubs, the change range of the TDR in the case without stubs near 50 Ω is smaller before 0.4 ns, and the maximum impedance difference from 50 Ω is 4.1 Ω; while in the case with stubs, its TDR reaches up to 37.8 Ω at worst, and the impedance difference from 50 Ω is 12.2 Ω.
[0090] According to the above simulation results, it shows that the signal transmission route without stubs can effectively improve the insertion loss, optimize the TDR, reduce reflections and improve the signal integrity.
[0091] In some embodiments, both the first positioning member 21 and the second positioning member 22 can be insulating members. The first positioning member 21 and the second positioning member 22 only play a role of fixing and positioning and will not have any adverse effects on the test signals.
[0092] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims
1. A chip testing fixture, characterized in that: include: A transfer piece, the transfer piece comprising a first surface layer and a second surface layer which are arranged opposite to each other along the thickness direction thereof and exposed to the outside, the first surface layer being provided with a first conductive terminal group, the second surface layer being provided with a second conductive terminal group, one of the first conductive terminal group and the second conductive terminal group being arranged corresponding to a first solder joint of a chip to be tested, and the other being arranged corresponding to a second solder joint of a package substrate; as well as The positioning component includes a first positioning member and a second positioning member, wherein the first positioning member can be connected to the packaging substrate, the first positioning member includes a first connecting portion and a first clamping groove, and the first clamping groove is used to clamp the adapter; the second positioning member includes a second connecting portion and a second clamping groove, and the second clamping groove can clamp the chip to be tested; Among them, in the test state, the first positioning member and the second positioning member are paired through the first connecting portion and the second connecting portion so that the adapter is positioned between the chip to be tested and the packaging substrate, and one of the first conductive terminal group and the second conductive terminal group is connected to the first solder point accordingly, and the other is connected to the second solder point accordingly.
2. The chip testing fixture according to claim 1, characterized in that: The first connection portion and the second connection portion are both connection holes; In the test state, the first connection portion and the second connection portion are arranged opposite to each other along the thickness direction, so that the first positioning member and the second positioning member are matched.
3. The chip testing fixture according to claim 2, characterized in that: The adapter comprises a third connection portion, and the third connection portion penetrates the adapter along the thickness direction. In the test state, the first connection portion, the third connection portion and the second connection portion are arranged opposite to each other in sequence along the thickness direction.
4. The chip testing fixture according to claim 3, characterized in that: The first positioning member and the adapter are connected via a first fixing member penetrating the first connecting portion and the third connecting portion, and the adapter and the second positioning member are connected via a second fixing member penetrating the second connecting portion and the third connecting portion; or The first positioning member, the adapter member and the second positioning member are connected by a third fixing member which is simultaneously provided in the first connecting portion, the second connecting portion and the third connecting portion.
5. The chip testing fixture according to claim 1, characterized in that: The adapter is provided with a clamping portion and a recessed portion on one side away from the second positioning member along the thickness direction. The recessed portion surrounds at least part of the circumference of the clamping portion. The clamping portion is clamped in the first clamping groove. The first positioning member is at least partially accommodated in the recessed portion.
6. The chip testing fixture according to claim 5, characterized in that: The first clamping slot matches at least a portion of the chip to be tested, so that the first clamping slot can clamp the chip to be tested; and / or The second clamping slot matches with at least a partial section of the chip to be tested, so that the second clamping slot can clamp the chip to be tested.
7. The chip testing fixture according to claim 5, characterized in that: The first positioning member includes a first beam, a second beam and a third beam. The first beam and the second beam are respectively connected to two ends of the third beam and are arranged parallel to the third beam. The first beam, the second beam and the third beam enclose the first positioning groove.
8. The chip testing fixture according to claim 1, characterized in that: The second positioning member further includes a limiting portion, which is disposed on a side of the second clamping slot away from the adapter along the thickness direction and is used to limit the chip to be tested clamped in the second clamping slot along the thickness direction.
9. The chip testing fixture according to claim 1, characterized in that: The first conductive terminal group includes a first signal terminal, the second conductive terminal group includes a second signal terminal, and the first signal terminal and the second signal terminal are connected via a signal line; The adapter also includes a test terminal, which is disposed on one of the first surface layer and the second surface layer and is connected to the signal line.
10. The chip testing fixture according to claim 1, characterized in that: The first positioning member and the second positioning member are both insulating members.