SMU testing device

Abstract

The utility model discloses an SMU testing device which comprises a main control module, an SMU function module, a TTL communication module, a mode selection module and a USB transmission module, a user transmits signals to the main control module through the USB transmission module, the main control module controls the SMU function module to detect a chip to be tested, and a digital-to-analog conversion circuit and an analog-to-digital conversion circuit are arranged in the SMU function module; the main control module is provided with a main control chip U3, and the main control chip U3 is an FPGA (Field Programmable Gate Array) chip with the model of XC6SLX9-T144; an XC6SLX9-T144 type FPGA (field programmable gate array) main control chip is adopted by the main control module, eight SMU sources can be provided at most, and compared with an existing testing device, more SMU channel resources are provided, so that the testing efficiency of the chip is improved; and the TTL communication module is arranged and can be connected with other equipment such as a manipulator or a sorting machine for communication, so that automatic production of the test chip is realized.

Description

Technical Field

[0001] The utility model relates to a testing device, in particular to a chip testing device. Background Art

[0002] An SMU (i.e., a source measure unit) is an instrument that combines the functions of a signal source and a measurement function on the same pin or connector. It can provide voltage or current and measure voltage or current simultaneously. During the test production process of chips, the SMU function is required for testing. The traditional testing method is to use the SMU integrated in the tester for testing. However, there are some deficiencies in the traditional tester. For example, the traditional tester is large in volume, expensive in price, high in cost, and complex to use with a long production cycle. The SMU channel resources of the traditional tester are too few to meet the simultaneous testing of multiple pins. Summary of the Invention

[0003] In order to overcome the deficiencies of the prior art, the utility model provides an SMU testing device.

[0004] The technical solution adopted by the utility model to solve its technical problems is as follows:

[0005] An SMU testing device includes a main control module, an SMU function module, a TTL communication module, a mode selection module, and a USB transmission module. A user transmits signals to the main control module through the USB transmission module. The main control module controls the SMU function module to detect the chip to be tested. A digital-to-analog conversion circuit and an analog-to-digital conversion circuit are arranged in the SMU function module. The main control module is provided with a main control chip U3, and the main control chip U3 is an FPGA chip of the XC6SLX9-T144 model.

[0006] As a further improvement of the present utility model, the main control module includes a main control chip U3, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R17, R18, R19, R20, capacitors C3, C9, C10, C11, C12, C13, C14, C15, C16, C18, a flash memory U1, an interface terminal JP3, diodes DS1, DS3, a crystal oscillator X1, and a buzzer J1; pins 3, 13, 25, 49, 54, 68, 77, 91, 96, 108, 113, 130, and 136 of the main control chip U3 are grounded; pins 4, 18, 31, 42, 63, 76, 86, 103, 122, 125, and 135 of the main control chip U3 are connected to a 3.3V supply voltage, pins 19, 28, 52, 89, and 128 of the main control chip U3 are connected to a 1.2V supply voltage, pins 20, 36, 53, 90, and 129 of the main control chip U3 are connected to an auxiliary voltage VCCAUX, and pin 72 of the main control chip U3 is connected to the 3.3V supply voltage after connecting the resistor R20; pin 144 of the main control chip U3 is grounded after being connected in series with the resistor R9; the capacitors C9, C12, C15, and C18 are connected in parallel, with one end connected to the 3.3V supply voltage and the other end grounded; the capacitors C10 and C13 are connected in parallel, with one end connected to the 1.2V supply voltage and the other end grounded; the capacitors C11 and C14 are connected in parallel, with one end connected to the auxiliary voltage VCCAUX and the other end grounded; the resistors R1 and R7 are connected in series, with one end connected to the 3.3V supply voltage and the other end grounded, and the connection point of the resistors R1 and R7 is connected to pin 69 of the main control chip U3, the resistors R2 and R8 are connected in series, with one end connected to the 3.3V supply voltage and the other end grounded, and the connection point of the resistors R2 and R8 is connected to pin 60 of the main control chip U3; one end of the capacitor C16 is connected to the 3.3V supply voltage and the other end is grounded; pin 1 of the flash memory U1 is connected to pin 38 of the main control chip U3, pin 2 of the flash memory U1 is connected to the resistor R3 and then connected to pin 65 of the main control chip U3, pin 3 of the flash memory U1 is connected to the 3.3V supply voltage, pin 4 of the flash memory U1 is grounded, pin 5 of the flash memory U1 is connected to pin 64 of the main control chip U3, pin 6 of the flash memory U1 is connected to the resistor R10 and then connected to pin 70 of the main control chip U3, and pins 7 and 8 of the flash memory U1 are connected to the 3.3V supply voltage; pin 1 of the interface terminal JP3 is connected to pin 109 of the main control chip U3, one end of the resistor R11 is connected to the connection point of pin 1 of the interface terminal JP3 and pin 109 of the main control chip U3, and the other end is grounded; pin 2 and pin 10 of the interface terminal JP3 are grounded; pin 3 of the interface terminal JP3 is connected to pin 106 of the main control chip U3, pin 5 of the interface terminal JP3 is connected to pin 107 of the main control chip U3, pin 9 of the interface terminal JP3 is connected to pin 110 of the main control chip U3, and pins 6, 7, and 8 of the interface terminal JP3 are left unconnected; one ends of the resistors R12 and R13 are connected together and then connected to the 3.3V supply voltage, the other end of the resistor R12 is connected to the connection point of pin 5 of the interface terminal JP3 and pin 107 of the main control chip U3, the other end of the resistor R13 is connected to the connection point of pin 9 of the interface terminal JP3 and pin 110 of the main control chip U3, and pin 4 of the interface terminal JP3 is connected to the 3.3V supply voltage; one ends of the resistors R4, R5, and R6 are connected together and then connected to the 3.3V supply voltage, the other end of the resistor R4 is connected to pin 37 of the main control chip U3, the other end of the resistor R5 is connected to pin 39 of the main control chip U3, the other end of the resistor R6 is connected to pin 71 of the main control chip U3, the positive electrode of the diode DS1 is connected to the connection point of the resistor R6 and pin 71 of the main control chip U3, and the negative electrode is grounded; the positive electrode of the diode DS3 is connected to the resistor R17 and then connected to pin 75 of the main control chip U3, and the negative electrode of the diode DS3 is grounded; the resistors R18 and R19 are connected in series, one end is connected to the 3.3V supply voltage and the other end is grounded, and the connection point of the resistors R18 and R19 is connected to pin 73 of the main control chip U3; one end of the buzzer J1 is connected to the resistor R14 and then connected to pin 124 of the main control chip U3, and the other end is grounded; one end of the capacitor C3 is connected to pin 2 of the crystal oscillator X1, the other end is connected to pin 4 of the crystal oscillator X1, the connection point of the capacitor C3 and pin 4 of the crystal oscillator X1 is connected to the 3.3V supply voltage, the connection point of the capacitor C3 and pin 2 of the crystal oscillator X1 is grounded, and pin 3 of the crystal oscillator X1 is connected to the resistor R15 and then connected to pin 123 of the main control chip U3.

[0007] As a further improvement of the present utility model, the USB transmission module includes a USB serial port chip U6, a USB interface terminal JP5, a resistor R16, a resistor R21, a resistor R22, a resistor R23, a crystal oscillator Y1, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, and a capacitor C24. One end of the resistor R16 is connected to the 3.3V power supply voltage, and the other end is connected to pin 5 of the USB serial port chip U6; pin 4 of the USB serial port chip U6 is connected to the 3.3V power supply voltage, and pin 7 is grounded; pin 15 of the USB serial port chip U6 is connected to the resistor R23 and then to pin 3 of the USB interface terminal JP5, and pin 16 of the USB serial port chip U6 is connected to the resistor R22 and then to pin 2 of the USB interface terminal JP5; pins 1 and 4 of the USB interface terminal JP5 are left unconnected, and pin 5 of the USB interface terminal JP5 is grounded; pin 17 of the USB serial port chip U6 is connected to the resistor R21 and then to the connection point of pin 15 of the USB serial port chip U6 and the resistor R23, pins 18, 21, 22, 23, 25, and 26 of the USB serial port chip U6 are connected in parallel and then grounded, one end of the capacitor C21 is connected to the connection point of pin 17 of the USB serial port chip U6 and the resistor R21, and the other end is grounded, pin 27 of the USB serial port chip U6 is connected to the capacitor C23 and then grounded, pin 28 of the USB serial port chip U6 is connected to the capacitor C22 and then grounded, one end of the crystal oscillator Y1 is connected to the connection point of pin 27 of the USB serial port chip U6 and the capacitor C23, and the other end is connected to the connection point of pin 28 of the USB serial port chip U6 and the capacitor C22; one end of the capacitor C20 is connected to the 3.3V power supply voltage, and the other end is grounded; one end of the capacitor C24 is connected to the 5V operating voltage, and the other end is grounded.

[0008] Further, the digital-to-analog conversion circuit includes a digital-to-analog converter U1, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C8, a capacitor C17, and a capacitor C19. One end of the parallel connection of the capacitor C26 and the capacitor C27 is connected to the pin 4 of the digital-to-analog converter U1, and the other end is connected to the pin 5 of the digital-to-analog converter U1. The connection point of the capacitor C26, the capacitor C27, and the pin 4 of the digital-to-analog converter U1 is connected to the -15V voltage. One end of the parallel connection of the capacitor C8 and the capacitor C17 is connected to the pin 24 of the digital-to-analog converter U1, and the other end is grounded. The connection point of the capacitor C8, the capacitor C17, and the pin 24 of the digital-to-analog converter U1 is connected to the 5V operating voltage. One end of the parallel connection of the capacitor C19 and the capacitor C25 is connected to the pin 25 of the digital-to-analog converter U1, and the other end is grounded. The connection point of the capacitor C19, the capacitor C25, and the pin 25 of the digital-to-analog converter U1 is connected to the +15V voltage. The pins 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 of the digital-to-analog converter U1 are connected together.

[0009] Further, the analog-to-digital conversion circuit includes an analog-to-digital converter U2, a resistor R28, a resistor R29, a capacitor C32, a capacitor C33, a capacitor C34, and a capacitor C35. The pin 1 of the analog-to-digital converter U2 is connected to the resistor R28 and then connected to an external circuit. The pin 2 of the analog-to-digital converter U2 is connected to the capacitor C33 and then connected to the pin 3 of the analog-to-digital converter U2. The pin 4 of the analog-to-digital converter U2 is connected to the resistor R29 and then connected to the connection point of the pin 1 of the analog-to-digital converter U2 and the resistor R28. The pin 5 of the analog-to-digital converter U2 is connected to the capacitor C32 and then connected to the connection point of the pin 1 of the analog-to-digital converter U2 and the resistor R28. The connection point of the pin 5 of the analog-to-digital converter U2 and the capacitor C32 is grounded. The pins 27 and 28 of the analog-to-digital converter U2 are connected and then divided into two paths. One path is connected to the capacitor C34 and then grounded, and the other path is connected to the capacitor C35 and then grounded. The pins 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, and 22 of the analog-to-digital converter U2 are connected together, and the pin 14 of the analog-to-digital converter U2 is grounded.

[0010] Further, the mode selection module includes a resistor 24, a resistor 25, a resistor 26, and a resistor 27. One end of the series connection of the resistor 24 and the resistor 26 is connected to the 3.3V power supply voltage, and the other end is grounded. One end of the series connection of the resistor 25 and the resistor 27 is connected to the 3.3V power supply voltage, and the other end is grounded. The connection point of the resistor 24 and the resistor 26 is connected to the external circuit, and the connection point of the resistor 25 and the resistor 27 is connected to the external circuit.

[0011] Further, the TTL communication module includes resistor 30, resistor 31, resistor 32, resistor 33, resistor 34, resistor 35, resistor 36, resistor 37, optocoupler U19, and interface terminal J2. Pin 2 of the optocoupler U19 is connected to resistor 30 and then grounded. Pin 4 of the optocoupler U19 is connected to resistor 31 and then grounded. Pin 6 of the optocoupler U19 is connected to resistor 32 and then grounded. Pin 7 of the optocoupler U19 is connected to resistor 33 and then connected to the 5V operating voltage. Pin 8 of the optocoupler U19 is connected to pin 4 of the interface terminal J2. Pins 9, 11, 13, and 15 of the optocoupler U19 are grounded. Pins 10, 12, 14, and 16 of the optocoupler U19 are respectively connected to resistor 37, resistor 36, resistor 35, and resistor 34 and then connected to the 5V operating voltage.

[0012] The beneficial effects of the present utility model are as follows: The main control module of the present utility model uses an FPGA main control chip of the XC6SLX9-T144 model, which can provide up to 8 SMU sources. Compared with the existing test devices, there are more SMU channel resources, improving the test efficiency of the chip. And a TTL communication module is provided, which can be connected to other devices such as a manipulator or a sorter for communication to realize the automated production of test chips. Description of the Drawings

[0013] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0014] Figure 1 is the circuit schematic diagram of the present utility model.

[0015] Figure 2 is one of the circuit structure diagrams of the main control module.

[0016] Figure 3 is the second circuit structure diagram of the main control module.

[0017] Figure 4 is the third circuit structure diagram of the main control module.

[0018] Figure 5 is the fourth circuit structure diagram of the main control module.

[0019] Figure 6 is the fifth circuit structure diagram of the main control module.

[0020] Figure 7 is the sixth circuit structure diagram of the main control module.

[0021] Figure 8 is the seventh circuit structure diagram of the main control module.

[0022] Figure 9It is the eighth circuit structure diagram of the main control module.

[0023] Figure 10 It is the ninth circuit structure diagram of the main control module.

[0024] Figure 11 It is the tenth circuit structure diagram of the main control module.

[0025] Figure 12 It is the eleventh circuit structure diagram of the main control module.

[0026] Figure 13 It is the twelfth circuit structure diagram of the main control module.

[0027] Figure 14 It is the thirteenth circuit structure diagram of the main control module.

[0028] Figure 15 It is the fourteenth circuit structure diagram of the main control module.

[0029] Figure 16 It is the fifteenth circuit structure diagram of the main control module.

[0030] Figure 17 It is the sixteenth circuit structure diagram of the main control module.

[0031] Figure 18 It is the seventeenth circuit structure diagram of the main control module.

[0032] Figure 19 It is the eighteenth circuit structure diagram of the main control module.

[0033] Figure 20 It is the nineteenth circuit structure diagram of the main control module.

[0034] Figure 21 It is the twentieth circuit structure diagram of the main control module.

[0035] Figure 22 It is the circuit structure diagram of the USB transmission module.

[0036] Figure 23 It is the circuit structure diagram of the digital-to-analog conversion circuit.

[0037] Figure 24 It is the circuit structure diagram of the analog-to-digital conversion circuit.

[0038] Figure 25 It is the circuit structure diagram of the mode selection module.

[0039] Figure 26 It is the circuit structure diagram of the TTL communication module. Specific implementation mode

[0040] To make the objectives, technical solutions and advantages of the present utility model more clear and understandable, the present utility model will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present utility model and the features in the embodiments may be combined with each other.

[0041] It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present utility model.

[0042] Referring to Figures 1 to 26 , an SMU test device includes a main control module, an SMU function module, a TTL communication module, a mode selection module, and a USB transmission module. A user transmits a signal to the main control module through the USB transmission module. The main control module controls the SMU function module to detect a chip to be tested. A digital-to-analog conversion circuit and an analog-to-digital conversion circuit are arranged in the SMU function module; a main control chip U3 is arranged in the main control module. The main control chip U3 is an FPGA chip of the XC6SLX9-T144 model. The FPGA chip has the characteristics of fast speed, rich IO resources, flexible programming, and low power consumption. The main control module of this embodiment adopts an FPGA main control chip of the XC6SLX9-T144 model, which can provide up to 8 SMU sources. Compared with the existing test devices, there are more SMU channel resources, improving the test efficiency of the chip; and a TTL communication module is provided, which can be connected to other devices such as a manipulator or a sorter for communication to realize the automated production of test chips.

[0043] The main control module includes a main control chip U3, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R17, R18, R19, R20, capacitors C3, C9, C10, C11, C12, C13, C14, C15, C16, C18, a flash memory U1, an interface terminal JP3, diodes DS1, DS3, a crystal oscillator X1, and a buzzer J1; Pins 3, 13, 25, 49, 54, 68, 77, 91, 96, 108, 113, 130, and 136 of the main control chip U3 are grounded; Pins 4, 18, 31, 42, 63, 76, 86, 103, 122, 125, and 135 of the main control chip U3 are connected to a 3.3V supply voltage, pins 19, 28, 52, 89, and 128 of the main control chip U3 are connected to a 1.2V supply voltage, pins 20, 36, 53, 90, and 129 of the main control chip U3 are connected to an auxiliary voltage VCCAUX, and pin 72 of the main control chip U3 is connected to the 3.3V supply voltage after connecting to the resistor R20; Pin 144 of the main control chip U3 is grounded after being connected in series with the resistor R9; The capacitors C9, C12, C15, and C18 are connected in parallel, with one end connected to the 3.3V supply voltage and the other end grounded; The capacitors C10 and C13 are connected in parallel, with one end connected to the 1.2V supply voltage and the other end grounded; The capacitors C11 and C14 are connected in parallel, with one end connected to the auxiliary voltage VCCAUX and the other end grounded; The resistors R1 and R7 are connected in series, with one end connected to the 3.3V supply voltage and the other end grounded, and the connection point of the resistors R1 and R7 is connected to pin 69 of the main control chip U3. The resistors R2 and R8 are connected in series, with one end connected to the 3.3V supply voltage and the other end grounded, and the connection point of the resistors R2 and R8 is connected to pin 60 of the main control chip U3; One end of the capacitor C16 is connected to the 3.3V supply voltage and the other end is grounded; Pin 1 of the flash memory U1 is connected to pin 38 of the main control chip U3, pin 2 of the flash memory U1 is connected to the resistor R3 and then connected to pin 65 of the main control chip U3, pin 3 of the flash memory U1 is connected to the 3.3V supply voltage, pin 4 of the flash memory U1 is grounded, pin 5 of the flash memory U1 is connected to pin 64 of the main control chip U3, pin 6 of the flash memory U1 is connected to the resistor R10 and then connected to pin 70 of the main control chip U3, and pins 7 and 8 of the flash memory U1 are connected to the 3.3V supply voltage; Pin 1 of the interface terminal JP3 is connected to Pin 109 of the main control chip U3. One end of the resistor R11 is connected to the connection point of Pin 1 of the interface terminal JP3 and Pin 109 of the main control chip U3, and the other end is grounded; Pins 2 and 10 of the interface terminal JP3 are grounded; Pin 3 of the interface terminal JP3 is connected to Pin 106 of the main control chip U3, Pin 5 of the interface terminal JP3 is connected to Pin 107 of the main control chip U3, Pin 9 of the interface terminal JP3 is connected to Pin 110 of the main control chip U3, and Pins 6, 7, and 8 of the interface terminal JP3 are left unconnected; One ends of the resistors R12 and R13 are connected together and then connected to the 3.3V supply voltage. The other end of the resistor R12 is connected to the connection point of Pin 5 of the interface terminal JP3 and Pin 107 of the main control chip U3, and the other end of the resistor R13 is connected to the connection point of Pin 9 of the interface terminal JP3 and Pin 110 of the main control chip U3. Pin 4 of the interface terminal JP3 is connected to the 3.3V supply voltage; One ends of the resistors R4, R5, and R6 are connected together and then connected to the 3.3V supply voltage. The other end of the resistor R4 is connected to Pin 37 of the main control chip U3, the other end of the resistor R5 is connected to Pin 39 of the main control chip U3, and the other end of the resistor R6 is connected to Pin 71 of the main control chip U3. The positive pole of the diode DS1 is connected to the connection point of the resistor R6 and Pin 71 of the main control chip U3, and the negative pole is grounded; The positive pole of the diode DS3 is connected to the resistor R17 and then connected to Pin 75 of the main control chip U3, and the negative pole of the diode DS3 is grounded; The resistors R18 and R19 are connected in series, with one end connected to the 3.3V supply voltage and the other end grounded. The connection point of the resistors R18 and R19 is connected to Pin 73 of the main control chip U3; One end of the buzzer J1 is connected to the resistor R14 and then connected to Pin 124 of the main control chip U3, and the other end is grounded; One end of the capacitor C3 is connected to Pin 2 of the crystal oscillator X1, and the other end is connected to Pin 4 of the crystal oscillator X1. The connection point of the capacitor C3 and Pin 4 of the crystal oscillator X1 is connected to the 3.3V supply voltage, the connection point of the capacitor C3 and Pin 2 of the crystal oscillator X1 is grounded, and Pin 3 of the crystal oscillator X1 is connected to the resistor R15 and then connected to Pin 123 of the main control chip U3.

[0044] The USB transmission module includes a USB serial port chip U6, a USB interface terminal JP5, resistors R16, R21, R22, R23, a crystal oscillator Y1, capacitors C20, C21, C22, C23, C24. One end of the resistor R16 is connected to the 3.3V power supply voltage, and the other end is connected to pin 5 of the USB serial port chip U6; pin 4 of the USB serial port chip U6 is connected to the 3.3V power supply voltage, and pin 7 is grounded; pin 15 of the USB serial port chip U6 is connected to the resistor R23 and then to pin 3 of the USB interface terminal JP5, and pin 16 of the USB serial port chip U6 is connected to the resistor R22 and then to pin 2 of the USB interface terminal JP5; pin 1 and pin 4 of the USB interface terminal JP5 are left unconnected, and pin 5 of the USB interface terminal JP5 is grounded; pin 17 of the USB serial port chip U6 is connected to the resistor R21 and then to the connection point of pin 15 of the USB serial port chip U6 and the resistor R23, pins 18, 21, 22, 23, 25, 26 of the USB serial port chip U6 are connected in parallel and then grounded, one end of the capacitor C21 is connected to the connection point of pin 17 of the USB serial port chip U6 and the resistor R21, and the other end is grounded, pin 27 of the USB serial port chip U6 is connected to the capacitor C23 and then grounded, pin 28 of the USB serial port chip U6 is connected to the capacitor C22 and then grounded, one end of the crystal oscillator Y1 is connected to the connection point of pin 27 of the USB serial port chip U6 and the capacitor C23, and the other end is connected to the connection point of pin 28 of the USB serial port chip U6 and the capacitor C22; one end of the capacitor C20 is connected to the 3.3V power supply voltage, and the other end is grounded; one end of the capacitor C24 is connected to the 5V operating voltage, and the other end is grounded. The USB serial port chip U6 in this embodiment is specifically a USB to serial port chip of the PL2303 model. It is a highly integrated RS232-USB interface converter that can provide a solution for the convenient connection of an RS232 full-duplex asynchronous serial communication device and a USB functional interface. This device integrates a USB functional controller, a USB transceiver, an oscillator, and a UART with all modem control signals. Only a few external capacitors are required to achieve the conversion between USB signals and RS232 signals, and it can be easily embedded into various devices; as a USB / RS232 bidirectional converter, on the one hand, it receives USB data from the host and converts it into an RS232 information flow format and sends it to the peripheral device; on the other hand, it receives data from the RS232 peripheral device and converts it into a USB data format and transmits it back to the host.

[0045] The digital-to-analog conversion circuit includes a digital-to-analog converter U1, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C8, a capacitor C17, and a capacitor C19. The digital-to-analog converter U1 is specifically a digital-to-analog conversion chip of model DAC7724. One end of the capacitor C26 and the capacitor C27 in parallel is connected to the pin 4 of the digital-to-analog converter U1, and the other end is connected to the pin 5 of the digital-to-analog converter U1. The connection point of the capacitor C26, the capacitor C27 and the pin 4 of the digital-to-analog converter U1 is connected to -15V voltage. One end of the capacitor C8 and the capacitor C17 in parallel is connected to the pin 24 of the digital-to-analog converter U1, and the other end is grounded. The connection point of the capacitor C8, the capacitor C17 and the pin 24 of the digital-to-analog converter U1 is connected to the 5V working voltage. One end of the capacitor C19 and the capacitor C25 in parallel is connected to the pin 25 of the digital-to-analog converter U1, and the other end is grounded. The connection point of the capacitor C19, the capacitor C25 and the pin 25 of the digital-to-analog converter U1 is connected to +15V voltage. The pins 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 of the digital-to-analog converter U1 are connected.

[0046] The analog-to-digital conversion circuit includes an analog-to-digital converter U2, a resistor R28, a resistor R29, a capacitor C32, a capacitor C33, a capacitor C34, and a capacitor C35. The analog-to-digital converter U2 is specifically an analog-to-digital conversion chip of model AD976. The pin 1 of the analog-to-digital converter U2 is connected to the resistor R28 and then connected to an external circuit. The pin 2 of the analog-to-digital converter U2 is connected to the capacitor C33 and then connected to the pin 3 of the analog-to-digital converter U2. The pin 4 of the analog-to-digital converter U2 is connected to the resistor R29 and then connected to the connection point of the pin 1 of the analog-to-digital converter U2 and the resistor R28. The pin 5 of the analog-to-digital converter U2 is connected to the capacitor C32 and then connected to the connection point of the pin 1 of the analog-to-digital converter U2 and the resistor R28. The connection point of the pin 5 of the analog-to-digital converter U2 and the capacitor C32 is grounded. The pins 27 and 28 of the analog-to-digital converter U2 are connected and then divided into two paths. One path is connected to the capacitor C34 and then grounded, and the other path is connected to the capacitor C35 and then grounded. The pins 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 22 of the analog-to-digital converter U2 are connected, and the pin 14 of the analog-to-digital converter U2 is grounded.

[0047] The mode selection module includes resistors R24, R25, R26, and R27. One end of the series connection of R24 and R26 is connected to the 3.3V supply voltage, and the other end is grounded; one end of the series connection of R25 and R27 is connected to the 3.3V supply voltage, and the other end is grounded; the connection point of R24 and R26 is connected to the external circuit, and the connection point of R25 and R27 is connected to the external circuit; the mode selection module adopts a resistor network solution, which facilitates the software design. When changing the mode, only the resistor needs to be replaced accordingly.

[0048] The TTL communication module includes resistors R30, R31, R32, R33, R34, R35, R36, R37, optocoupler U19, and interface terminal J2. Pin 2 of the optocoupler U19 is connected to R30 and then grounded, pin 4 of the optocoupler U19 is connected to R31 and then grounded, and pin 6 of the optocoupler U19 is connected to R32 and then grounded; pin 7 of the optocoupler U19 is connected to R33 and then connected to the 5V operating voltage, pin 8 of the optocoupler U19 is connected to pin 4 of the interface terminal J2, pins 9, 11, 13, and 15 of the optocoupler U19 are grounded, and pins 10, 12, 14, and 16 of the optocoupler U19 are respectively connected to R37, R36, R35, and R34 and then connected to the 5V operating voltage; the TTL communication interface module is used to realize the communication connection between this embodiment and the manipulator or sorting machine equipment for automated batch production.

[0049] In the present utility model, the term "plurality" refers to two or more, unless otherwise clearly defined. The term "and / or" used herein includes any and all combinations of one or more of the related listed items. Terms such as "mounted", "connected", "connected to", "fixed" and the like should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0050] It should be noted that when an element is referred to as being "assembled on", "mounted on", "fixed to" or "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only implementation manner.

[0051] In the description of this specification, the descriptions of terms such as "one embodiment", "some embodiments", "specific embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or instance. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0052] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present utility model, and the scope of the present utility model is defined by the claims and their equivalents.

Claims

1. A SMU test device, characterized in that It includes a main control module, an SMU functional module, a TTL communication module, a mode selection module, and a USB transmission module. The user transmits a signal to the main control module through the USB transmission module. The main control module controls the SMU functional module to detect the chip to be tested. The SMU functional module is provided with a digital-to-analog conversion circuit and an analog-to-digital conversion circuit; the main control module is provided with a main control chip U3, and the main control chip U3 is an FPGA chip of the XC6SLX9-T144 model.

2. The SMU test device according to claim 1, characterized in that The main control module includes a main control chip U3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C3, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C18, a flash memory U1, an interface terminal JP3, a diode DS1, a diode DS3, a crystal oscillator X1, and a buzzer J1; pins 3, 13, 25, and 16 of the main control chip U3 are 49, pin 54, pin 68, pin 77, pin 91, pin 96, pin 108, pin 113, pin 130, pin 136 are grounded; pin 4, pin 18, pin 31, pin 42, pin 63, pin 76, pin 86, pin 103, pin 122, pin 125, pin 135 of the main control chip U3 are connected to a 3.3V power supply voltage, pin 19, pin 28, pin 52, pin 89, pin 128 of the main control chip U3 are connected to a 1.2V power supply voltage, pin 20, pin 36, pin 53, pin 90, pin 129 of the main control chip U3 are connected to an auxiliary voltage VCCAUX, and pin 72 of the main control chip U3 is connected to the resistor R20 The 3.3V power supply voltage is then connected; the pin 144 of the main control chip U3 is connected in series with the resistor R9 and then grounded; the capacitors C9, C12, C15 and C18 are connected in parallel and one end is connected to the 3.3V power supply voltage, and the other end is grounded; the capacitor C10 and the capacitor C13 are connected in parallel and one end is connected to the 1.2V power supply voltage, and the other end is grounded; the capacitor C11 and the capacitor C14 are connected in parallel and one end is connected to the auxiliary voltage VCCAUX, and the other end is grounded; the resistor R1 and the resistor R7 are connected in series and one end is connected to the 3.3V power supply voltage, and the other end is grounded, the junction of the resistor R1 and the resistor R7 is connected to the pin 69 of the main control chip U3, and the resistor R2 and the resistor R8 are connected in series and one end is connected to the 3.3V The connection point of the resistor R2 and the resistor R8 is connected to the pin 60 of the main control chip U3; one end of the capacitor C16 is connected to the 3.3V supply voltage, and the other end is grounded; the pin 1 of the flash memory U1 is connected to the pin 38 of the main control chip U3, the pin 2 of the flash memory U1 is connected to the resistor R3 and then connected to the pin 65 of the main control chip U3, the pin 3 of the flash memory U1 is connected to the 3.3V supply voltage, the pin 4 of the flash memory U1 is grounded, the pin 5 of the flash memory U1 is connected to the pin 64 of the main control chip U3, the pin 6 of the flash memory U1 is connected to the resistor R10 and then connected to the pin 70 of the main control chip U3, and the pins 7 and 8 of the flash memory U1 are connected to the 3.3V supply voltage.3V power supply voltage; Pin 1 of the interface terminal JP3 is connected to Pin 109 of the main control chip U3, one end of the resistor R11 is connected to the junction of Pin 1 of the interface terminal JP3 and Pin 109 of the main control chip U3, and the other end is grounded; Pin 2 and Pin 10 of the interface terminal JP3 are grounded; Pin 3 of the interface terminal JP3 is connected to Pin 106 of the main control chip U3, Pin 5 of the interface terminal JP3 is connected to Pin 107 of the main control chip U3, Pin 9 of the interface terminal JP3 is connected to Pin 110 of the main control chip U3, and the interface terminal Pin 6, Pin 7, and Pin 8 of the interface terminal JP3 are connected; one end of the resistor R12 and the resistor R13 are connected and then connected to the 3.3V power supply voltage, the other end of the resistor R12 is connected to the contact point between Pin 5 of the interface terminal JP3 and Pin 107 of the main control chip U3, the other end of the resistor R13 is connected to the contact point between Pin 9 of the interface terminal JP3 and Pin 110 of the main control chip U3, and Pin 4 of the interface terminal JP3 is connected to the 3.3V power supply voltage; one end of the resistor R4, the resistor R5, and the resistor R6 are connected and then connected to the 3.3V power supply voltage, the resistors The other end of the resistor R4 is connected to the pin 37 of the main control chip U3, the other end of the resistor R5 is connected to the pin 39 of the main control chip U3, the other end of the resistor R6 is connected to the pin 71 of the main control chip U3, the positive electrode of the diode DS1 is connected to the junction of the resistor R6 and the pin 71 of the main control chip U3, and the negative electrode is grounded; the positive electrode of the diode DS3 is connected to the resistor R17 and then to the pin 75 of the main control chip U3, and the negative electrode of the diode DS3 is grounded; the resistors R18 and R19 are connected in series, and one end is connected to the 3.3V power supply voltage and the other end is grounded. The connection point of the resistor R18 and the resistor R19 is connected to the pin 73 of the main control chip U3; one end of the buzzer J1 is connected to the resistor R14 and then connected to the pin 124 of the main control chip U3, and the other end is grounded; one end of the capacitor C3 is connected to the pin 2 of the crystal oscillator X1, and the other end is connected to the pin 4 of the crystal oscillator X1. The connection point between the capacitor C3 and the pin 4 of the crystal oscillator X1 is connected to the 3.3V power supply voltage, the connection point between the capacitor C3 and the pin 2 of the crystal oscillator X1 is grounded, and the pin 3 of the crystal oscillator X1 is connected to the resistor R15 and then connected to the pin 123 of the main control chip U3.

3. The SMU test device according to claim 2, characterized in that The USB transmission module includes a USB serial port chip U6, a USB interface terminal JP5, a resistor R16, a resistor R21, a resistor R22, a resistor R23, a crystal oscillator Y1, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, and a capacitor C24. One end of the resistor R16 is connected to the 3.3V power supply voltage, and the other end is connected to pin 5 of the USB serial port chip U6; pin 4 of the USB serial port chip U6 is connected to the 3.3V power supply voltage, and pin 7 is grounded; pin 15 of the USB serial port chip U6 is connected to the resistor R23 and then to pin 3 of the USB interface terminal JP5, and pin 16 of the USB serial port chip U6 is connected to the resistor R22 and then to pin 2 of the USB interface terminal JP5; pin 1 and pin 4 of the USB interface terminal JP5 are unconnected, and pin 5 of the USB interface terminal JP5 is grounded; pin 2 of the USB serial port chip U6 is connected to the resistor R23 and then to pin 2 of the USB interface terminal JP5; pin 1 and pin 4 of the USB interface terminal JP5 are unconnected, and pin 5 of the USB interface terminal JP5 is grounded; Pin 17 is connected to the resistor R21 and then to the junction of pin 15 of the USB serial port chip U6 and resistor R23. Pin 18, pin 21, pin 22, pin 23, pin 25 and pin 26 of the USB serial port chip U6 are connected in parallel and then grounded. One end of the capacitor C21 is connected to the junction of pin 17 of the USB serial port chip U6 and resistor R21, and the other end is grounded. Pin 27 of the USB serial port chip U6 is connected to the capacitor C23 and then to ground. Pin 28 of the USB serial port chip U6 is connected to the capacitor C22 and then to ground. One end of the crystal oscillator Y1 is connected to the junction of pin 27 of the USB serial port chip U6 and capacitor C23, and the other end is connected to the junction of pin 28 of the USB serial port chip U6 and capacitor C22. One end of the capacitor C20 is connected to the 3.3V power supply voltage, and the other end is grounded. One end of the capacitor C24 is connected to the 5V working voltage, and the other end is grounded.

4. The SMU test device according to claim 3, characterized in that The digital-to-analog conversion circuit includes a digital-to-analog converter U1, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C8, a capacitor C17, and a capacitor C19. After the capacitor C26 and the capacitor C27 are connected in parallel, one end is connected to the pin 4 of the digital-to-analog converter U1, and the other end is connected to the pin 5 of the digital-to-analog converter U1. The connection point between the capacitor C26, the capacitor C27 and the pin 4 of the digital-to-analog converter U1 is connected to a -15V voltage. After the capacitor C8 and the capacitor C17 are connected in parallel, one end is connected to the pin 24 of the digital-to-analog converter U1, and the other end is grounded. The connection point between capacitor C8, capacitor C17 and pin 24 of the digital-to-analog converter U1 is connected to the 5V operating voltage; after the capacitor C19 and capacitor C25 are connected in parallel, one end is connected to pin 25 of the digital-to-analog converter U1, and the other end is grounded, and the connection point between capacitor C19, capacitor C25 and pin 25 of the digital-to-analog converter U1 is connected to a +15V voltage; pin 8, pin 9, pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, pin 16, pin 17, pin 18 and pin 19 of the digital-to-analog converter U1 are connected.

5. The SMU test device according to claim 4, characterized in that The analog-to-digital conversion circuit includes an analog-to-digital converter U2, a resistor R28, a resistor R29, a capacitor C32, a capacitor C33, a capacitor C34, and a capacitor C35; the pin 1 of the analog-to-digital converter U2 is connected to the resistor R28 and then to an external circuit, the pin 2 of the analog-to-digital converter U2 is connected to the capacitor C33 and then to the pin 3 of the analog-to-digital converter U2; the pin 4 of the analog-to-digital converter U2 is connected to the resistor R29 and then to the connection point between the pin 1 of the analog-to-digital converter U2 and the resistor R28; the pin 5 of the analog-to-digital converter U2 is connected to the capacitor C32 and then to the analog-to-digital converter U 2 and the connection point of resistor R28; the connection point of pin 5 of the analog-to-digital converter U2 and capacitor C32 is grounded; pin 27 and pin 28 of the analog-to-digital converter U2 are divided into two paths after being connected, one path is connected to the capacitor C34 and then to ground, and the other path is connected to the capacitor C35 and then to ground; pin 6, pin 7, pin 8, pin 9, pin 10, pin 11, pin 12, pin 13, pin 15, pin 16, pin 17, pin 18, pin 19, pin 20, pin 21, and pin 22 of the analog-to-digital converter U2 are connected, and pin 14 of the analog-to-digital converter U2 is grounded.

6. The SMU test device according to claim 5, characterized in that The mode selection module includes resistor 24, resistor 25, resistor 26, and resistor 27. After the resistor 24 and resistor 26 are connected in series, one end is connected to the 3.3V power supply voltage, and the other end is grounded; after the resistor 25 and resistor 27 are connected in series, one end is connected to the 3.3V power supply voltage, and the other end is grounded; the connection point of the resistor 24 and resistor 26 is connected to the external circuit, and the connection point of the resistor 25 and resistor 27 is connected to the external circuit.

7. The SMU test device according to claim 6, characterized in that The TTL communication module includes resistor 30, resistor 31, resistor 32, resistor 33, resistor 34, resistor 35, resistor 36, resistor 37, photoelectric coupler U19, and interface terminal J2. Pin 2 of the photoelectric coupler U19 is connected to the resistor 30 and then to ground, pin 4 of the photoelectric coupler U19 is connected to the resistor 31 and then to ground, and pin 6 of the photoelectric coupler U19 is connected to the resistor 32 and then to ground; pin 7 of the photoelectric coupler U19 is connected to the resistor 33 and then to the 5V working voltage, pin 8 of the photoelectric coupler U19 is connected to pin 4 of the interface terminal J2, pin 9, pin 11, pin 13, and pin 15 of the photoelectric coupler U19 are grounded, and pin 10, pin 12, pin 14, and pin 16 of the photoelectric coupler U19 are respectively connected to the resistor 37, resistor 36, resistor 35, and resistor 34 and then to the 5V working voltage.

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