Information processing carrier plate based on 3U VPX architecture

Abstract

The utility model discloses an information processing carrier plate based on 3U VPX architecture, which relates to the technical field of signal processing equipment and comprises a back plate, a main control card, an instruction card, an input card, an output card and a front panel. The main control card, the instruction card, the input card and the output card are connected between the back plate and the front panel; a plurality of 3U VPX connectors are arranged on the back plate, and the back plate is connected with the main control card, the instruction card, the input card and the output card through the 3U VPX connectors; the instruction card is provided with an SFP + optical module, and the SFP + optical module is connected with the front panel. The beneficial effect of the utility model is that the efficiency of information processing and data transmission is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of signal processing equipment, and more specifically, to an information processing carrier board based on a 3U VPX architecture. Background Art

[0002] An information processing carrier board is usually a hardware device or module for processing and transmitting information, and is usually applied to a high-performance computing environment. Real-time data processing and computing tasks are crucial for quick response and efficient processing. Although traditional general-purpose processors (CPUs) and graphics processing units (GPUs) have certain computing capabilities, there are performance bottlenecks when dealing with complex algorithms and large-scale data.

[0003] Therefore, this solution provides an information processing carrier board based on a 3U VPX architecture to improve information processing efficiency and data transmission efficiency. Content of the Utility Model

[0004] In order to overcome the deficiencies of the prior art, the utility model provides an information processing carrier board based on a 3U VPX architecture, which solves the problem of performance bottlenecks in current information processing carrier boards when dealing with complex algorithms and large-scale data, thereby improving information processing and data transmission efficiency.

[0005] The technical solution adopted by the utility model to solve its technical problems is: an information processing carrier board based on a 3U VPX architecture, which is improved in that the information processing carrier board based on a 3U VPX architecture includes a backplane, a main control card, an instruction card, an input card, an output card, and a front panel; the main control card, the instruction card, the input card, and the output card are connected between the backplane and the front panel;

[0006] A number of 3U VPX connectors are arranged on the backplane, and the backplane is connected to the main control card, the instruction card, the input card, and the output card through the 3U VPX connectors;

[0007] An SFP+ optical module is arranged on the instruction card, and the SFP+ optical module is connected to the front panel.

[0008] In the above structure, an input control circuit is connected between the front panel and the input card; the input control circuit includes a MOS transistor Q1 and a first optocoupler; the MOS transistor Q1 is connected between the first optocoupler and the front panel; the first optocoupler is connected between the MOS transistor Q1 and the input card.

[0009] In the above structure, an output control circuit is connected between the front panel and the output card; the output control circuit includes MOS transistor Q2, MOS transistor Q3, a second optocoupler, and a third optocoupler; the MOS transistor Q2 is connected between the second optocoupler and the front panel; the second optocoupler is connected between the MOS transistor Q1 and the output card; the MOS transistor Q3 is connected between the output card and the third optocoupler; the third optocoupler is connected between the MOS transistor Q3 and the connection line between the MOS transistor Q2 and the front panel.

[0010] In the above structure, the 3U VPX connectors each include a VPX0 interface, a VPX1 interface, and a VPX2 interface. Among them, the 3U VPX connectors respectively connected to the main control card, the input card, and the output card are connected to the main control card, the input card, and the output card through the VPX0 interface, the VPX1 interface, and the VPX2 interface; the 3U VPX connector connected to the instruction card is connected to the instruction card through the VPX0 interface and the VPX1 interface.

[0011] In the above structure, the front panel is provided with a J30J interface, an HJ30J interface, a DEBUG interface, and status indicators; the J30J interface is connected to the input card, the output card, the MOS transistor Q1, and the MOS transistor Q2; the HJ30J interface is connected to the instruction card; the DEBUG interface is connected to the main control card; the status indicators are connected to the instruction card, the input card, and the output card.

[0012] In the above structure, the input card, the instruction card, and the output card are all FPGA boards, and the model of each is MX7K360.

[0013] In the above structure, the information processing carrier board based on the 3U VPX architecture further includes several IIC buses; the main control card is connected to the FPGA board through the IIC buses.

[0014] In the above structure, communication modules are connected between the backplane and the main control card, the input card, the instruction card, and the output card. The communication module includes an AT4307 connector and an MCU. The AT4307 connector is connected between the backplane and the MCU, and the MCU is connected between the AT4307 and the main control card / input card / instruction card / output card.

[0015] In the above structure, the information processing carrier board based on the 3U VPX architecture further includes a power card and a time card. The power card and the time card are both connected to the backplane through 3U VPX connectors, and the power card and the time card are both connected to the main control card, the input card, the instruction card, and the output card.

[0016] In the above structure, the model of the main control card is FT-D2000 / 8.

[0017] The beneficial effects of the present utility model are as follows: By connecting several 3U VPX connectors between the backplane and the main control card, instruction card, input card, and output card respectively, the computing and signal processing performance of the information processing carrier board is optimized. By providing 4 SFP+ optical modules on the instruction card and using the SERDES signal as the communication protocol, the information transmission efficiency can reach 10G, thereby improving the information processing and data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the overall circuit connection schematic diagram of an information processing carrier board based on the 3U VPX architecture of the present utility model Figure 1 ;

[0019] Figure 2 is the overall circuit connection schematic diagram of an information processing carrier board based on the 3U VPX architecture of the present utility model Figure 2 ;

[0020] Figure 3 is the circuit connection diagram of the main control card of an information processing carrier board based on the 3U VPX architecture of the present utility model;

[0021] Figure 4 is the circuit connection diagram of the instruction card of an information processing carrier board based on the 3U VPX architecture of the present utility model;

[0022] Figure 5 is the circuit connection diagram of the input card of an information processing carrier board based on the 3U VPX architecture of the present utility model;

[0023] Figure 6 is the circuit connection diagram of the output card of an information processing carrier board based on the 3U VPX architecture of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0025] The concept, specific structure, and technical effects of the present utility model will be clearly and completely described below in conjunction with the embodiments and drawings to fully understand the purpose, features, and effects of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all embodiments. Based on the embodiments of the present utility model, other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present utility model. In addition, all the connection / connection relationships involved in the patent do not refer to the direct connection of components alone, but refer to the formation of a more optimal connection structure by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the present utility model can be combined with each other without conflicting with each other.

[0026] Referring to Figure 1 and Figure 3 As shown, the present utility model discloses an information processing carrier board based on a 3U VPX architecture. The information processing carrier board based on the 3U VPX architecture includes a backplane, a main control card, an instruction card, an input card, an output card, a front panel, a power card, and a time card. The main control card, the instruction card, the input card, and the output card are connected between the backplane and the front panel. A plurality of 3U VPX connectors are provided on the backplane, and the backplane is connected to the main control card, the instruction card, the input card, the output card, the power card, and the time card through the 3U VPX connectors. Four SFP+ optical modules are provided on the instruction card, and the SFP+ optical modules are connected to the front panel. Both the power card and the time card are connected to the main control card, the input card, the instruction card, and the output card.

[0027] In this embodiment, the information processing carrier board based on the 3U VPX architecture includes a backplane, a main control card, an instruction card, an input card, an output card, and a front panel. Among them, the backplane is the foundation of the entire carrier board, carrying the connections of all components. That is, multiple 3U VPX connectors are installed on the backplane, and these connectors provide physical interfaces for connecting the main control card, the instruction card, the input card, and the output card. The main control card is the core of the entire system, responsible for managing and coordinating various functional modules on the carrier board. It is connected to the 3U VPX connectors on the backplane and transmits data and control signals to other cards through these connectors. The instruction card is usually responsible for processing specific instructions or algorithms to execute specific functions on the carrier board. Four SFP+ optical modules are provided on the instruction card for data transmission. Among them, the SFP+ optical module (10 Gigabit Small Form Factor Pluggable) is a hot-pluggable optical transceiver independent of the communication protocol. The optical wavelength it usually transmits is 850nm, 1310nm, or 1550nm, and it is used in 10Gbps SONET / SDH, Fibre Channel, Gigabit Ethernet, 10 Gigabit Ethernet, and other applications, including DWDM links. The input card is responsible for receiving external input data or signals and passing them to the main control card or the instruction card for processing. The input card is connected to one of the 3U VPX connectors on the backplane to communicate with other components. The output card is responsible for outputting the processed data or signals to external devices or systems. It is also connected to one of the 3U VPX connectors on the backplane to communicate with other cards. The front panel is the external interface of the carrier board, providing physical access to internal components. The power card is responsible for providing stable power for the entire carrier board to ensure that each card can work properly. The power card is strictly designed according to the VPX standard and adopts a conduction-cooled fixing method. Specifically, it is designed as a multi-output isolated power supply with a wide input voltage range, high efficiency, and high reliability, and is mainly applied to industrial control systems, communication networks, and other fields. The time card provides time synchronization and clock signals to ensure the timing consistency of each module in the system, which is particularly important in applications that require precise time control. When implementing the present utility model specifically, the information processing carrier board based on the 3U VPX architecture is respectively connected between the backplane and the main control card, the instruction card, the input card, the output card, the time card, and the power card through several 3U VPX connectors to optimize the computing and signal processing performance of the information processing carrier board. By providing four SFP+ optical modules on the instruction card and using the SERDES signal as the communication protocol, the information transmission efficiency can reach 10G, thereby improving the information processing and data transmission efficiency.

[0028] Refer to Figures 3 - 6As shown, the 3U VPX connectors each include a VPX0 interface, a VPX1 interface, and a VPX2 interface. Among them, the 3U VPX connectors respectively connected to the main control card, the input card, and the output card are connected to the main control card, the input card, and the output card through the VPX0 interface, the VPX1 interface, and the VPX2 interface; the 3U VPX connector connected to the instruction card is connected to the instruction card through the VPX0 interface and the VPX1 interface;

[0029] It should be noted that the 3U VPX connectors are a type of standardized connectors used in embedded computing and communication systems. They usually include multiple interfaces, such as VPX0, VPX1, and VPX2. Each interface is used for specific types of data transmission and communication, and the design of each 3U VPX connector allows for multiple different connection configurations to meet the communication requirements between different cards in the system; in this embodiment, each 3U VPX connector includes a VPX0 interface, a VPX1 interface, and a VPX2 interface. These interfaces define different signals and data paths in the 3U VPX standard. They are usually used to connect different functional modules or cards to achieve data transmission and communication, enabling the main control card to effectively control and manage the data flow of the input card and the output card, thus completing the function of the entire information processing carrier board. In short, the presence of the 3U VPX connectors ensures stable and efficient data exchange between the key components (main control card, input card, output card, and instruction card) of the information processing carrier board, and can meet the requirements of high-performance information processing systems for speed and reliability.

[0030] Continue to refer to Figures 3 - 6As shown in the figure, the front panel is provided with a J30J interface, an HJ30J interface, a DEBUG interface and status indicators; the J30J interface is connected to the input card and the output card; the HJ30J interface is connected to the instruction card; the DEBUG interface is connected to the main control card; the status indicators are connected to the instruction card, the input card and the output card. In this embodiment, the front panel is provided with a J30J interface, an HJ30J interface, a DEBUG interface and status indicators; among them, the J30J interface is used to connect the input card and the output card. The input card is usually used to receive external data or signals, and the output card is used to send the processed data or signals. The J30J interface provides a two-way data transmission path, enabling the information processing board to effectively receive and send information; the HJ30J interface is used to connect the instruction card. Since the instruction card is usually responsible for controlling and executing specific instructions and operations in the system, and for passing instructions and responses between the main control card and other components, through the HJ30J interface, the instruction card can receive instructions from the main control card and execute corresponding operations; the DEBUG interface is used to connect the main control card. In an embedded system, the DEBUG interface is usually used for system debugging and monitoring. Through this interface, developers can obtain key information during system operation for debugging and performance optimization; the status indicators are used to display the operating status and working status of each part of the system, enabling the staff to intuitively determine whether the carrier board is working properly and whether there is data transmission. When implementing the present invention specifically, the front panel is provided with different interfaces and status indicators to effectively manage and control the data flow, instruction transfer and operating status in the system, thereby ensuring that the system can operate efficiently and stably.

[0031] Refer to Figures 2 - 6 As shown in the figure, the input card, the instruction card and the output card are all FPGA boards, and their models are all MX7K360;

[0032] It should be noted that the input card, the instruction card and the output card are FPGA boards with the same model but different configurations, where:

[0033] The input card integrates 8GB of DDR4 memory with a bit width of 64 bits, and supports 1 PCIE signal, 1 SPI signal and 8 GPIO for communication with the main control card. It supports two groups of 4 SR IO signals and two groups of 16 single-ended signals for interconnection between instruction cards. At the same time, it supports 16 single-ended signals to be connected to the output card, and supports 3 single-ended signals to interact with the time card for time information (PPS, TOD, 10MHz reference clock). And through the front panel, 1 JTAG debug port, 16 IO ports (for internal debugging of the instruction card) and 4 operating status indicators are arranged;

[0034] The output card integrates 8GB of DDR4 memory with a bit width of 64 bits. The output card communicates with the main control card through 1 PCIE signal and 8 single-ended signals on the backplane, interacts with 3 instruction cards through 3×16 single-ended signals, interacts with the input card through 24 single-ended signals, and interacts with the time card through 3 single-ended signals to transmit time information (PPS, TOD, 10MHz reference clock). Additionally, 1 JTAG debug port, 24 isolated outputs with feedback (output voltage: 24V) and status indicators, and 4 operating status indicator lights are arranged on the front panel.

[0035] The input card integrates 8GB of DDR4 memory with a bit width of 64 bits. It communicates with the main control card through 1 PCIE signal, 1 SPI signal, and 8 single-ended signals on the backplane, interacts with the output card through 24 single-ended signals, and interacts with the time board through 3 single-ended signals to transmit time information (PPS, TOD, 10MHz reference clock). Also, 1 JTAG debug port, 32 isolated inputs (input voltage: 24V) and status indicators, and 4 operating status indicator lights are arranged on the front panel.

[0036] It should also be noted that the model of the main control card is FT-D2000 / 8, with a maximum processor frequency of 2.6GHz. It supports the military reinforcement structure of the board card, has strong functions, small size, and low power consumption, and is suitable for embedded computer scenarios with small computing workloads and low power consumption.

[0037] It should also be noted that the information processing carrier board based on the 3U VPX architecture further includes several IIC buses. The main control card is connected to the FPGA board through the IIC bus. In this example, the IIC bus is an SRIO high-speed serial communication bus, which has low latency, high bandwidth, and a rate of up to 10Gbps, and is used for the interconnection and information exchange of the FPGA board.

[0038] Refer to Figure 5 and Figure 6As shown, an input control circuit is connected between the front panel and the input card; the input control circuit includes MOS transistor Q1 and a first optocoupler; the MOS transistor Q1 is connected between the first optocoupler and the front panel; the first optocoupler is connected between the MOS transistor Q1 and the input card; an output control circuit is connected between the front panel and the output card; the output control circuit includes MOS transistors Q2, Q3, a second optocoupler, and a third optocoupler; the MOS transistor Q2 is connected between the second optocoupler and the front panel; the second optocoupler is connected between the MOS transistor Q1 and the output card; the MOS transistor Q3 is connected between the output card and the third optocoupler; the third optocoupler is connected between the MOS transistor Q3 and the connection line of the MOS transistor Q2 to the front panel; in addition, the MOS transistors Q1 and Q2 are connected to the front panel through the J30J interface.

[0039] In this embodiment, the input control circuit includes MOS transistor Q1 and a first optocoupler: through the connection of the MOS transistor Q1 and the first optocoupler in the input control circuit, the front panel and the input card realize the functions of electrical isolation and signal transmission; specifically, when the front panel needs to send data or control signals to the input card, the MOS transistor Q1 in the control circuit is activated, which causes the conduction state of the MOS transistor Q1, allowing current to be transmitted to the input card through the first optocoupler. Since the first optocoupler provides electrical isolation, the signal transmission between the front panel and the input card can be effectively isolated to avoid electrical interference and protect the circuit; the output control circuit includes MOS transistors Q2, Q3, a second optocoupler, and a third optocoupler. Through the connection methods of the MOS transistors Q2, Q3, the second optocoupler, and the third optocoupler in the output control circuit, effective data and control signal transmission between the front panel and the output card are realized; specifically, when the front panel needs to send data or control signals to the output card, the MOS transistor Q2 in the output control circuit is activated, which causes the conduction state of the MOS transistor Q2, allowing current to be transmitted to the output card through the second optocoupler. Similarly, the second optocoupler can protect the signal transmission between the front panel and the output card to avoid electrical interference; the MOS transistor Q3 and the third optocoupler form a feedback loop for monitoring the output state and adjusting the input signal or control signal according to the output situation. This feedback loop can be used to stabilize the system and prevent overload or out-of-control; in addition, the MOS transistors Q1 and Q2 are connected to the front panel through the J30J interface to ensure effective communication between the input control circuit, the output control circuit, and the front panel.

[0040] A communication module is connected between the backplane and the main control card, input card, instruction card, and output card. The communication module includes an AT4307 connector and an MCU. The AT4307 connector is connected between the backplane and the MCU, and the MCU is connected between the AT4307 and the main control card / input card / instruction card / output card.

[0041] In this embodiment, the communication module includes an AT4307 connector and an MCU. Among them, the AT4307 connector is used to achieve the physical connection between the backplane and the MCU, and the AT4307 connector can support the connection of multiple signal lines to ensure the efficient transmission of data. The MCU (micro control unit) integrates a processor, memory, and input / output interfaces, and is responsible for processing data and controlling communication. The MCU plays a bridging role in this carrier board, connecting the backplane with the main control card, input card, instruction card, and output card. When implementing the present utility model specifically, the communication module between the backplane and the main control card, input card, instruction card, and output card realizes efficient and reliable data transmission through the collaborative work of the AT4307 connector and the MCU. The MCU, as the core control unit of the carrier board, is responsible for processing and forwarding signals to ensure effective communication between each module. This design improves the flexibility and expandability of the carrier board, enabling different modules to work independently while being coordinated and managed through the MCU.

[0042] The above is a specific description of the preferred embodiment of the present utility model, but the creation of the present utility model is not limited to the above embodiment. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present utility model, and these equivalent deformations or substitutions are all included in the scope defined by the claims of this application.

Claims

1. An information processing carrier board based on a 3U VPX architecture, characterized in that: The information processing carrier board based on the 3U VPX architecture includes a backplane, a main control card, a command card, an input card, an output card and a front panel; the main control card, the command card, the input card and the output card are connected between the backplane and the front panel; The backplane is provided with a plurality of 3U VPX connectors, and the backplane is connected with the main control card, the instruction card, the input card and the output card through the 3U VPX connectors; The instruction card is provided with an SFP+ optical module, and the SFP+ optical module is connected to the front panel.

2. The information processing carrier board based on 3U VPX architecture according to claim 1, characterized in that: An input control circuit is connected between the front panel and the input card; the input control circuit includes a MOS tube Q1 and a first optical coupler; the MOS tube Q1 is connected between the first optical coupler and the front panel; the first optical coupler is connected between the MOS tube Q1 and the input card.

3. The information processing carrier board based on 3U VPX architecture according to claim 1, characterized in that: An output control circuit is connected between the front panel and the output card; the output control circuit includes a MOS tube Q2, a MOS tube Q3, a second optical coupler and a third optical coupler; the MOS tube Q2 is connected between the second optical coupler and the front panel; the second optical coupler is connected between the MOS tube Q1 and the output card; the MOS tube Q3 is connected between the output card and the third optical coupler; the third optical coupler is connected between the connection line between the MOS tube Q3 and the MOS tube Q2 and the front panel.

4. The information processing carrier board based on 3U VPX architecture according to claim 3, characterized in that: The 3U VPX connectors all include a VPX0 interface, a VPX1 interface and a VPX2 interface, wherein the 3U VPX connectors respectively connected to the main control card, the input card and the output card are connected to the main control card, the input card and the output card through the VPX0 interface, the VPX1 interface and the VPX2 interface; the 3U VPX connector connected to the instruction card is connected to the instruction card through the VPX0 interface and the VPX1 interface.

5. The information processing carrier board based on 3U VPX architecture according to claim 4, characterized in that: The front panel is provided with a J30J interface, an HJ30J interface, a DEBUG interface and a status indicator light; the J30J interface is connected to the input card, the output card, the MOS tube Q1 and the MOS tube Q2; the HJ30J interface is connected to the instruction card; the DEBUG interface is connected to the main control card; the status indicator light is connected to the instruction card, the input card and the output card.

6. The information processing carrier board based on 3U VPX architecture according to claim 1, characterized in that: The input card, instruction card and output card are all FPGA boards, and the model is MX7K360.

7. The information processing carrier board based on 3U VPX architecture according to claim 6, characterized in that: The information processing carrier board based on the 3U VPX architecture also includes a plurality of IIC buses; the main control card is connected to the FPGA board card via the IIC buses.

8. The information processing carrier board based on 3U VPX architecture according to claim 1, characterized in that: A communication module is connected between the backplane and the main control card, input card, command card and output card. The communication module includes an AT4307 connector and an MCU. The AT4307 connector is connected between the backplane and the MCU, and the MCU is connected between the AT4307 and the main control card / input card / command card / output card.

9. The information processing carrier board based on 3U VPX architecture according to claim 1, characterized in that: The information processing carrier board based on the 3U VPX architecture also includes a power card and a time card, both of which are connected to the backplane via a 3U VPX connector, and both of which are connected to the main control card, input card, instruction card and output card.

10. The information processing carrier board based on 3U VPX architecture according to claim 1, characterized in that: The model of the main control card is FT-D2000 / 8.

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