Fan-out and stacked system-level semiconductor packaging structure

Abstract

The utility model relates to the technical field of semiconductor packaging, and specifically relates to a fan-out and stacked packaging system-level semiconductor packaging structure. Comprising a first chip, a second chip, a third chip, a copper column and a plastic package material, copper wires are arranged at the two ends of the copper column, on the basis of an existing technology, a new system-in-package structure is adopted to meet the requirements of a product for high integration level, low cost performance, heat dissipation and the like, and the integration level of the product is improved through fan-out and stacking technologies; meanwhile, through material optimization and structure optimization, the stress of the product is greatly reduced, the service life of the product is prolonged, and the reliability of the product is improved; according to the design, the processing cost of the original packaging technology can be reduced, and the processing efficiency of the product is improved, so that the technical problem that the existing heat dissipation and interconnection technology cannot meet the corresponding heat requirement, the power integrity requirement and the high-speed signal transmission requirement of the product along with the large-scale popularization of high power and high frequency is effectively solved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a system-level semiconductor packaging structure for fan-out and stacked packaging. Background Art

[0002] Flip chip technology is an advanced microelectronic packaging technology that directly interconnects components downward to a substrate, carrier, or circuit board through bumps on the chip; due to its pinless structure and the characteristic that high I / O leads are distributed on the entire chip surface, this technology has significant advantages in packaging density and processing speed. In the prior art, after interconnecting the chip and the substrate using the flipchip process, heat conduction and interconnection of the product are achieved through heat conduction holes or heat conduction blocks on the substrate, thereby meeting the heat dissipation requirements and general applications of the product.

[0003] However, with the wide promotion of high power and high frequency, the existing heat dissipation and interconnection technologies cannot meet the requirements of the product for heat, power integrity, and high-speed signal transmission. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a system-level semiconductor packaging structure for fan-out and stacked packaging, aiming to solve the technical problem that with the wide promotion of high power and high frequency in the prior art, the existing heat dissipation and interconnection technologies cannot meet the requirements of the product for heat, power integrity, and high-speed signal transmission.

[0005] To achieve the above purpose, a system-level semiconductor packaging structure for fan-out and stacked packaging adopted by the utility model includes a first chip, a second chip, a third chip, copper pillars, and molding compound. Copper traces are provided at both ends of the copper pillars. The first chip, the second chip, and the third chip are all integrated on the copper pillars, and the copper pillars are integrated on the molding compound.

[0006] Among them, the first chip and the second chip are both located below the third chip, and the first chip and the second chip are symmetrically arranged.

[0007] Among them, the system-level semiconductor packaging structure for fan-out and stacked packaging further includes a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a fifth electronic component. The first electronic component, the second electronic component, the third electronic component, the fourth electronic component, and the fifth electronic component are all integrated on the copper pillars.

[0008] Among them, the first electronic component, the second electronic component, and the third electronic component are all located on one side of the third chip, and the fourth electronic component and the fifth electronic component are all located on the other side of the third chip.

[0009] Among them, the first chip is located on one side of the second chip, and the second chip is located above the third chip.

[0010] Among them, the fan-out and stacked system-level semiconductor packaging structure further includes a sixth electronic component, a seventh electronic component, an eighth electronic component, and a ninth electronic component, and the sixth electronic component, the seventh electronic component, the eighth electronic component, and the ninth electronic component are all integrated on the copper pillar.

[0011] Among them, the sixth electronic component and the seventh electronic component are located on one side of the third chip, the eighth electronic component is located below the first chip and also on the other side of the third chip, and the ninth electronic component is located on one side of the first chip.

[0012] A fan-out and stacked system-level semiconductor packaging structure of the present utility model includes a first chip, a second chip, a third chip, copper pillars, and a molding compound. Copper traces are provided at both ends of the copper pillars. The first chip, the second chip, and the third chip are all integrated on the copper pillars, and the copper pillars are integrated on the molding compound. Based on the existing process, a new system-level packaging structure is adopted to meet the product's requirements for high integration, low cost performance, and heat dissipation. Through fan-out and stacking technologies, the integration of the product is improved; at the same time, through material optimization and structure optimization, the stress of the product is greatly reduced, and the life and reliability of the product are improved; this design can reduce the processing cost of the original packaging technology and improve the processing efficiency of the product, thereby effectively solving the technical problems that with the large-scale popularization of high power and high frequency, the existing heat dissipation and interconnection technologies cannot meet the product's requirements for heat, power integrity, and high-speed signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0014] Figure 1 is a schematic structural diagram of a prior art product.

[0015] Figure 2 is a schematic structural diagram of the first embodiment of the present utility model.

[0016] Figure 3 is a schematic structural diagram of the second embodiment of the present utility model.

[0017] 1 - First chip, 2 - Second chip, 3 - Third chip, 4 - Copper pillar, 5 - Encapsulant, 6 - First electronic component, 7 - Second electronic component, 8 - Third electronic component, 9 - Fourth electronic component, 10 - Fifth electronic component, 11 - Sixth electronic component, 12 - Seventh electronic component, 13 - Eighth electronic component, 14 - Ninth electronic component, 15 - Copper trace, 16 - Pin pad. Detailed implementation manner

[0018] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention, but should not be construed as limiting the present invention.

[0019] First embodiment:

[0020] Please refer to Figure 2 , where Figure 2 is a schematic structural diagram of the first embodiment of the present invention.

[0021] The present invention provides a fan - out and stacked - package system - level semiconductor packaging structure, including a first chip 1, a second chip 2, a third chip 3, a copper pillar 4, an encapsulant 5, a first electronic component 6, a second electronic component 7, a third electronic component 8, a fourth electronic component 9, and a fifth electronic component 10.

[0022] For this specific implementation manner, copper traces 15 are provided at both ends of the copper pillar 4. The first chip 1, the second chip 2, and the third chip 3 are all integrated on the copper pillar 4, and the copper pillar 4 is integrated on the encapsulant 5. Starting from the deficiencies and process bottlenecks of the prior art, the requirements for high integration of system - level packaging technology are solved. Through stacking and fan - out technologies, the integration degree of the product is further improved; from the perspective of applicability, the stress of the product is reduced, the reliability of the product is improved, and the physical life and reliability of the product are greatly enhanced; at the same time, from the perspective of material application, the entire industrial chain is integrated. The original packaging technology that requires a substrate and encapsulant 5 is integrated into only the encapsulant 5 packaging technology; finally, from the perspective of packaging materials and structure, the materials of this packaging structure are simpler than traditional packaging, and the thermal stress problem caused by material differences can be significantly improved; combined with existing processes, the 3D interconnection technology of the product is realized, the flexible mounting of the chip is achieved, making the subsequent packaging forms more flexible and variable. At the same time, taking into account multiple means such as chip interconnection and copper pillar 4 bumping interconnection, the diversification of the product heat dissipation path is realized, and the requirements of low parasitics and low impedance for the product electrical interconnection are achieved.

[0023] Among them, the first chip 1 and the second chip 2 are both located below the third chip 3, and the first chip 1 and the second chip 2 are symmetrically arranged.

[0024] Secondly, the first electronic component 6, the second electronic component 7, the third electronic component 8, the fourth electronic component 9, and the fifth electronic component 10 are all integrated on the copper pillar 4, and the first electronic component 6, the second electronic component 7, the third electronic component 8, the fourth electronic component 9, and the fifth electronic component 10 are all integrated by resistors, capacitors, and inductors.

[0025] Thirdly, the first electronic component 6, the second electronic component 7, and the third electronic component 8 are all located on one side of the third chip 3, and the fourth electronic component 9 and the fifth electronic component 10 are all located on the other side of the third chip 3.

[0026] When using the present utility model for structural connection, the first step: electroplate a seed layer on the carrier board; the second step: expose, develop, and electroplate copper traces; the third step: expose, develop, and electroplate copper pillars, and remove the seed layer; the fourth step: encapsulate the copper traces 15 and the copper pillars 4; the fifth step: mount the first chip 1 and the second chip 2 with completed bumping bumps on the surface of the encapsulant 5; the sixth step: mount the preformed copper pillars 4 on the electroplated copper pillars; the seventh step: encapsulate the first chip, the second chip 2, and the preformed copper pillars 4; the eighth step: perform planar grinding to expose the bumping bumps of the first chip 1 and the second chip 2 and the copper pillars 4; the ninth step: after completing the electroplating of the seed layer, expose, develop, and electroplate copper traces; the tenth step: encapsulate the copper traces 15 and the copper pillars 4, and remove the seed layer; the eleventh step: if continuing to route or the copper pillars 4, steps five to seven can be cycled, with a maximum of 4 layers of copper traces 15; the twelfth step: remove the carrier board and turn the product over; the thirteenth step: perform reflow soldering and mounting of the third chip 3 and SMD on the copper traces 15; the fourteenth step: encapsulate the third chip 3 and SMD devices; the fifteenth step: perform pin electroplating; complete the product for testing.

[0027] The second embodiment is as follows:

[0028] Please refer to Figure 3 where Figure 3 is a schematic structural diagram of the second embodiment of the present utility model.

[0029] The present utility model provides a fan-out and stacked package system-level semiconductor package structure including a first chip 1, a second chip 2, a third chip 3, copper pillars 4, an encapsulant 5, a sixth electronic component 11, a seventh electronic component 12, an eighth electronic component 13, and a ninth electronic component 14.

[0030] For this specific embodiment, copper traces 15 are provided at both ends of the copper pillar 4. The first chip 1, the second chip 2, and the third chip 3 are all integrated on the copper pillar 4, and the copper pillar 4 is integrated on the encapsulant 5. Starting from the deficiencies and process bottlenecks of the prior art, the requirements for high integration of the system-level packaging technology are solved. Through stacking and fan-out technologies, the integration of the product is further improved; from the perspective of applicability, the stress of the product is reduced, the reliability of the product is improved, and the physical life and reliability of the product are greatly enhanced; at the same time, from the perspective of material application, the entire industrial chain is integrated. The original packaging technology that requires a substrate and the encapsulant 5 is integrated into only the encapsulant 5 packaging technology through integration; finally, from the perspective of packaging materials and structures, the materials of this packaging structure are simpler than those of traditional packaging, and the thermal stress problems caused by material differences can be significantly improved; combined with the existing process, the 3D interconnection technology of the product is realized, the flexible mounting of the chips is achieved, and the subsequent packaging forms are more flexible and diverse. At the same time, various means such as chip interconnection and copper pillar 4 bumping interconnection are taken into account, realizing the diversification of the product's heat dissipation path and meeting the requirements of low parasitics and low impedance for the electrical interconnection of the product.

[0031] Among them, the first chip 1 is located on one side of the second chip 2, and the second chip 2 is located above the third chip 3.

[0032] Secondly, the sixth electronic component 11, the seventh electronic component 12, the eighth electronic component 13, and the ninth electronic component 14 are all integrated on the copper pillar 4. The sixth electronic component 11, the seventh electronic component 12, the eighth electronic component 13, and the ninth electronic component 14 are all integrated by resistors, capacitors, and inductors.

[0033] Thirdly, the sixth electronic component 11 and the seventh electronic component 12 are located on one side of the third chip 3. The eighth electronic component 13 is located below the first chip 1 and also on the other side of the third chip 3. The ninth electronic component 14 is located on one side of the first chip 1.

[0034] When using the present utility model for structural connection, the first step: electroplating the pins of the electroplated plastic package and the copper column 4; the second step: encapsulating the pins and the copper column 4; the third step: electroplating the pads and traces of the third chip 3 and the SMD; the fourth step: performing reflow soldering and mounting of the third chip 3 and the SMD on the copper trace 15; the fifth step: mounting and soldering the preformed copper column 4; the sixth step: encapsulating the third chip 3, the SMD device and the copper column 4; the seventh step: grinding to expose the copper column 4; the eighth step: mounting the first chip 1, the second chip 2 core and the preformed copper column 4; the ninth step: encapsulating the first chip 1, the second chip 2 and the preformed copper column 4; the tenth step: grinding to expose the bump protrusions of the first chip 1 and the second chip 2 and the preformed copper column 4; the eleventh step: after completing the electroplating of the seed layer, performing exposure, development and electroplating of copper traces; the twelfth step: exposure, development and electroplating of copper columns, and removing the seed layer; the thirteenth step: encapsulating the copper trace 15 and the copper column 4; if continuing with traces or the copper column 4, steps five to seven can be cycled, with a maximum of four layers of the copper trace 15; the fourteenth step: pin electroplating; testing the completed product.

[0035] The above-disclosed is only a preferred embodiment of the present utility model. Of course, the scope of rights of the present utility model cannot be limited thereby. Those of ordinary skill in the art can understand the implementation of all or part of the above processes, and the equivalent changes made according to the claims of the present utility model still fall within the scope covered by the utility model.

Claims

1. A fan-out and stacked system-level semiconductor packaging structure, characterized in that: The invention comprises a first chip, a second chip, a third chip, a copper column and a plastic packaging material, wherein both ends of the copper column are provided with copper wiring, the first chip, the second chip and the third chip are integrated on the copper column, and the copper column is integrated on the plastic packaging material.

2. The fan-out and stacked system-level semiconductor packaging structure according to claim 1, wherein: The first chip and the second chip are both located below the third chip, and the first chip and the second chip are symmetrically arranged.

3. The fan-out and stacked system-level semiconductor packaging structure as claimed in claim 2, characterized in that: The fan-out and stacked system-level semiconductor packaging structure also includes a first electronic component, a second electronic component, a third electronic component, a fourth electronic component and a fifth electronic component, and the first electronic component, the second electronic component, the third electronic component, the fourth electronic component and the fifth electronic component are all integrated on the copper column.

4. The fan-out and stacked system-level semiconductor packaging structure as claimed in claim 3, characterized in that: The first electronic component, the second electronic component and the third electronic component are all located on one side of the third chip, and the fourth electronic component and the fifth electronic component are all located on the other side of the third chip.

5. The fan-out and stacked system-level semiconductor packaging structure according to claim 1, wherein: The first chip is located on one side of the second chip, and the second chip is located above the third chip.

6. The fan-out and stacked system-level semiconductor packaging structure as claimed in claim 5, characterized in that: The fan-out and stacked system-level semiconductor packaging structure also includes a sixth electronic component, a seventh electronic component, an eighth electronic component and a ninth electronic component, and the sixth electronic component, the seventh electronic component, the eighth electronic component and the ninth electronic component are all integrated on the copper pillar.

7. The fan-out and stacked system-level semiconductor packaging structure according to claim 6, wherein: The sixth electronic component and the seventh electronic component are located on one side of the third chip, the eighth electronic component is located below the first chip and also located on the other side of the third chip, and the ninth electronic component is located on one side of the first chip.

Images