Semiconductor device

Abstract

A semiconductor device includes a gate layer, a gate oxide layer and a plurality of semiconductor channels. The gate layer is disposed in one of the plurality of metallization layers over the semiconductor substrate and includes a plurality of gates. The gate oxide layer is disposed over the gates. The semiconductor channel is separated from the gate layer by the gate oxide layer. The semiconductor channels include a plurality of transistors of the first memory cell. The gate and the semiconductor channel are interconnected to form a plurality of layers of first memory cells including metallization structures.

Description

Technical Field

[0001] Embodiments of the present disclosure are substantially related to a semiconductor device. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the increase in integration density is due to the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. Summary of the Utility Model

[0003] The present disclosure provides a semiconductor device, comprising: a gate layer, a gate oxide layer, and several semiconductor channels. The gate layer is disposed in one of several metallization layers above a semiconductor substrate, wherein the gate layer comprises several gates. The gate oxide layer is disposed above these gates. These semiconductor channels are separated from the gate layer by the gate oxide layer, wherein these semiconductor channels comprise several transistors of a first memory cell. Wherein these gates and these semiconductor channels are interconnected to form a first memory cell, and the first memory cell comprises several layers of a metallization structure.

[0004] The present disclosure provides a semiconductor device, comprising: a first metallization layer, comprising a plurality of first conductors laterally separated from each other; a plurality of first semiconductor channels, disposed above the first metallization layer; a second metallization layer, disposed above those first semiconductor channels and comprising a plurality of second conductors; and a third metallization layer, disposed above the second metallization layer and comprising a plurality of third conductors; wherein at least four of those first conductors, at least six of those first semiconductor channels, at least three of those second conductors, and at least six of those third conductors are operable to form a memory cell.

[0005] The present disclosure provides a semiconductor device, comprising: a plurality of gate layers, each layer of those gate layers comprising a plurality of gates with an interlayer dielectric in the middle laterally; a plurality of drain / source connections, electrically connected to a plurality of semiconductor channels, those drain / source connections being electrically coupled to: a plurality of word line structures; and a connection of a first voltage level and a second voltage level of each of a pair of cross-coupled inverters, wherein those gate layers are joined by different threshold voltages. Description of the Drawings

[0006] When read in conjunction with the attached Figure 1 Aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0007] Figure 1Schematic diagram of a sandwich memory device according to some embodiments;

[0008] Figure 2 Example flowchart of a method for manufacturing a semiconductor device according to some embodiments;

[0009] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A and Figure 11B According to some embodiments, a top view and a cross-sectional view of an example semiconductor device manufactured by the method of Figure 2 at various manufacturing stages are shown;

[0010] Figure 12 According to some embodiments, a circuit corresponding to a 6T SRAM memory cell of a semiconductor device is shown;

[0011] Figure 13 According to some embodiments, a block diagram of a semiconductor device is shown;

[0012] Figure 14 Another example flowchart of a method for manufacturing a semiconductor device according to some embodiments;

[0013] Figure 15 、 Figure 16 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A 、 Figure 21B 、 Figure 22A 、 Figure 22B 、 Figure 23A 、 Figure 23B and Figure 23C According to some embodiments, a top view and a cross-sectional view of an example semiconductor device manufactured by the method of Figure 14 at various manufacturing stages are shown;

[0014] Figure 24 According to some embodiments, a circuit corresponding to the semiconductor device of Figures 14 to 23C is shown.

[0015]

Symbol description

[0016] 100: Memory cell

[0017] 102: (First) access transistor

[0018] 104: (Second) access transistor

[0019] 106: (First) inverter

[0020] 108: (Second) inverter

[0021] 110: First pull-up transistor

[0022] 112: First pull-down transistor

[0023] 114: Second pull-down transistor

[0024] 116: Second pull-up transistor

[0025] 118(VSS): (First) voltage level

[0026] 120(VDD): (Second) voltage level

[0027] 122: (First) bit line

[0028] 124: (Second) bit line

[0029] 126(Q): Storage node

[0030] 128(QB): Complementary storage node

[0031] 130: Gate layer

[0032] 132: Gate (word line gate)

[0033] 134: Gate (word line gate)

[0034] 136: Gate (first inverter gate)

[0035] 138: Gate (second inverter gate)

[0036] 140: Gate oxide layer

[0037] 142: Dielectric

[0038] 144: (First) interlayer

[0039] 146: (Second) interlayer

[0040] 148, 148A, 148B: Word line

[0041] 150: N-type channel

[0042] 152: P-type channel

[0043] 154: Contact

[0044] 156: Through-hole structure

[0045] 200: Method

[0046] 202, 204, 206, 208,

[0047] 210, 212, 214, 216: Operations

[0048] 300: Semiconductor device

[0049] 302: Semiconductor die

[0050] 304: Metallization layer

[0051] 306: Gate layer

[0052] 308: Second gate layer

[0053] 310: Third gate layer

[0054] 402: Gate oxide

[0055] 502: Gate isolation trench

[0056] 504: Isolation oxide

[0057] 602A: n-type channel

[0058] 602B: P-type channel

[0059] 702: Contact

[0060] 704: Scoring line

[0061] 802: (First) upright portion

[0062] 902: (First) interlayer

[0063] 1002: (Second) upright portion

[0064] 1102: (Second) interlayer

[0065] 1302: (First) memory sub-stack

[0066] 1304: (Second) memory sub-stack

[0067] 1306: (Third) memory sub-stack

[0068] 1308, 1308A, 1308B: Memory array

[0069] 1310: Word line driver

[0070] 1312, 1312A, 1312B: I / O Block

[0071] 1314: Memory Controller

[0072] 1400: Method

[0073] 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, 1418, 1420: Operations

[0074] 2202: (Third) Upright Portion

[0075] 2302: (Third) Interlayer Detailed Implementation Manner

[0076] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature is formed on or above a second feature, which may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure repeats reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself limit the relationship between the various embodiments and / or components discussed.

[0077] In addition, spatial relative terms such as "beneath", "below", "lower", "above", "upper", "top", "bottom" and similar terms are used herein for ease of description of the relationship between one element or component and another (some) element or component, as depicted in the accompanying drawings. Except for the directions depicted in the figures, spatial relative terms are intended to cover different directions of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptions used herein may be interpreted accordingly.

[0078] A semiconductor device can implement a register or a cache, etc., using a memory device such as an SRAM memory. The semiconductor device can include a semiconductor die having an active surface. The active surface can include various logic, memory, power management, or other transistors, diodes, fuses, etc. For example, various devices can include interconnections from a first metallization layer M0 disposed above the semiconductor die. Subsequent metallization layers (e.g., M1, M2, M3, etc.) can interconnect the first metallization layer to further interconnect the silicon die, or connect the silicon die to other silicon dies, other devices, or terminals of a semiconductor package. The conductors of the M0 layer may be constrained by the feature size of the silicon die, and any N-well or P-well may be constrained by design rules associated with the semiconductor die. The performance (e.g., access time, power loss, etc.) of the memory and other devices formed along the active surface of the semiconductor device may vary according to the capacitance or resistance of the interconnections. In addition, increasing the size of the memory may result in a corresponding increase in the die size, which may reduce yield, performance, or increase cost, etc.

[0079] Generally, the present disclosure relates to memory devices formed along the metallization layers of a semiconductor device. These layers can be formed according to a back end of line (BEOL) process. The BEOL process includes a manufacturing process for creating metal interconnections on multiple layers of a semiconductor device, such as to facilitate the flow of electrical signals between different components (e.g., dies or terminals) of the semiconductor device. The BEOL process may omit or relax various design rules associated with the front end of line (FEOL) process. The FEOL process includes manufacturing components such as transistors and diodes along the active surface of a semiconductor wafer. The design rules of the FEOL can include a smaller minimum feature distance, for example, manufacturing transistors and diodes that may be larger than the metal interconnections. The design rules of the FEOL can be applied to the memory formed at the active surface of the semiconductor die while maintaining the FEOL rules for other devices formed on the active surface (e.g., transistor logic, such as for a microcontroller). One or more layers of the semiconductor device can include gates, gate oxides, channels, and interconnections for memory cells. For example, the memory cells can include static random access memory (SRAM) cells, such as six transistor (6T), eight transistor (8T), or other transistor cells.

[0080] The metallization layer may include larger and lower-resistance interconnects than the lower layers of the metallization structure, and may have larger spacings therebetween, such that the memory cells disclosed herein may exhibit lower power consumption, lower capacitance, or faster access times than corresponding memories formed along the active surface of the die. Additionally, various such layers may be vertically spaced (e.g., stacked) along the semiconductor device. Various portions of the memory device may include different gate oxide thicknesses, channel sizes, etc., such that the threshold voltage, leakage current, etc. may vary between one or more memory cells. For example, the various layers of the semiconductor device may include high-performance cells with relatively low access times and relatively high leakage, low-power cells with relatively high access times and relatively low leakage, or balanced cells with medium access times and associated leakage.

[0081] Figure 1 An example of a sandwich memory cell 100 according to some embodiments is helpful for understanding Figure 2 method 200. The sandwich memory cell may include or represent memory cell 100, which has a channel and interconnects formed by the metallization layer of the semiconductor device. For example, the illustrated memory cell 100 may be one of various memory cells fabricated according to Figure 2 its operation. More specifically, the illustrated memory cell 100 is a 6T SRAM cell. Memory cell 100 includes a gate layer 130 that may be formed in a BEOL process. For example, memory cell 100 may be formed above the active surface of the semiconductor die or may be formed in a semiconductor device that does not include a semiconductor die. Memory cell 100 includes a first access transistor 102 and a second access transistor 104 that control access to the logic state of the device (e.g., access to a flip-flop including a first inverter 106 cross-coupled with a second inverter 108). The gate layer 130 may include word line gates 132, 134 for each of the first access transistor 102 and the second access transistor 104. The gate may selectively connect the state of the memory cell 100 to be read between a first bit line 122 and a second bit line 124.

[0082] The gate layer 130 includes a first inverter gate 136 for the first inverter 106 and a second inverter gate 138 for the second inverter 108. The first inverter 106 includes a first pull-up transistor 110 connected to a first voltage level (e.g., VSS) at the source / drain, a first pull-down transistor 112 connected to a second voltage level (e.g., VDD) at the source / drain, and the first inverter gate 136. The second inverter 108 includes a second pull-down transistor 114 connected to the first voltage level at the source / drain, a second pull-up transistor 116 connected to the second voltage level at the source / drain, and the second inverter gate 138.

[0083] The gate oxide layer 140 is interposed between the gate layer 130 and the channels of the respective transistors. The dielectric 142 can electrically isolate the respective gates 132, 134, 136, 138 of the gate layer 130. According to various embodiments, the same or another dielectric 142 (e.g., silicon dioxide) can extend over other portions of the memory cell 100. For example, the dielectric 142 can occupy the depicted negative space, which is shown removed for clarity in depicting other features of the memory cell 100.

[0084] The semiconductor channel can be disposed above the gate oxide layer 140. For example, the channel can include an N-type channel 150 or a P-type channel 152. Various embodiments of the present disclosure can employ various channel types for various transistors. For example, the depicted sandwich memory cell 100 includes four P-type channels 152 to form four P-type transistors and two N-type channels 150 to form two N-type transistors. Hereinafter, Figure 12 the circuit shows two P-type channels 152 to form two P-type transistors, and four N-type channels 150 to form four N-type transistors. The semiconductor channel can be connected to an electrical contact 154 (e.g., source / drain) to connect to the via structure 156.

[0085] The interconnection of the memory cell can be performed in multiple vertically spaced layers. For example, for each gate, the via structure 156 can extend between the gate or the channel and the first sandwich 144 of the memory cell 100. As shown, the first sandwich 144 includes a plurality of conductive elements, including: a word line 148 connecting the gates of the access transistors 102, 104; a storage node 126 connecting the gate of the second inverter 108 to a node that connects the source / drain of the first pull-up transistor 110, the first pull-down transistor 112, and the source / drain of the first access transistor 102; and a complementary storage node 128 connecting the gate of the first inverter 106 to a node that connects the source / drain of the second pull-up transistor 116, the second pull-down transistor 114, and the source / drain of the second access transistor 104.

[0086] The via structure 156 may also extend to the second interlayer 146 of the memory cell 100. As shown, the source / drain of the first pull-up transistor 110 and the second pull-down transistor 114 are connected to a conductive element at a first voltage level 118 (e.g., VSS); the source / drain of the first pull-down transistor 112 and the second pull-up transistor 116 are connected to a conductive element at a second voltage level 120 (e.g., VDD). The second interlayer 146 may also include connections to the first bit line 122 and the second bit line 124. The via structure 156 may include additional conductive elements or be connected to additional conductive elements, such as conductive metals on the first interlayer 144 or the second interlayer 146, or conductive contacts in the channel or gate. In various embodiments, such as embodiments employing additional transistors, the interconnects may be connected on a third interlayer or additional interlayers (not shown).

[0087] Figure 2 A flowchart of a method 200 of manufacturing a semiconductor device according to some embodiments is included. For example, at least some of the operations described in method 200 may result in Figure 1 、 Figures 3 to 13 the semiconductor device depicted in. The disclosed method 200 is disclosed as a non-limiting example and may provide additional operations before, during, and after Figure 2 method 200. Additionally, some operations are only briefly described herein, however, those skilled in the art will understand that the disclosed operations may be combined with other disclosed methods herein or with other disclosed methods known in the art. For example, it is noted that the present method contemplates forming a controller and I / O along the same lateral plane as the depicted memory cells, connecting the respective memory cells that are vertically offset from each other, connecting the respective memory cells as registers, characters, etc. to transfer data between the cells and the connections of the semiconductor die or semiconductor device terminals. Additionally, the order of the disclosed operations is not intended to be limiting; certain operations may be performed in a different order and may also be ordered by making appropriate modifications to additional operations.

[0088] Briefly, method 200 includes an operation 202 of forming a gate layer of a semiconductor device. Method 200 also includes an operation 204 in which a gate oxide is formed above the gate layer. Method 200 also includes an operation 206 in which various gates are defined from the gate layer. Method 200 also includes an operation 208 in which various semiconductor channels are formed. In operation 210, a first via structure portion is formed. The via structure portion may include a source / drain connection or a riser portion of the via. In operation 212, a first interlayer is formed. In operation 214, a second via structure portion is formed. In operation 216, a second interlayer is formed.

[0089] Corresponding to Figure 2 operation 202 of method 200, Figure 3 is a cross-sectional view of gate layer 306 of semiconductor device 300. For example, gate layer 306 may be formed above semiconductor die 302. Semiconductor die 302 may be a semiconductor substrate, such as a polysilicon wafer having an active surface including various doped surfaces. Metallization layer 304 may interconnect corresponding portions of the active surface to form circuits therebetween. The feature size of metallization layer 304 may vary such that layers closer to semiconductor die 302 may be smaller than the feature size away from semiconductor die 302. Metallization layer 304 may be connected to terminals such as micro-bumps, copper pillars, or another connection structure along a face of metallization layer 304 opposite semiconductor die 302. Metallization layer 304 may include various conductive materials such as copper, lead, silver, tin, aluminum, etc. Metallization layer 304 may include alternating conductive elements extending along a side surface of the device and via structures extending vertically to electrically connect the conductive elements. Metallization layer 304 may be made of one or more materials, such as the same material for different layers, different materials for different layers, or a combination of multiple layers (e.g., dual metal vias). According to various embodiments, various numbers of metallization layers 304 may be employed (e.g., depending on the circuit complexity or density on the active surface of semiconductor die 302, the desired number or type of memory cells, etc.). For example, according to some embodiments, at least about 5 or about 10 metallization layers 304 may be located between semiconductor die 302 and the depicted gate layer 306.

[0090] The gate layer 306 can be one of the metallization layers 304. For example, the gate layer 306 can be a metallization layer 304 made of the same or different materials. In various embodiments, the gate layer 306 can be formed of tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), polycrystalline silicon (poly-Si), or a combination of the foregoing. The gate layer 306 can include one or more of the same or different materials to be electrically connected to another layer in the metallization layer 304. The metallization layer 304 can be deposited by different processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, etc.

[0091] In some embodiments, the gate layer 306 may not be formed over the semiconductor die 302. For example, the gate layer 306 can be formed over a dielectric layer that includes terminal connections. Thereafter, the terminal connections can be used as a memory device, such as a memory device for coupling to a controller, input, and output, etc. on a printed circuit board. The memory device can be coupled to another device (e.g., a controller) that includes one or more logic circuits to access the memory device (e.g., store information thereon or retrieve stored information therefrom).

[0092] After operation 202, additional gate layers, such as a second gate layer 308, a third gate layer 310, etc., can be formed according to the processes described herein with respect to the gate layer 306. Additional memory cells 100 can be formed along each of the second gate layer 308 and the third gate layer 310 and connected through one or more via structures. Together with the additional memory cells 100, a memory controller, input or output connections (I / O) for data signals, a word line driver, etc. can be formed on a vertical portion of the semiconductor device 300 corresponding to each gate layer. Each additional memory cell layer can be configured to operate at the same or varying leakage levels, access speeds, etc. For the sake of clarity and brevity of description, Figures 4 to 12 the second gate layer 308 and the third gate layer 310 are omitted. Generally corresponding to Figures 4 to 12 a further illustration shows that a second memory cell 100 can be formed over the first memory cell and a third memory cell can be formed over the second memory cell. With respect to Figure 14 andFigure 23C An example of a semiconductor device 300 including multiple gate layers is provided.

[0093] Corresponding to Figure 2 operation 204 of method 200, Figure 4 is a cross-sectional view of semiconductor device 300, where a gate oxide 402 is formed above gate layer 306. A gate oxide layer 140 may be formed above gate layer 306 and then patterned to form the depicted gate oxide 402. The thickness of the oxide can be selected according to the desired characteristics of the memory cell (e.g., target access time or leakage current). Additional or fewer portions of gate oxide 402 may be formed according to the type of memory cell. For example, an 8T or 10T SRAM memory cell 100 may include additional portions of gate oxide 402.

[0094] In one non-limiting example, gate oxide 402 may be formed of a high-k dielectric material such as hafnium dioxide (HfO 2 ), which is deposited by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process using Hf and O 2 precursors. Another dielectric such as silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ) or silicon oxynitride (SiON) etc. may be deposited using CVD, plasma-enhanced chemical vapor deposition (PECVD), spin-on-glass (SOG) or ALD etc., all within the scope of this disclosure. A positive or negative photoresist process may selectively remove a portion of gate oxide 402 between gate oxide 402 and gate layer 306 to pattern the gate oxide 402 layer corresponding to the semiconductor channel position. Each successive portion of gate oxide 402 may correspond to the position of one or more semiconductor channels above the lateral surface of semiconductor device 300.

[0095] Corresponding to Figure 2 operation 206 of method 200, Figure 5is a cross-sectional view of a semiconductor device 300, in which gate isolation trenches 502 are formed to electrically isolate the respective portions of the gate layer 306 from each other. The isolated portions of the gate layer 306 may include one or more gate oxides 402 formed thereon. As with the other operations of the depicted method 200, the operations may be performed in various orders. For example, the gate oxide 402 may be deposited after or before the formation of the gate isolation trenches 502.

[0096] In some embodiments, the gate isolation trenches 502 are formed through the gate oxide 402 and the gate layer 306. An isolation oxide 504 or other dielectric may occupy the gate isolation trenches 502 to provide mechanical support and increase electrical isolation. The isolation oxide 504 may include Figure 4 any of the gate oxides 402 or other types of isolation dielectric materials mentioned in 2 , and may also be referred to as an inter-layer dielectric (ILD). For example, the ILD may include SiO 3 N 4 , HfO 2 , Al 2 O 3 or a combination of the foregoing, etc. In some embodiments, the ILD (isolation oxide 504) is formed of the same material as the gate oxide 402. In some embodiments, the ILD is formed of a material that is selectively etchable relative to the gate oxide 402 or the semiconductor channel 602 discussed below with respect to Figure 6 . The isolation oxide 504 may be selectively removed to form a contact electrically connected to the gate layer 306 (e.g., Figure 7A and Figure 7B the first via structure portion contact 702), or the first via structure portion contact 702 may be electrically connected to the gate layer 306 before forming the isolation oxide 504 over the gate layer 306. Additional portions of the gate layer 306 may be defined to form a controller for the memory cell 100 formed according to the method 200, a conductive element for a word line driver, etc. The additional portions may still form interconnections, such as for transmitting data from the memory cell 100 of the method 200 or data of a logic device vertically spaced from the memory cell 100.

[0097] Corresponds to Figure 2 operation 208 of the method 200, Figure 6is a top view of the semiconductor device 300, where a semiconductor channel 602 is formed above the gate oxide 402. The semiconductor channel 602 may include at least one n-type channel 602A and at least one p-type channel 602B. As described above, the various features provided herein are not drawn to scale. According to various embodiments, different transistors may be configured with different geometries, which may correspond to different drive strengths. For example, the length or width of the p-type channel 602B may be adjusted to match the drive strength of the n-type channel 602A. Additionally, one p-type channel 602B or n-type channel 602A may have different dimensions from another semiconductor channel 602 of the same type. For example, the semiconductor channel 602 for access transistors may have a different geometry compared to the semiconductor channel 602 for pull-up or pull-down transistors, corresponding to a higher drive strength (e.g., a wider channel), lower leakage power (e.g., a longer channel), etc.

[0098] Furthermore, the semiconductor channel 602 may vary according to the lateral or vertical position of the device. For example, the first layer of the device may include various memory cells 100, word line drivers, and controllers corresponding to the memory cells 100. The memory cells 100 in this layer may be of the same or different types. For example, the memory cells 100 in this layer may include various voltage thresholds, leakage currents, or configurations of p-type and n-type channels for implementing various transistor memory cells. The respective layers of the semiconductor device 300 may employ the same or different materials for the n-type channel 602A or p-type channel 602B. For example, for the n-type channel 602A, one or more layers may include indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium(III) oxide (In 2 O 3 ), tin(IV) oxide (SnO 2 ), indium gallium arsenide (InGaAs), carbon nanotube (CNT), transition metal dichalcogenide (TMD), or black phosphorus nanoribbon (BPNR), combinations of the foregoing, etc. Similarly, for the p-type channel 602B, one or more layers may include nickel oxide (NiO), copper(I) oxide (Cu 2 O), copper aluminum oxide (CuAlO 2) Copper gallium oxide; CuGaO 2 ) Copper indium oxide; CuInO 2 ) Strontium copper oxide; SrCu 2 O 2 ) Tin(II) oxide; SnO, and the foregoing combinations, etc.

[0099] In various embodiments, either an n-type channel 602A or a p-type channel 602B can be formed according to a patterning process, and then the other of the n-type channel 602A or the p-type channel 602B can be formed.

[0100] Corresponding to Figure 2 operation 210 of method 200, Figure 7A and Figure 7B are a top view and a cross-sectional view of semiconductor device 300, in which source / drain contact 702 is formed. Source / drain contact 702 can refer to the first part of via structure 156 of memory cell 100 or a part of the first part of via structure 156 of memory cell 100. For example, the first part of via structure 156 can include electrical contact 702 electrically coupled to gate layer 306 and electrically coupled to the upright portion of the via structure. Another contact 702 (e.g., a gate contact) can be connected to, for example, semiconductor channel 602 or gate oxide 402, and can be electrically coupled to the upright portion described below. As described above, contact 702 can be formed before or after isolation oxide 504. It is noted that, in some embodiments, contact 702 can be separated from a portion of semiconductor channel 602 by gate oxide 402. Contact 702 can be formed by depositing a metal layer over the surface of semiconductor device 300. Then the deposited metal layer is patterned using a lithography process, followed by a selective etching process to remove the unwanted portions of the metal layer and leave the desired pattern of contact 702. Contact 702 can be formed of various materials, such as tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), polycrystalline silicon (poly-Si), ruthenium (Ru), cobalt (Co), copper (Cu), etc. or combinations of the foregoing.

[0101] As Figure 7B illustrated in Figure 7AThe cross-sectional view can be along the drawn cut line 704. As Figure 7B Further shown therein, the contact 702 can electrically couple a plurality of semiconductor channels 602 to each other. For example, the contact 702 can be or include Figure 1 the various drain / source connections shown therein. The various cross-sectional views can follow various cut lines.

[0102] Continuing with operation 210 of method 200 corresponding to Figure 2 and Figure 8A and Figure 8B are a top view and a cross-sectional view of the semiconductor device 300, wherein a first upright portion 802 of a first part of the via structure 156 is formed above the contact 702. For clarity of description and brevity only, dielectric materials (e.g., ILD) for isolating conductive interconnects (e.g., via structures) are omitted in the figures and in other figures hereinafter.

[0103] It should be noted that such materials can be formed to fill the vertically disposed layers for the via structure 156 and the interlayer. For example, a conductive layer (such as the layer including the first upright portion 802) is deposited above the surface of the semiconductor device 300. A dielectric layer (not shown) is deposited above the top of the contact 702, the gate layer 306, or the gate oxide 402 using a suitable deposition technique (e.g., chemical vapor deposition or spin coating). Then, the dielectric layer is planarized using chemical-mechanical polishing or grinding (CMP / G) or other suitable processes to remove any excess material and form a smooth and uniform surface. Then, the planarized dielectric layer is etched using a suitable etching technique to produce an opening exposing the underlying contact 702, gate layer 306, or gate oxide 402. Then, the opening is filled with a suitable conductive material (e.g., copper or tungsten) using a deposition process such as electroplating or chemical vapor deposition to provide a conductive path between the contact 702, the gate layer 306, or the gate oxide 402 and the first interlayer of the semiconductor device 300, as described below.

[0104] Corresponding to Figure 2 operation 212 of method 200 corresponding to Figure 9A and Figure 9B are a top view and a cross-sectional view of the semiconductor device 300, wherein a first interlayer 902 is formed above its surface. For example, the first interlayer 902 can include various interconnects, which can correspond to Figure 12A portion of the circuit depicted in. Specifically, the first interlayer 902 may include word lines 148, storage nodes (Q) 126, complementary storage nodes (QB) 128, and conductive elements electrically coupled to the first upright portion 802. The interlayer 902 may be formed according to a method similar to that of other metallization layers 304 (such as the upright portion 802). For example, the interlayer 902 may be formed by depositing a metal layer over the surface of the semiconductor device 300. Then, the deposited metal layer is patterned using a lithography process, followed by a selective etching process to remove the unwanted portions of the metal layer and leave the desired pattern of the interlayer 902.

[0105] Corresponding to Figure 2 operation 214 of method 200, Figure 10A and Figure 10B are a top view and a cross-sectional view of the semiconductor device 300, in which a second upright portion 1002 forming a first portion of the via structure 156. The second upright portion 1002 may be formed according to the same techniques discussed for the first upright portion in Figure 8A and Figure 8B The same number of alternating additional interlayers and upright portions may be formed in a similar manner.

[0106] Corresponding to Figure 2 operation 216 of method 200, Figure 11A and Figure 11B are a top view and a cross-sectional view of the semiconductor device 300, in which a second interlayer 1102 is formed over its surface. The second interlayer 1102 may include various interconnects, which may correspond to Figure 12 a portion of the circuit depicted in. Specifically, the first interlayer 902 may include a first voltage level 118, a second voltage level 120, a first bit line 122, and a second bit line 124. Various voltage levels (e.g., for pull-up or pull-down transistors) may be connected to other layers or other portions of the semiconductor device 300, such as a redistribution layer for a ground plane or a VCC level. The second interlayer 1102 may extend its conductive portions to one or more I / O regions for various memory cells. Various I / Os may be connected between multiple layers of the semiconductor device 300, such as to the active surface of the semiconductor die. For example, the depicted bit lines 122, 124 may be directly connected to the die, or connected to the die through a data bus arbitration line (not shown).

[0107] Now refer to Figure 12, according to some embodiments, there is provided a schematic diagram 1200 of a circuit corresponding to a 6T SRAM memory cell of a semiconductor device 300. The schematic diagram 1200 includes a first inverter 106 cross-coupled with a second inverter 108. Each of the first inverter 106 and the second inverter 108 includes a pull-up / pull-down transistor pair respectively connected to each of a first voltage level 118 depicted as VSS and a second voltage level 120 depicted as VDD. A word line 148 selectively connects the respective inverters 106, 108 to each of a first bit line 122 and a second bit line 124.

[0108] Now referring to Figure 13 , according to some embodiments, there is provided a block diagram 1300 for a semiconductor device 300. The block diagram 1300 includes a first memory sub-stack 1302, a second memory sub-stack 1304, and a third memory sub-stack 1306. Each sub-stack may include one or more layers, such as corresponding to Figure 11A , Figure 23B or Figure 23C the depicted layers.

[0109] Each memory sub-stack 1302 may include one or more memory arrays 1308, such as the depicted first memory array 1308A and second memory array 1308B. A memory controller 1314 may cause a word line driver 1310 to select respective columns of memory cells 100 for read or write operations and transmit messages to the cells through an I / O block 1312. For example, a first I / O block 1312A may correspond to the first memory array 1308A, and a second I / O block 1312B may correspond to the second memory array 1308B.

[0110] Each of the memory arrays 1308 may include one or more cell types. For example, the first memory array 1308A and the second memory array 1308B may be the same or different memory cell types, and further may be the same or different memory cell types relative to the memory arrays 1308 of the second memory sub-stack 1304 or the third memory sub-stack 1306. For example, the channel size, gate oxide thickness, or material, etc. may vary to produce memory cells with various conditions (e.g., power optimized for low leakage, high access time, or performance optimized for high leakage, low access time, etc.).

[0111] Figure 14 is a flowchart of another example of a method 1400 for manufacturing a semiconductor device 300 according to some embodiments. For example, at least some of the operations described in the method 1400 may produce Figures 14 to 23C the depicted 8T SRAM memory cell 100, corresponding to Figure 24Schematic diagram 2400. The disclosed method 1400 is disclosed as a non-limiting example and can provide additional operations before, during, and after Figure 14 method 1400. In addition, only some operations are briefly described herein. However, those skilled in the art will understand that the disclosed operations can be combined with other disclosed methods herein or with other disclosed methods known in the art. In addition, the order of the disclosed operations is not intended to be limiting; certain operations can be performed in a different order and can also be sorted by making appropriate modifications to additional operations.

[0112] Briefly, method 1400 includes an operation 1402 of forming a gate layer of semiconductor device 300. Method 1400 also includes an operation 1404 in which a gate oxide is formed above the gate layer. Method 1400 also includes an operation 1406 in which various gates are defined by the gate layer. Method 1400 also includes an operation 1408 in which various semiconductor channels are formed. In operation 1410, a first via structure portion is formed. The via structure portion can include a source / drain connection or an upright portion of the via. In operation 1412, a first interlayer is formed. In operation 1414, a second upright portion of a second via structure portion is formed. In operation 1416, a second interlayer is formed. In operation 1418, a third upright portion of a third via structure portion is formed. In operation 1420, a third interlayer is formed.

[0113] Some operations of the disclosed method 1400 can be similar to Figure 2 the operations of method 200, and the details corresponding to these operations will not be repeated. However, additional drawings are also included to disclose an example 8T memory cell. This example is an illustrative example and is not intended to be limiting. Various wirings for interconnection can be formed according to various embodiments, and additional memory cells (e.g., 9T cells or 10T cells) can be formed according to this disclosure. Operation 1402 corresponds to Figure 2 operation 202. Operation 1404 corresponds to Figure 2 operation 204. In the illustrated example, an additional gate oxide 402 can be formed above the gate layer 306, corresponding to an additional transistor of the 8T memory cell 100, as Figure 15 illustrated. Operation 1406 corresponds to Figure 2 operation 206. Operation 1408 corresponds to Figure 2 operation 208. In the illustrated example, additional semiconductor channels 602 (e.g., n-type channel 602A and p-type channel 602B) can be formed above the gate oxide 402. Again, Figure 16The examples depicted are not intended to be limiting. In various embodiments, the 8T SRAM memory cell 100 may include: two n-type channels 602A for the read port, along with four additional n-type channels 602A and two p-type channels 602B; two p-type channels 602B for the read port, along with four additional p-type channels 602B and two n-type channels 602A; two n-type channels 602A or two p-type channels 602B for the read port, along with two channels of the same type, and four additional p-type channels 602B or four additional n-type channels 602A.

[0114] Operation 1410 corresponds to Figure 2 operation 210. Figure 17A and Figure 17B FIGS. and respectively illustrate a cross-sectional view and a top view of the semiconductor device 300, which includes contacts 702 (source / drain contacts 702) electrically coupled to the semiconductor channel. Further corresponding to operation 1410, Figure 18A and Figure 18B illustrate a first upright portion 802 formed above the contact 702. Operation 1412 corresponds to Figure 2 operation 212. As shown in Figure 19A and Figure 19B depicted, the first interlayer 902 includes a write word line 148A, a first bit line 122, a second bit line 124, and a voltage level line, such as the depicted first voltage level 118 (e.g., VSS). Operation 1414 corresponds to Figure 2 operation 214, as shown in Figure 20A and Figure 20B depicted. Operation 1416 corresponds to Figure 2 operation 216. The second interlayer 1102 is illustrated in the cross-sectional view of Figure 21A and the top view of Figure 21B As shown, the second interlayer 1102 includes a first voltage level 118 and a second voltage level 120, a first bit line 122, and a second bit line 124. An additional word line 148 (e.g., the depicted read word line 148B) extends from the gate layer 306 through the electrically coupled via structure 156 (e.g., including the contact 702, the first upright portion 802, the first interlayer 902, the second upright portion 1002, and the second interlayer 1102).

[0115] Corresponding to Figure 14 operation 1418 of the method 1400, Figure 22A and Figure 22Bare a top view and a cross-sectional view of semiconductor device 300, in which a third vertical portion 2202 that forms a first portion of via structure 156. The third vertical portion 2202 can be formed according to the same techniques discussed with respect to the second vertical portion 1002 or the first vertical portion 802.

[0116] corresponds to Figure 14 operation 1420 of method 1400, Figure 23A and Figure 23B are a top view and a cross-sectional view of semiconductor device 300, in which a third interlayer 2302 is formed. The third interlayer 2302 can include various interconnects and can correspond to Figure 24 a portion of the circuitry depicted in. For example, the third interlayer 2302 can include a lateral portion of read word line 148B. As described above, semiconductor device 300 can include a second gate layer 308, a third gate layer 310, etc., that are vertically spaced along semiconductor device 300. In some embodiments, each memory cell 100 that includes a gate on a respective gate layer (e.g., second gate layer 308) can include multiple portions disposed on the same semiconductor layer. For example, Figure 23C illustrates Figure 22B memory cell 100 and another read word line 148B, which can be a read word line 148B for another memory cell. For example, the stacked memory cells 100 can be configured to have a read word line 148B (or other interconnect) disposed above its gate layer or a read word line 148B (or other interconnect) disposed below its gate layer, which can increase device density, reduce resistive losses of signals passing through semiconductor device 300, etc.

[0117] Now refer to Figure 24 , which, in accordance with some embodiments, provides a schematic diagram 2400 of a circuit corresponding to 8T SRAM memory cell 100 of semiconductor device 300. Schematic diagram 2400 includes a first inverter 106 cross-coupled with a second inverter 108. Each of the first inverter 106 and the second inverter 108 includes a pull-up / pull-down transistor pair that are respectively connected to each of a first voltage level 118 depicted as VSS and a second voltage level 120 depicted as VDD. Write word line 148A selectively connects the respective inverters 106, 108 to each of first bit line 122 and second bit line 124. Read word line 148B selectively connects the respective inverters 106, 108 to a voltage level and each of first bit line 122.

[0118] In one aspect of the present disclosure, a method for manufacturing a semiconductor package is disclosed. The method includes: depositing a metal to form a gate layer for a first memory cell in a metallization layer of a semiconductor device. The method includes: forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes: defining a plurality of gates from the gate layer. The method includes: interconnecting those gates and those semiconductor channels to form a first memory cell, wherein the interconnecting includes a plurality of interlayers.

[0119] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a plurality of gate layers, each gate layer including a plurality of gates disposed laterally along a surface of the semiconductor device, those gates being separated by an interlayer dielectric. The semiconductor device includes: a plurality of drain / source connections electrically connected to a plurality of semiconductor channels. Those drain / source connections are electrically coupled to: a plurality of word line via structures. Those drain / source connections are electrically coupled to: connections of a first voltage level and a second voltage level of each of a pair of cross-coupled inverters, wherein those gate layers can be joined by different threshold voltages.

[0120] In another aspect of the present disclosure, a system is disclosed. The system includes: a plurality of metallization layers on a semiconductor die. The first layer of those metallization layers includes: a first gate oxide between a first gate layer and a plurality of first semiconductor channels, those first semiconductor channels forming a first pair of cross-coupled inverters configured as a first storage node and a first complementary storage node. The first layer of those metallization layers further includes: a controller configured to transfer first data between the first storage node and the semiconductor die. The second layer of those metallization layers can include: a second gate oxide between a second gate layer and a plurality of second semiconductor channels, those second semiconductor channels forming a second pair of cross-coupled inverters configured as a second storage node and a second complementary storage node. The second layer of those metallization layers can include: a second controller configured to transfer second data between the second storage node and the semiconductor die. The metallization layers include: a plurality of additional first metallization layers including a plurality of first interlayers configured to interconnect the first layer of those metallization layers. The metallization layers include: a plurality of additional second metallization layers including a plurality of second interlayers, those second interlayers configured to interconnect the second layer of those second metallization layers.

[0121] In another aspect of the present disclosure, a method for manufacturing a semiconductor package is disclosed. The method includes: forming a gate layer in one of a plurality of metallization layers above a semiconductor substrate. The method includes: defining a plurality of gates from the gate layer; the method includes: forming a gate oxide layer above those gates. The method includes: forming a plurality of semiconductor channels separated from the gate layer by the gate oxide layer, those semiconductor channels defining a plurality of transistors of a first memory cell. The method includes: interconnecting those gates and those semiconductor channels to form a first memory cell, wherein the first memory cell includes a plurality of layers of a metallization structure. In some embodiments, wherein the gate layer is formed above a semiconductor die, and the gate layer includes tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), or a combination of the foregoing. In some embodiments, the method further includes: forming a plurality of metallization layers above the semiconductor die, wherein the gate layer is not one of the first five metallization layers disposed above the semiconductor die. In some embodiments, the method further includes: forming a second gate layer for a second memory cell, the second gate layer being vertically spaced apart from the gate layer of the semiconductor device; forming a plurality of second semiconductor channels separated from the second gate layer by a second gate oxide layer; defining a plurality of second gates from the second gate layer; and interconnecting those second gates and those second semiconductor channels to form a second memory cell, wherein the second memory cell includes a plurality of second layers of a metallization structure. In some embodiments, wherein at least one of those layers of the metallization structure is not vertically spaced apart from at least one of those second layers of the metallization structure. In some embodiments, wherein the dimensions of those semiconductor channels are different from the dimensions of those second semiconductor channels, such that the access time or leakage current of the first memory cell is different from the access time or leakage current of the second memory cell. In some embodiments, wherein the semiconductor channels include a plurality of p-type channels and a plurality of n-type channels, and wherein the dimensions of those p-type channels are different from the corresponding dimensions of those n-type channels. In some embodiments, wherein the first layer of those layers of the metallization structure includes word line interconnects, storage node interconnects, and complementary storage node interconnects. In some embodiments, wherein the second layer of those layers of the metallization structure includes a first bit line interconnect and a second bit line interconnect. In some embodiments, wherein the third layer of those layers of the metallization structure includes a second word line of the first memory cell, and a word line of the second memory cell. In some embodiments, wherein the first memory cell and the second memory cell have different threshold voltages.

[0122] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first metallization layer having a plurality of first conductors laterally separated from each other. The semiconductor device includes: a plurality of first semiconductor channels disposed above the first metallization layer. The semiconductor device includes: a second metallization layer disposed above those first semiconductor channels and including a plurality of second conductors. The semiconductor device includes: a third metallization layer disposed above the second metallization layer and including a plurality of third conductors. At least four of those first conductors, at least six of those first semiconductor channels, at least three of those second conductors, and at least six of those third conductors operably form a memory cell. In some embodiments, the first metallization layer is one of a plurality of first metallization layers vertically spaced apart from each other and vertically spaced from the semiconductor die. In some embodiments, each layer of the plurality of first metallization layers includes: a memory controller laterally spaced from a plurality of word line structures; and a word line driver laterally spaced from the memory controller. In some embodiments, the semiconductor device further includes: a 6T memory cell; and an 8T memory cell vertically spaced from the 6T memory cell. In some embodiments, the semiconductor channel includes: an n-type channel including: indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), tin dioxide (SnO 2 ), indium gallium arsenide (InGaAs), carbon nanotube (CNT), transition metal dichalcogenide (TMD), black phosphorus nanoribbon (BPNR), or a combination of the foregoing; and a p-type channel including: nickel oxide (NiO), cuprous oxide (Cu 2 O), copper aluminum oxide (CuAlO 2 ), copper gallium oxide (CuGaO 2 ), copper indium oxide (CuInO 2 ), strontium copper oxide (SrCu 2 O 2 ), tin monoxide (SnO), or a combination of the foregoing. In some embodiments, a first via structure electrically connects a first layer of those first metallization layers to the same layer as a second via structure that electrically connects a second layer of those first metallization layers, wherein the first via structure and the second via structure are not electrically connected in the same layer.

[0123] In another aspect of the present disclosure, a semiconductor device is disclosed. This semiconductor device includes: a plurality of gate layers, each of those gate layers including a plurality of gates with an interlayer dielectric in the middle horizontally. This semiconductor device includes: a plurality of drain / source connections, electrically connected to a plurality of semiconductor channels. Those drain / source connections are electrically coupled to a plurality of word line via structures. Those drain / source connections are electrically coupled to the connection points of the first voltage level and the second voltage level of each of a pair of cross-coupled inverters, where those gate layers are joined with different threshold voltages. In some embodiments, where those gates are connected to semiconductor dies vertically spaced apart from those gate layers. In some embodiments, it further includes: a layer including a metallization structure for one of the plurality of word line structures, and this layer alternates between vertically adjacent ones of those gate layers with respect to those gate layers.

[0124] In another aspect of the present disclosure, a semiconductor device is disclosed. This semiconductor device includes a gate layer, a gate oxide layer, and several semiconductor channels. The gate layer is disposed in one of several metallization layers above a semiconductor substrate, where the gate layer includes several gates. The gate oxide layer is disposed above these gates. These semiconductor channels are separated from the gate layer by the gate oxide layer, where these semiconductor channels include several transistors of a first memory cell. Where these gates and these semiconductor channels are interconnected to form a first memory cell, and the first memory cell includes several layers of a metallization structure.

[0125] In some embodiments, this semiconductor device further includes a second gate layer of a second memory cell and several second semiconductor channels. The second gate layer of the second memory cell is vertically spaced apart from the gate layer of the semiconductor device. The second semiconductor channels are separated from the second gate layer by a second gate oxide layer, where the second gate layer includes several second gates. Where these second gates and these second semiconductor channels are interconnected to form a second memory cell, and the second memory cell includes several second layers of a metallization structure. In some embodiments, where the first layer of these layers of the metallization structure includes word line interconnections, storage node interconnections, and complementary storage node interconnections. In some embodiments, where the second layer of these layers of the metallization structure includes a first bit line interconnection and a second bit line interconnection. In some embodiments, where the third layer of these layers of the metallization structure includes a second word line of the first memory cell and a word line of the second memory cell.

[0126] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first metallization layer including a plurality of first conductors laterally separated from each other; a plurality of first semiconductor channels disposed above the first metallization layer; a second metallization layer disposed above the first semiconductor channels and including a plurality of second conductors; and a third metallization layer disposed above the second metallization layer and including a plurality of third conductors; wherein at least four of the first conductors, at least six of the first semiconductor channels, at least three of the second conductors, and at least six of the third conductors operatively form memory cells. In some embodiments, the first metallization layer is one of a plurality of first metallization layers vertically spaced apart from each other and vertically spaced from the semiconductor die. In some embodiments, the semiconductor device further includes 6T memory cells and 8T memory cells vertically spaced apart from the 6T memory cells. In some embodiments, the semiconductor device further includes a first via structure electrically connecting a first layer of the first metallization layers to the same layer as a second via structure electrically connecting a second layer of the first metallization layers, and wherein the first via structure and the second via structure are not electrically connected in the same layer.

[0127] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of gate layers, each of the gate layers including a plurality of gates with an interlayer dielectric therebetween laterally; a plurality of drain / source connections electrically connected to a plurality of semiconductor channels, the drain / source connections being electrically coupled to: a plurality of word line structures; and a connection of a first voltage level and a second voltage level of each of a pair of cross-coupled inverters, wherein the gate layers are joined by different threshold voltages.

[0128] As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 includes 0.45 and 0.55, about 10 includes 9 to 11, and about 1000 includes 900 to 1100.

[0129] The foregoing summary describes features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a gate layer disposed in one of a plurality of metallization layers above a semiconductor substrate, wherein the gate layer comprises a plurality of gates; a gate oxide layer disposed above the plurality of gates; as well as a plurality of semiconductor channels separated from the gate layer by the gate oxide layer, wherein the plurality of semiconductor channels include a plurality of transistors of a first memory cell; The plurality of gates and the plurality of semiconductor channels are interconnected to form the first memory unit, and the first memory unit includes a plurality of layers of a metallization structure.

2. The semiconductor device according to claim 1, wherein Also includes: a second gate layer of a second memory cell, the second gate layer being vertically spaced apart from the gate layer of the semiconductor device; and a plurality of second semiconductor channels separated from the second gate layer by a second gate oxide layer, wherein the second gate layer comprises a plurality of second gates; The plurality of second gates and the plurality of second semiconductor channels are interconnected to form the second memory unit, and the second memory unit includes a plurality of second layers of the metallization structure.

3. The semiconductor device according to claim 2, wherein: A first layer of the plurality of layers of the metallization structure includes a word line interconnect, a storage node interconnect, and a complementary storage node interconnect.

4. The semiconductor device according to claim 3, wherein: A second layer of the plurality of layers of the metallization structure includes a first bit line interconnect and a second bit line interconnect.

5. The semiconductor device according to claim 4, wherein: A third layer of the plurality of layers of the metallization structure includes a second word line of the first memory cell and a word line of the second memory cell.

6. A semiconductor device, characterized in that: Include: a first metallization layer comprising a plurality of first conductors laterally separated from each other; A plurality of first semiconductor channels are disposed above the first metallization layer; a second metallization layer disposed above the plurality of first semiconductor channels and comprising a plurality of second conductors; as well as a third metallization layer disposed above the second metallization layer and comprising a plurality of third conductors; At least four of the first conductors, at least six of the first semiconductor channels, at least three of the second conductors, and at least six of the third conductors are operable to form a memory unit.

7. The semiconductor device according to claim 6, wherein: The first metallization layer is one of a plurality of first metallization layers vertically spaced apart from each other and vertically spaced apart from a semiconductor die.

8. The semiconductor device according to claim 6, wherein: Include: A 6T memory unit; and An 8T memory cell is vertically spaced apart from the 6T memory cell.

9. The semiconductor device according to claim 7, wherein: Also includes: a first via structure electrically connecting a first layer of the plurality of first metallization layers to a same layer as a second via structure electrically connecting a second layer of the plurality of first metallization layers; The first through-hole structure and the second through-hole structure are not electrically connected in the same layer.

10. A semiconductor device, characterized in that: Include: A plurality of gate layers, each of the plurality of gate layers comprising a plurality of gates with an interlayer dielectric in the middle laterally; a plurality of drain / source connections electrically connected to the plurality of semiconductor channels, the plurality of drain / source connections electrically coupled to: Multiple word line structures; as well as A connection between a first voltage level and a second voltage level of each of a pair of cross-coupled inverters, wherein the plurality of gate layers are connected by different threshold voltages.

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