Operational amplification circuit and filter

Abstract

The embodiment of the utility model discloses an operational amplifier circuit and a filter. The operational amplifier circuit comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a feed-forward module and a compensation module, the first operational amplifier is used for realizing global input of an input signal and outputting a first intermediate signal; the second operational amplifier is connected between the first operational amplifier and the third operational amplifier and is used for amplifying the first intermediate signal to generate a second intermediate signal and transmitting the second intermediate signal to the third operational amplifier; the feed-forward module is connected between the output end of the first operational amplifier and the output interface and is used for transmitting the first intermediate signal to the output interface at a second speed; the compensation module is connected between the first operational amplifier and the output interface, and the compensation module is used for generating poles, increasing the bandwidth of the operational amplifier circuit and reducing quality factors. According to the technical scheme provided by the embodiment of the utility model, the problems of poor bandwidth and gain of the operational amplifier are solved.

Description

Technical Field

[0001] The embodiments of the present utility model relate to the technical field of automotive electronic chips, and in particular to an operational amplifier circuit and a filter. Background Art

[0002] With the advancement of automotive intelligent technologies, especially in application scenarios such as ADAS (Advanced Driving Assistance System) and UWB (Ultra-WideBand) wireless carrier communication technologies, new requirements for the operation of chips in terms of bandwidth and gain have been put forward. Existing operational amplifier circuits have problems such as difficult compensation or high power consumption, resulting in poor bandwidth and gain of the operational amplifier. Summary of the Utility Model

[0003] The embodiments of the present utility model provide an operational amplifier circuit and a filter to solve the problem of poor bandwidth and gain of existing operational amplifiers.

[0004] To solve the above technical problems, the present utility model adopts the following technical solutions:

[0005] The embodiments of the present utility model provide an operational amplifier circuit, including:

[0006] A first operational amplifier, a second operational amplifier, a third operational amplifier, a feedforward module, and a compensation module; the first operational amplifier is configured to receive an input signal, perform global input of the input signal, and output a first intermediate signal;

[0007] The second operational amplifier is connected between the first operational amplifier and the third operational amplifier; the second operational amplifier is configured to amplify the first intermediate signal to generate a second intermediate signal and transmit the second intermediate signal to the third operational amplifier at a first speed; the third operational amplifier is configured to amplify the second intermediate signal;

[0008] The feedforward module is connected between the output end of the first operational amplifier and the output interface, and the feedforward module is configured to transmit the first intermediate signal to the output interface at a second speed; the second speed is greater than the first speed;

[0009] The compensation module is connected between the first operational amplifier and the output interface, and the compensation module is configured to generate poles, increase the bandwidth of the operational amplifier circuit, and reduce the quality factor.

[0010] Optionally, the compensation module includes a first Miller compensation unit and a second Miller compensation unit connected in parallel. The first Miller compensation unit is used to increase the bandwidth of the operational amplifier circuit; the second Miller compensation unit is used to reduce the quality factor.

[0011] Optionally, the first operational amplifier includes:

[0012] An N-input unit and a P-input unit, where the N-input unit and the P-input unit are connected in parallel;

[0013] A cascode unit, where the input end of the cascode unit is connected to the N-input unit, and the source end of the cascode unit is connected to the first end of the first Miller compensation unit; the output end of the cascode unit serves as the output end of the first operational amplifier and is connected to the first end of the second Miller compensation unit; the second end of the first Miller compensation unit and the second end of the second Miller compensation unit are connected to the output interface;

[0014] A first load unit, which is connected between the P-input unit and the output interface, and the first load unit is used to serve as the load of the P-input unit.

[0015] Optionally, the N-input unit includes:

[0016] A first current source, a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor;

[0017] The first pole of the first switching transistor and the first pole of the second switching transistor are connected to the ground terminal through the first current source;

[0018] The second pole of the first switching transistor is connected to the first pole of the third switching transistor, and the second pole of the second switching transistor is connected to the input end of the cascode unit; the control end of the first switching transistor is connected to the positive input interface, and the control end of the second switching transistor is connected to the negative input interface;

[0019] The second pole of the third switching transistor is connected to the power supply terminal, the control end of the third switching transistor is connected to the first pole of the third switching transistor and the control end of the fourth switching transistor, the first pole of the fourth switching transistor is connected to the first end of the load unit, and the second pole of the fourth switching transistor is connected to the power supply terminal.

[0020] Optionally, the P-input unit includes:

[0021] A second current source, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, and an eighth switching transistor;

[0022] The first pole of the fifth switching tube is connected to the first pole of the sixth switching tube and the first end of the second current source, and the second end of the second current source is connected to the power supply terminal;

[0023] The second pole of the fifth switching tube is connected to the first pole of the seventh switching tube, the control terminal of the fifth switching tube is connected to the positive input interface, the second pole of the sixth switching tube is connected to the first end of the load unit, and the control terminal of the sixth switching tube is connected to the negative input interface;

[0024] The second pole of the seventh switching tube and the second pole of the eighth switching tube are connected to the ground terminal, the control terminal of the seventh switching tube is connected to the first pole of the seventh switching tube and the control terminal of the eighth switching tube, and the first pole of the eighth switching tube is connected to the input terminal of the cascode unit.

[0025] Optionally, the cascode unit includes:

[0026] A ninth switching tube, a tenth switching tube, an eleventh switching tube, and a twelfth switching tube;

[0027] The first pole of the ninth switching tube and the first pole of the tenth switching tube are connected to the power supply terminal, the control terminal of the ninth switching tube and the control terminal of the tenth switching tube are connected to the first end of the eleventh switching tube and the output terminal of the N input unit, the second end of the eleventh switching tube is connected to the second pole of the ninth switching tube, the first pole of the twelfth switching tube is connected to the output terminal of the first operational amplifier, the second pole of the tenth switching tube and the first pole of the twelfth switching tube are connected to the source terminal, and the control terminal of the eleventh switching tube and the control terminal of the twelfth switching tube are connected to the bias voltage input terminal.

[0028] Optionally, the first load unit includes:

[0029] A thirteenth switching tube and a fourteenth switching tube;

[0030] The first poles of the thirteenth switching tube and the fourteenth switching tube are connected to the ground terminal, the second pole of the thirteenth switching tube is connected to the control terminal of the thirteenth switching tube and the control terminal of the fourteenth switching tube, and the second pole of the fourteenth switching tube is connected to the output terminal of the first operational amplifier.

[0031] Optionally, the second operational amplifier includes: a third current source, an amplification unit, and a second load unit;

[0032] The first end of the third current source is connected to the power supply terminal and the first end of the second load unit. The second end of the third current source is connected to the first end of the amplifying unit at a first node. The control end of the amplifying unit is connected to the output end of the first operational amplifier. The second end of the amplifying unit is connected to the second end of the load unit at the ground terminal. The third end of the second load unit is connected to the input end of the third operational amplifier.

[0033] Optionally, the amplifying unit includes:

[0034] A fifteenth switching transistor, the first end of the fifteenth switching transistor is connected to the ground terminal, the second end of the fifteenth switching transistor is connected to the first node, and the control end of the fifteenth switching transistor is connected to the output end of the first operational amplifier;

[0035] The second load unit includes: a sixteenth switching transistor, a seventeenth switching transistor, and an eighteenth switching transistor;

[0036] The first pole of the sixteenth switching transistor, the control end of the sixteenth switching transistor, and the control end of the seventeenth switching transistor are connected to the first node. The second pole of the sixteenth switching transistor and the second pole of the seventeenth switching transistor are connected to the ground terminal. The second end of the seventeenth switching transistor is connected to the first end of the eighteenth switching transistor and the control end of the eighteenth switching transistor, serving as the output end of the second operational amplifier. The second pole of the eighteenth switching transistor is connected to the power supply terminal.

[0037] Optionally, the third operational amplifier includes a nineteenth switching transistor. The first pole of the nineteenth switching transistor is connected to the power supply terminal. The second pole of the nineteenth switching transistor is connected to the output interface. The control end of the nineteenth switching transistor is connected to the output end of the second operational amplifier;

[0038] The first Miller compensation unit includes a first capacitor and the twelfth switching transistor. The first end of the first capacitor is connected to the source terminal. The second end of the first capacitor is connected to the output interface;

[0039] The second Miller compensation unit includes a second capacitor. The first end of the second capacitor is connected to the output end of the first operational amplifier. The second end of the second capacitor is connected to the output interface;

[0040] The feedforward module includes a twentieth switching transistor. The first pole of the twentieth switching transistor is connected to the ground terminal. The second pole of the twentieth switching transistor is connected to the output interface. The control end of the twentieth switching transistor is connected to the output end of the first operational amplifier.

[0041] According to another aspect of the present invention, this embodiment provides a filter, including the operational amplifier circuit proposed in any item of the first aspect.

[0042] In the operational amplifier circuit provided by the embodiment of the present utility model, by arranging the compensation module between the first operational amplifier and the output interface, and arranging the feedforward module between the output end of the first operational amplifier and the output interface, the operational amplifier circuit can quickly respond to the jump of the input signal, generate a dominant pole, increase the frequency of the pole, increase the bandwidth, reduce the quality factor Q, thereby improving the bandwidth and gain of the operational amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for description in the embodiments of the present utility model. Obviously, the following described drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the content of the embodiments of the present utility model and these drawings.

[0044] Figure 1 is a schematic structural diagram of an operational amplifier circuit provided by an embodiment of the present utility model;

[0045] Figure 2 is a schematic structural diagram of another operational amplifier circuit provided by an embodiment of the present utility model;

[0046] Figure 3 is a schematic structural diagram of yet another operational amplifier circuit provided by an embodiment of the present utility model;

[0047] Figure 4 is a schematic structural diagram of yet another operational amplifier circuit provided by an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The following will further elaborate on the present utility model in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present utility model, rather than limiting the present utility model. Additionally, it should be noted that for the sake of convenience of description, only the parts related to the present utility model rather than all the structures are shown in the drawings.

[0049] Based on the above technical problems, the following solutions are proposed in this embodiment:

[0050] Figure 1 is a schematic structural diagram of an operational amplifier circuit provided by an embodiment of the present utility model. Figure 2 is a schematic structural diagram of another operational amplifier circuit provided by an embodiment of the present utility model. Combined with Figure 1 and Figure 2, an embodiment of the present utility model provides an operational amplifier circuit, including: a first operational amplifier 1, a second operational amplifier 2, a third operational amplifier 3, a feedforward module 4, and a compensation module 5; the first operational amplifier 1 is configured to receive an input signal, implement the global input of the input signal, and output a first intermediate signal; the second operational amplifier 2 is connected between the first operational amplifier 1 and the third operational amplifier 3; the second operational amplifier 2 is configured to amplify the first intermediate signal to generate a second intermediate signal and transmit the second intermediate signal to the third operational amplifier 3 at a first speed; the third operational amplifier 3 is configured to amplify the second intermediate signal; the feedforward module 4 is connected between the output end of the first operational amplifier 1 and the output interface, and the feedforward module 4 is configured to transmit the first intermediate signal to the output interface at a second speed; the second speed is greater than the first speed; the compensation module 5 is connected between the first operational amplifier 1 and the output interface, and the compensation module 5 is configured to generate poles, increase the bandwidth of the operational amplifier circuit, and reduce the quality factor Q.

[0051] Specifically, the input interface Vin includes a positive input interface and a negative input interface. The first operational amplifier 1 receives the input signals of the positive input interface and the negative input interface. The first operational amplifier 1 can implement the global reception of the input signals. For example, the input voltage range can include the voltage Vdd from 0V to the power supply terminal vdd. The first operational amplifier 1 performs a first-stage amplification on the input signals and outputs a first intermediate signal after the first-stage amplification.

[0052] The input end of the second operational amplifier 2 is connected to the output end of the first operational amplifier 1. The second operational amplifier 2 performs a second-stage amplification on the first intermediate signal and outputs a second intermediate signal. Since the second operational amplifier 2 makes the impedance of the output second intermediate signal very small, the pole is very large, and the gain is relatively large.

[0053] The third operational amplifier 3 is connected to the output end of the second operational amplifier 2. The third operational amplifier 3 further amplifies the second intermediate signal, thereby improving the transient response of the operational amplifier circuit.

[0054] The feedforward module 4 is connected between the output end of the first operational amplifier 1 and the output interface. The feedforward module 4 transmits the first intermediate signal to the output interface at a second speed faster than the first speed, realizing the fast transmission of the amplified first intermediate signal from the first intermediate signal to the output interface, so that the first intermediate signal can be better synchronized with the output signal of the output interface and improve the response speed of the output interface. Exemplarily, when the input signal has a jump, causing the output of the first operational amplifier 1 to change through the feedforward module 4, the output interface can change quickly, realizing a fast response to the jump of the input signal.

[0055] The compensation module 5 is connected between the first operational amplifier 1 and the output interface. The compensation module 5 can generate poles, increase the bandwidth of the operational amplifier circuit, and reduce the quality factor Q. With such a setting, the operational amplifier circuit generates a dominant pole through the compensation module 5, thereby increasing the frequency of the pole, increasing the bandwidth, and at the same time, the quality factor Q is not too large, thus improving the bandwidth and gain of the operational amplifier circuit.

[0056] For the operational amplifier circuit provided by the embodiment of the present invention, by arranging the compensation module 5 between the first operational amplifier 1 and the output interface, and arranging the feed-forward module 4 between the output terminal of the first operational amplifier 1 and the output interface, the operational amplifier circuit can quickly respond to the jump of the input signal, generate a dominant pole, increase the frequency of the pole, increase the bandwidth, reduce the quality factor Q, thereby improving the bandwidth and gain of the operational amplifier circuit.

[0057] It should be noted that Figure 2 Exemplarily, it is shown that op represents an operational amplifier, simply referred to as an op-amp. Op_compensate represents the operational amplifier of the compensation part. The first operational amplifier 1 includes a first-stage op-amp op1, a first-stage equivalent output resistance R1, and a first-stage equivalent output capacitance C1. The second operational amplifier 2 includes a second-stage op-amp op2, a second-stage equivalent output resistance R2, and a second-stage equivalent output capacitance C2. The third operational amplifier 3 includes a third-stage op-amp op3, a third-stage equivalent output resistance R3, and a third-stage equivalent output capacitance C3. The compensation module 5 includes a first capacitor Ca, a second capacitor Cb, and a compensated op-amp op_compensate.

[0058] Optionally, Figure 3 is a schematic structural diagram of another operational amplifier circuit provided by the embodiment of the present invention. On the basis of the above embodiment, refer to Figure 3 , the compensation module 5 may include a first Miller compensation unit 51 and a second Miller compensation unit 52 connected in parallel. The first Miller compensation unit 51 is used to increase the bandwidth of the operational amplifier circuit; the second Miller compensation unit 52 is used to reduce the quality factor Q.

[0059] The first operational amplifier 1 may include: an N-input unit 11 and a P-input unit 12, and the N-input unit 11 and the P-input unit 12 are connected in parallel; a cascode unit 13, the input terminal of the cascode unit 13 is connected to the N-input unit 11, and the source terminal A of the cascode unit 13 is connected to the first end of the first Miller compensation unit 51; the output terminal of the cascode unit 13 serves as the output terminal Vo_1 of the first operational amplifier 1 st, is connected to the first end of the second Miller compensation unit 52; the second end of the first Miller compensation unit 51 and the second end of the second Miller compensation unit 52 are connected to the output interface; a first load unit 14, the first load unit 14 is connected between the P input unit 12 and the output interface, and the first load unit 14 is used as the load of the P input unit 12.

[0060] Specifically, when the input signal of the positive input interface Vin+ is a positive signal, the N input unit 11 conducts and works, and amplifies the input positive signal, while the P input unit 12 does not work. When the input signal of the negative input interface Vin- is a negative signal, the N input unit 11 does not work, the P input unit 12 conducts and works, and amplifies the input negative signal. The first load unit 14 is connected between the P input unit 12 and the output interface, and the first load unit 14 is used as the load of the P input unit 12. The cascode unit 13 serves as the load of the N input unit 11. The load of the first operational amplifier 1 adopts a cascode structure, resulting in a very large output impedance and a high gain. Therefore, the first operational amplifier 1 is a single-pole, high-gain, and symmetrically structured OTA (analog circuit structure).

[0061] The first Miller compensation unit 51 is connected between the source terminal A of the cascode unit 13 and the output interface. The output terminal of the cascode unit 13 serves as the output terminal Vo_1 of the first operational amplifier 1 st . The first Miller compensation unit 51 is a cascode Miller compensation. The compensation method of the first Miller compensation unit 51 can greatly improve the bandwidth of the operational amplifier.

[0062] By setting the second Miller compensation unit 52 to be connected between the output terminal of the cascode unit 13 and the output interface. The second Miller compensation unit 52 is a direct Miller compensation, which can increase the quality factor Q and make the operational amplifier circuit suitable for wide capacitive loads.

[0063] Optionally, Figure 4 is a schematic structural diagram of another operational amplifier circuit provided by an embodiment of the present invention. On the basis of the above embodiment, refer to Figure 4, the N-input unit 11 may include: a first current source I1, a first switching transistor M1, a second switching transistor M2, a third switching transistor M18a, and a fourth switching transistor M18b; a first pole of the first switching transistor M1 and a first pole of the second switching transistor M2 are connected to a ground terminal GND through the first current source I1; a second pole of the first switching transistor M1 is connected to a first pole of the third switching transistor M18a, and a second pole of the second switching transistor M2 is connected to an input terminal of the cascode unit 13; a control terminal of the first switching transistor M1 is connected to a positive input interface Vin+, and a control terminal of the second switching transistor M2 is connected to a negative input interface Vin-; a second pole of the third switching transistor M18a is connected to a power supply terminal vdd, a control terminal of the third switching transistor M18a is connected to the first pole of the third switching transistor M18a and a control terminal of the fourth switching transistor M18b, a first pole of the fourth switching transistor M18b is connected to a first end of the load unit, and a second pole of the fourth switching transistor M18b is connected to the power supply terminal vdd.

[0064] Specifically, the first switching transistor M1 and the second switching transistor M2 serve as input pair transistors of the N-input unit 11, and the load transistors of the N-input unit 11 are the third switching transistor M18a and the fourth switching transistor M18b. When the input voltage is a relatively high voltage, the N-input unit 11 conducts and operates.

[0065] Optionally, on the basis of the above embodiments, continuing to combine Figure 3 and Figure 4 , the P-input unit 12 may include: a second current source I2, a fifth switching transistor MP1, a sixth switching transistor MP2, a seventh switching transistor M17a, and an eighth switching transistor M17b; a first pole of the fifth switching transistor MP1, a first pole of the sixth switching transistor MP2, and a first end of the second current source I2 are connected, and a second end of the second current source I2 is connected to the power supply terminal vdd; a second pole of the fifth switching transistor MP1 is connected to a first pole of the seventh switching transistor M17a, a control terminal of the fifth switching transistor MP1 is connected to the positive input interface Vin+, a second pole of the sixth switching transistor MP2 is connected to a first end of the load unit, a control terminal of the sixth switching transistor MP2 is connected to the negative input interface Vin-; a second pole of the seventh switching transistor M17a and a second pole of the eighth switching transistor M17b are connected to the ground terminal GND, a control terminal of the seventh switching transistor M17a is connected to the first pole of the seventh switching transistor M17a and a control terminal of the eighth switching transistor M17b, and a first pole of the eighth switching transistor M17b is connected to an input terminal of the cascode unit 13.

[0066] Specifically, the fifth switching transistor MP1 and the sixth switching transistor MP2 serve as the input pair transistors of the P input unit 12. When the input voltage is a low voltage, the P input unit 12 conducts and operates. The P input unit 12 and the N input unit 11 are arranged in parallel, so that the input voltage range of the operational amplifier circuit can be from 0 to vdd. The load transistors of the P input unit 12 are the seventh switching transistor M17a and the eighth switching transistor M17b.

[0067] Optionally, based on the above embodiments, continue to combine Figure 3 and Figure 4 , the cascode unit 13 may include: a ninth switching transistor M13, a tenth switching transistor M14, an eleventh switching transistor M11, and a twelfth switching transistor M12; a first pole of the ninth switching transistor M13 and a first pole of the tenth switching transistor M14 are connected to the power supply terminal vdd, a control terminal of the ninth switching transistor M13 and a control terminal of the tenth switching transistor M14 are connected to a first end of the eleventh switching transistor M11 and an output terminal of the N input unit 11, a second end of the eleventh switching transistor M11 is connected to a second pole of the ninth switching transistor M13, a first pole of the twelfth switching transistor M12 is connected to an output terminal Vo_1 of the first operational amplifier 1 st connected, a second end of the tenth switching transistor M14 and a first pole of the twelfth switching transistor M12 are connected to the source terminal A, and a control terminal of the eleventh switching transistor M11 and a control terminal of the twelfth switching transistor M12 are connected to a bias voltage input terminal Vbp.

[0068] Specifically, the eleventh switching transistor M11, the ninth switching transistor M13, the twelfth switching transistor M12, and the tenth switching transistor M14 adopt a cascode structure, which can increase the output resistance and provide the twelfth switching transistor M12 for cascode miller compensation at the same time. The bias voltage input terminal Vbp is used to input an external bias voltage signal.

[0069] Optionally, based on the above embodiments, continue to combine Figure 3 and Figure 4 , the first load unit 14 includes: a thirteenth switching transistor M15 and a fourteenth switching transistor M16; a first pole of the thirteenth switching transistor M15 and a first pole of the fourteenth switching transistor M16 are connected to the ground terminal GND, a second pole of the thirteenth switching transistor M15 is connected to a control terminal of the thirteenth switching transistor M15 and a control terminal of the fourteenth switching transistor M16, and a second pole of the fourteenth switching transistor M16 is connected to an output terminal Vo_1 of the first operational amplifier 1 st connected.

[0070] Specifically, the current mirror formed by the thirteenth switching transistor M15 and the fourteenth switching transistor M16, the current mirror formed by the eleventh switching transistor M11 and the ninth switching transistor M13, and the current mirror formed by the twelfth switching transistor M12 and the tenth switching transistor M14 together constitute the load terminal of the first operational amplifier 1. The first operational amplifier 1 uses a symmetrically structured OTA, which improves matching and provides better offset and CMRR (Common Mode Rejection Ratio) characteristics.

[0071] For the internal nodes of the first operational amplifier 1, the impedance is on the order of 1 / gm, and the formed pole frequencies are very high. Only the output section out_1st of the first operational amplifier 1 is a high-impedance node, and the pole at this point will affect the loop. The load of the first operational amplifier 1 uses cascode, forming a very large output impedance, resulting in a high gain. Therefore, the first operational amplifier 1 is a single-pole, high-gain OTA.

[0072] Optionally, on the basis of the above embodiments, continue to combine Figure 3 and Figure 4 , the second operational amplifier 2 may include: a third current source I3, an amplification unit 21, and a second load unit 22; the first end of the third current source I3 is connected to the power supply terminal vdd and the first end of the second load unit 22, and the second end of the third current source I3 is connected to the first end of the amplification unit 21 at a first node B. The control end of the amplification unit 21 is connected to the output terminal Vo_1 of the first operational amplifier 1 st connected, and the second end of the amplification unit 21 is connected to the second end of the load unit at the ground terminal GND; the third end of the second load unit 22 is connected to the input terminal of the third operational amplifier 3.

[0073] Specifically, the third current source I3 is used to provide a tail current. The amplification unit 21 is used to amplify the second intermediate signal. The second load unit 22 can be a current mirror load, making the impedance of the first node B small, so that the pole of the first node B is very large. The pole of an operational amplifier refers to that in a circuit, when a voltage signal passes through a node, if this node has both resistance and capacitance, then a pole will be formed. The intuitive effect of a pole is that when the input voltage changes, during the process of the output voltage following the input voltage change, it lags a bit, and this lag generates a phase difference. In the Bode plot, the meaning represented by a pole is the cutoff frequency, that is, the frequency point when the amplitude of the output signal drops to 0.707 times that of the input signal, which is also the -3dB frequency point. A single pole will cause a -20dB / decade roll-off on its amplitude-frequency curve and a -90° phase shift on the corresponding phase-frequency curve.

[0074] Optionally, based on the above embodiments, continue to combine with Figure 3 and Figure 4 , the amplification unit 21 includes: a fifteenth switching transistor M21, a first end of the fifteenth switching transistor M21 is connected to the ground terminal GND, a second end of the fifteenth switching transistor M21 is connected to the first node B, and a control end of the fifteenth switching transistor M21 is connected to the output terminal Vo_1 of the first operational amplifier 1 st connected. The second load unit 22 may include: a sixteenth switching transistor M22, a seventeenth switching transistor M23, and an eighteenth switching transistor M24; a first pole of the sixteenth switching transistor M22, a control end of the sixteenth switching transistor M22, and a control end of the seventeenth switching transistor M23 are connected to the first node B, a second pole of the sixteenth switching transistor M22 and a second pole of the seventeenth switching transistor M23 are connected to the ground terminal GND, a second end of the seventeenth switching transistor M23 is connected to a first end of the eighteenth switching transistor M24 and a control end of the eighteenth switching transistor M24, serving as an output terminal of the second operational amplifier 2, and a second pole of the eighteenth switching transistor M24 is connected to the power supply terminal vdd.

[0075] Specifically, a current mirror load sixteenth switching transistor M22 is adopted, so the impedance of the first node B is small, approximately equal to 1 / gM22, making the pole of the first node B very large. Here, gM22 refers to the transconductance of the sixteenth switching transistor M22. At the same time, the voltage of the first node B relative to the ground is Vgs, which can be directly connected to the subsequent seventeenth switching transistor M23. The gain from the output terminal Vo_1 of the first operational amplifier 1 st to the first node B is gM21 / gM22. The seventeenth switching transistor M23 and the eighteenth switching transistor M24 form a common source circuit, and the sixteenth switching transistor M22 serves as a load and is diode-connected, forming a low-impedance node. The gain from the first node B to the output terminal C of the second operational amplifier 2 is gM23 / gM24.

[0076] Optionally, the third operational amplifier 3 includes a nineteenth switching transistor M3, a first pole of the nineteenth switching transistor M3 is connected to the power supply terminal vdd, a second pole of the nineteenth switching transistor M3 is connected to the output interface Vout, and a control end of the nineteenth switching transistor M3 is connected to the output terminal C of the second operational amplifier 2.

[0077] The first Miller compensation unit 51 includes a first capacitor Ca and the twelfth switching transistor M12, a first end of the first capacitor Ca is connected to the source terminal A, and a second end of the first capacitor Ca is connected to the output interface Vout; the second Miller compensation unit 52 includes a second capacitor Cb, a first end of the second capacitor Cb is connected to the output terminal Vo_1 of the first operational amplifier 1st is connected, the second terminal of the second capacitor Cb is connected to the output interface Vout; the feedforward module 4 includes a twentieth switching transistor M4, the first pole of the twentieth switching transistor M4 is connected to the ground terminal GND, the second pole of the twentieth switching transistor M4 is connected to the output interface Vout, and the control terminal of the twentieth switching transistor M4 is connected to the output terminal Vo_1 of the first operational amplifier 1 st is connected.

[0078] Specifically, the third operational amplifier 3 is composed of a nineteenth switching transistor M3 in a common-source configuration. The feedforward module 4 includes a twentieth switching transistor M4. The nineteenth switching transistor M3 and the twentieth switching transistor M4 can improve the transient response of the circuit.

[0079] The compensation module 5 is used to generate poles for the operational amplifier circuit. The first Miller compensation unit 51 includes a first capacitor Ca and a twelfth switching transistor M12. The compensation module 5 shares the twelfth switching transistor M12 with the first operational amplifier 1. The second capacitor Cb is directly connected from the output of the first operational amplifier 1 to the output interface Vout to form a direct Miller compensation. The first capacitor Ca and the twelfth switching transistor M12 form a cascode compensation network. The twelfth switching transistor M12 is a voltage buffer. This compensation method can greatly improve the bandwidth of the operational amplifier. By setting the second capacitor Cb, the quality factor Q can be reduced.

[0080] This embodiment provides a filter, including the operational amplifier circuit proposed in any of the above embodiments. It has the beneficial effects of the operational amplifier circuit proposed in any of the above embodiments, which will not be elaborated here.

[0081] Note that the above is only the preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An operational amplifier circuit, characterized in that: include: A first operational amplifier, a second operational amplifier, a third operational amplifier, a feedforward module and a compensation module; the first operational amplifier is used to realize the full-domain input of the input signal and output a first intermediate signal; The second operational amplifier is connected between the first operational amplifier and the third operational amplifier; the second operational amplifier is used to amplify the first intermediate signal to generate a second intermediate signal, and transmit the second intermediate signal to the third operational amplifier at a first speed; the third operational amplifier is used to amplify the second intermediate signal; The feedforward module is connected between the output terminal of the first operational amplifier and the output interface, and is used to transmit the first intermediate signal to the output interface at a second speed; the second speed is greater than the first speed; The compensation module is connected between the first operational amplifier and the output interface, and is used to generate a pole, increase the bandwidth of the operational amplifier circuit, and reduce the quality factor.

2. The operational amplifier circuit according to claim 1, characterized in that: The compensation module comprises a first Miller compensation unit and a second Miller compensation unit connected in parallel, wherein the first Miller compensation unit is used to increase the bandwidth of the operational amplifier circuit; The second Miller compensation unit is used to reduce the quality factor; The first operational amplifier comprises: An N input unit and a P input unit, wherein the N input unit and the P input unit are connected in parallel; A cascode unit, wherein the input end of the cascode unit is connected to the N input unit, and the source end of the cascode unit is connected to the first end of the first Miller compensation unit; the output end of the cascode unit is used as the output end of the first operational amplifier and is connected to the first end of the second Miller compensation unit; the second end of the first Miller compensation unit and the second end of the second Miller compensation unit are connected to the output interface; A first load unit, wherein the first load unit is connected between the P input unit and the output interface, and the first load unit is used as a load of the P input unit.

3. The operational amplifier circuit according to claim 2, characterized in that: The N input unit comprises: A first current source, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; The first electrode of the first switch tube and the first electrode of the second switch tube are connected to the ground terminal through the first current source; The second electrode of the first switch tube is connected to the first electrode of the third switch tube, and the second electrode of the second switch tube is connected to the input end of the common source and common gate unit; the control end of the first switch tube is connected to the positive input interface, and the control end of the second switch tube is connected to the negative input interface; The second pole of the third switch tube is connected to the power supply end, the control end of the third switch tube is connected to the first pole of the third switch tube and the control end of the fourth switch tube, the first pole of the fourth switch tube is connected to the first end of the load unit, and the second pole of the fourth switch tube is connected to the power supply end.

4. The operational amplifier circuit according to claim 3, characterized in that: The P input unit comprises: a second current source, a fifth switch tube, a sixth switch tube, a seventh switch tube and an eighth switch tube; The first electrode of the fifth switch tube is connected to the first electrode of the sixth switch tube and the first end of the second current source, and the second end of the second current source is connected to the power supply end; The second electrode of the fifth switch tube is connected to the first electrode of the seventh switch tube, the control end of the fifth switch tube is connected to the positive input interface, the second electrode of the sixth switch tube is connected to the first end of the load unit, and the control end of the sixth switch tube is connected to the negative input interface; The second electrode of the seventh switch tube and the second electrode of the eighth switch tube are connected to the ground end, the control end of the seventh switch tube is connected to the first electrode of the seventh switch tube and the control end of the eighth switch tube, and the first electrode of the eighth switch tube is connected to the input end of the common source and common gate unit.

5. The operational amplifier circuit according to claim 4, characterized in that: The cascode unit comprises: a ninth switch tube, a tenth switch tube, an eleventh switch tube and a twelfth switch tube; The first electrode of the ninth switch tube and the first electrode of the tenth switch tube are connected to the power supply end, the control end of the ninth switch tube and the control end of the tenth switch tube are connected to the first end of the eleventh switch tube and the output end of the N input unit, the second end of the eleventh switch tube is connected to the second electrode of the ninth switch tube, the first electrode of the twelfth switch tube is connected to the output end of the first operational amplifier, the second end of the tenth switch tube and the first electrode of the twelfth switch tube are connected to the source end, and the control end of the eleventh switch tube and the control end of the twelfth switch tube are connected to the bias voltage input end.

6. The operational amplifier circuit according to claim 4, characterized in that: The first load unit comprises: A thirteenth switch tube and a fourteenth switch tube; the first electrode of the thirteenth switch tube and the first electrode of the fourteenth switch tube are connected to the ground end, the second electrode of the thirteenth switch tube is connected to the control end of the thirteenth switch tube and the control end of the fourteenth switch tube, and the second electrode of the fourteenth switch tube is connected to the output end of the first operational amplifier.

7. The operational amplifier circuit according to claim 4, characterized in that: The second operational amplifier comprises: a third current source, an amplifying unit and a second load unit; The first end of the third current source is connected to the power supply end and the first end of the second load unit, the second end of the third current source and the first end of the amplifying unit are connected to a first node B, the control end of the amplifying unit is connected to the output end of the first operational amplifier, the second end of the amplifying unit and the second end of the load unit are connected to the ground end; the third end of the second load unit is connected to the input end of the third operational amplifier.

8. The operational amplifier circuit according to claim 7, characterized in that: The amplification unit comprises: a fifteenth switch tube, wherein a first end of the fifteenth switch tube is connected to the ground end, a second end of the fifteenth switch tube is connected to the first node, and a control end of the fifteenth switch tube is connected to the output end of the first operational amplifier; The second load unit includes: a sixteenth switch tube, a seventeenth switch tube and an eighteenth switch tube; The first electrode of the sixteenth switch tube, the control end of the sixteenth switch tube and the control end of the seventeenth switch tube are connected to the first node, the second electrode of the sixteenth switch tube and the second electrode of the seventeenth switch tube are connected to the ground end, the second end of the seventeenth switch tube is connected to the first end of the eighteenth switch tube and the control end of the eighteenth switch tube as the output end of the second operational amplifier, and the second electrode of the eighteenth switch tube is connected to the power supply end.

9. The operational amplifier circuit according to claim 5, characterized in that: The third operational amplifier comprises a nineteenth switch tube, a first electrode of the nineteenth switch tube is connected to the power supply end, a second electrode of the nineteenth switch tube is connected to the output interface, and a control end of the nineteenth switch tube is connected to the output end of the second operational amplifier; The first Miller compensation unit includes a first capacitor and the twelfth switch tube, the first end of the first capacitor is connected to the source terminal, and the second end of the first capacitor is connected to the output interface; The second Miller compensation unit comprises a second capacitor, a first end of the second capacitor is connected to the output end of the first operational amplifier, and a second end of the second capacitor is connected to the output interface; The feedforward module includes a twentieth switch tube, a first electrode of the twentieth switch tube is connected to the ground end, a second electrode of the twentieth switch tube is connected to the output interface, and a control end of the twentieth switch tube is connected to the output end of the first operational amplifier.

10. A filter, characterized in that: The operational amplifier circuit comprises the operational amplifier circuit described in any one of claims 1 to 9.

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