Composite cascode power amplifier for envelope tracking application

Abstract

To provide a composite cascode power amplifier for an envelope tracking application.SOLUTION: In an envelope tracking system, a composite cascode power amplifier 250 that amplifies a radio frequency (RF) signal includes a composite cascode power amplifier that receives power from a power amplifier supply voltage VPA and an envelope tracker that generates a power amplifier supply voltage based on an envelope of a RF signal RFIN. The composite cascode power amplifier includes an enhancement-mode (E-mode) field-effect transistor (FET) 241 for amplifying the RF signal, and a depletion-mode (D-mode) FET242 to be cascoded to the E-mode FET.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to an electronic system, and more particularly to a power amplifier for use in a radio frequency (RF) electronic device.

Background Art

[0002] A power amplifier is used to amplify an RF signal for transmission via an antenna in a radio frequency (RF) communication system. It is important to manage the power of RF signal transmission to extend battery life and / or provide an appropriate transmission power level.

[0003] Examples of RF communication systems having one or more power amplifiers include, but are not limited to, cellular phones, tablets, base stations, network access points, customer premise equipment (CPE), laptops, and wearable electronic devices. For example, in a wireless device that communicates using a cellular standard, a wireless local area network (WLAN) standard, and / or any other suitable communication standard, a power amplifier can be used for RF signal amplification. The RF signal can have a frequency in the range of about 30 kHz to about 300 GHz, such as, for example, in the range of about 410 MHz to about 7.125 GHz for 5G cellular communication in frequency range 1 (FR1), or in the range of about 24.250 GHz to about 52.600 GHz for frequency range 2 (FR2) of the 5G communication standard.

Summary of the Invention

[0004] In certain embodiments, the present disclosure includes a transceiver configured to generate a radio frequency signal, and a power amplifier supply voltage that varies in relation to the envelope of the radio frequency signal. ​​​​​​​​​​​​A power management system including an envelope tracker configured to, and a front-end system including a combined cascode power amplifier configured to receive a radio frequency signal and receive power from the power amplifier supply voltage. The combined cascode power amplifier includes an enhancement-mode field effect transistor configured to receive a radio frequency signal and a depletion-mode field effect transistor cascode-connected to the enhancement-mode field effect transistor. In various embodiments, the enhancement-mode field effect transistor is a metal oxide semiconductor transistor. In certain embodiments, the enhancement-mode field effect transistor is a short-channel n-type metal oxide semiconductor transistor. In some embodiments, the depletion-mode field effect transistor is a Schottky gate field effect transistor. In some embodiments, the source of the enhancement-mode field effect transistor is connected to a ground voltage portion, and the drain of the enhancement-mode field effect transistor is connected to the output terminal of the combined cascode power amplifier through the depletion-mode field effect transistor. According to certain embodiments, the gate of the depletion-mode transistor is biased by a ground voltage. According to some embodiments, the gate of the depletion-mode transistor is biased by a positive voltage exceeding the ground voltage.

[0005]

[0006]

[0007]

[0008]

[0009] In various embodiments, the composite cascode power amplifier further includes a choke inductor that is electrically connected between the power amplifier supply voltage section and the drain of the depletion mode field effect transistor.

[0010] In some embodiments, the composite cascode power amplifier further includes a gate bias inductor configured to apply a gate bias voltage to the gate of the enhancement mode field effect transistor.

[0011] In some embodiments, the envelope tracker includes a DC / DC converter configured to output a plurality of regulated voltages, and a modulator configured to generate a modulator output voltage at an output based on the plurality of regulated voltages and an envelope of a radio frequency signal, and a modulator output filter coupled between an output of the modulator and the power amplifier supply voltage section.

[0012] In various embodiments, the envelope tracker includes a DC / DC converter and an error amplifier configured to operate in parallel with each other to generate a power amplifier supply voltage.

[0013] In a given embodiment, the present disclosure relates to an envelope tracking system. The envelope tracking system includes an envelope tracker configured to generate a power amplifier supply voltage that varies in relation to an envelope of a radio frequency signal, and a composite cascode power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage. The composite cascode power amplifier includes an enhancement mode field effect transistor configured to receive the radio frequency signal. ​​​​​​​​a fruit transistor and a depletion mode field effect transistor cascode-connected to the enhancement mode field effect transistor are included.

[0014] In various embodiments, the enhancement mode field effect transistor is a metal oxide semiconductor transistor.

[0015] In some embodiments, the enhancement mode field effect transistor is a short channel n-type metal oxide semiconductor transistor.

[0016] In some embodiments, the depletion mode field effect transistor is a Schottky gate field effect transistor.

[0017] In various embodiments, the source of the enhancement mode field effect transistor is connected to a ground voltage section, and the drain of the enhancement mode field effect transistor is connected to the output terminal of a composite cascode power amplifier via the depletion mode field effect transistor. According to a certain number of embodiments, the gate of the depletion mode transistor is biased by a ground voltage. According to some embodiments, the gate of the depletion mode transistor is biased by a positive voltage exceeding the ground voltage. is applied.

[0018] In some embodiments, the composite cascode power amplifier further includes a choke inductor electrically connected between a power amplifier supply voltage section and the drain of the depletion mode field effect transistor. is included.

[0019] ​In some embodiments, the combined cascode power amplifier further comprises an enhancement gate bias inductor configured to apply a gate bias voltage to the gate of the enhancement mode field effect transistor.

[0020] In various embodiments, the envelope tracker comprises a DC / DC converter configured to output a plurality of regulated voltages, a modulator configured to generate a modulator output voltage at an output based on the plurality of regulated voltages and an envelope of a radio frequency signal, and a modulator output filter coupled between an output of the modulator and a power amplifier supply voltage section.

[0021] In some embodiments, the envelope tracker comprises a DC / DC converter and an error amplifier configured to operate in parallel with each other to generate a power amplifier supply voltage.

[0022] In a given embodiment, the present disclosure relates to a method for radio frequency signal amplification in a portable device. The method comprises generating, using an envelope tracker, a power amplifier supply voltage that varies in relation to an envelope of a radio frequency signal, applying the power amplifier supply voltage to a combined cascode power amplifier that comprises an enhancement mode field effect transistor and a depletion mode field effect transistor cascode to the enhancement mode field effect transistor, and amplifying the radio frequency signal using the combined cascode power amplifier.

[0023] In various embodiments, the enhancement mode field effect transistor is a metal oxide semiconductor transistor. ​​​​​​​​​​​​

[0024] In some embodiments, the enhancement-mode field-effect transistor is a short-channel n-type metal-oxide-semiconductor transistor.

[0025] In some embodiments, the depletion-mode field-effect transistor is a Schottky-gate field-effect transistor.

[0026] In some embodiments, the source of the enhancement-mode field-effect transistor is connected to a ground voltage portion, and the drain of the enhancement-mode field-effect transistor is connected to the output terminal of the composite cascode power amplifier through a depletion-mode field-effect transistor. According to some embodiments, the gate of the depletion-mode transistor is biased by a ground voltage. According to some embodiments, the gate of the depletion-mode transistor is biased by a positive voltage that is higher than the ground voltage.

[0027] In various embodiments, the method further includes applying a power amplifier supply voltage to the drain of the depletion-mode field-effect transistor using a choke inductor.

[0028] In some embodiments, the method further includes applying a gate bias voltage to the gate of the enhancement-mode field-effect transistor using a gate bias inductor.

[0029] In some embodiments, generating the power amplifier supply voltage includes outputting a plurality of regulated voltages from a DC / DC converter and using a modulator to modulate the plurality of regulated voltages. ​ generating a modulator output voltage based on the pressure and the envelope of the radio frequency signal, and the modulator ou using a power filter to filter the modulator output voltage to generate a power amplifier supply voltage. This includes.

[0030] In various embodiments, generating the power amplifier supply voltage includes tracking the envelope using a parallel operating D C / DC converter and an error amplifier.

Brief Description of the Drawings

[0031]

Figure 1

Figure 2

Figure 3

Figures 4A-4D

Figures 5A-5C

Figure 6

Figures 7A-7B

Figures 8A-8B

Figure 9A

Figure 9B

Figure 10

Figures 11A-11B

Figure 12

[0032] The following detailed description of certain embodiments represents various descriptions of specific embodiments. However, the innovations described herein are defined and covered, for example, by the claims. In this description, the same reference numerals refer to the same Reference is made to the drawings which may show identical or functionally similar elements. It is understood that the drawings It is to be further understood that elements depicted in the drawings are not necessarily to scale. The embodiments may include more elements than are shown in the drawings and / or may include more elements than are shown in the drawings. Additionally, some embodiments may include a subset of features from two or more of the drawings. Any suitable combination may be incorporated.

[0033] Figure 1 is a schematic diagram of an example of a mobile device 100. The mobile device 100 is based on a baseband system 1, a transceiver 2, a front-end system 3, an antenna 4, a power management system 5, a memory 6, a user interface 7, and a battery 8.

[0034] The mobile device 100 can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax ), and / or GPS technology. ) and / or GPS technology. It can be used to communicate using a variety of communication technologies including, but not limited to, 2G, 3G, 4G (including LTE, LTE Advanced, and LTE Advanced Pro), 5G, WLAN (e.g., Wi-Fi), WPAN (e.g., Bluetooth (registered trademark) and ZigBee (registered trademark)), WMAN (e.g., WiMax

[0035] The transceiver 2 generates RF signals for transmission and processes incoming RF signals received from the antenna 4. As will be understood, the various functions associated with the transmission and reception of RF signals can be achieved by one or more components collectively represented as the transceiver 2 in FIG. 1. In one example, separate components can be provided (e.g., separate circuits or dies) to handle a given type of RF signal. can be achieved by one or more components collectively represented as the transceiver 2 in FIG. 1. In one example, separate components can be provided (e.g., separate circuits or dies) to handle a given type of RF signal. For example, separate components (e.g., separate circuits or dies) can be provided to handle a given type of RF signal.

[0036] The front-end system 3 assists in conditioning signals transmitted to and / or received from the antenna 4. In the illustrated embodiment, the front-end system 3 includes a power amplifier (PA) 11, a low-noise amplifier (LNA) 12, a filter 13, a switch 14, and a duplexer 15. However, other implementations are possible. In the illustrated embodiment, the front-end system 3 includes a power amplifier (PA) 11, a low-noise amplifier (LNA) 12, a filter 13, a switch 14, and a duplexer 15. However, other implementations are possible. For example, the front-end system 3 can include signal amplification for transmission, amplification of received signals, signal filtering, and other functions.

[0037] filtering, and other functions for transmission and reception. Filtering, switching between different bands, switching between different power modes, switching between transmission mode and reception mode, signal duplexing, signal multip lexing (e.g., diplexing or triplexing), or any combination thereof, can provide a certain number of functions including but not limited to these.

[0038] In a given implementation example, the mobile device 100 supports carrier aggregation so that flexibility to increase the peak data rate is obtained. Carrier aggregation can be used for both frequency division duplexing (FDD) and time division duplexing (TDD), and can be used to aggregate multiple carriers or channels. Carrier aggregation includes adjacent aggregation in which adjacent carriers within the same operating frequency band are aggregated. Carrier aggregation may also be discontinuous and may include carriers with separated frequencies within a common band and / or in different

[0039] Antenna 4 may include antennas used for a variety of types of communication. For example, antenna 4 may include antennas related to transmitting and / or receiving signals associated with a variety of frequencies and communication standards.

[0040] In a given implementation example, antenna 4 supports MIMO communication and / or switch diversity communication. For example, MIMO communication uses multiple antennas to communicate multiple data streams via a single radio frequency channel. MIMO communication provides high signal-to-noise ratio, improved coding, and / or Benefit from reduced signal interference due to differences. Switch diversity refers to communication where a specific antenna is selected to operate at a specific time. For example, a group of antennas can be selected based on various factors such as the observed bit error rate and / or signal strength indicator using a switch.

[0041] Mobile device 100 can operate with beamforming in a given implementation example. For example, front-end system 3 can include a phase shifter whose variable phase is controlled by transceiver 2. Additionally, the phase shifter is controlled to provide beamforming and directivity for signal transmission and / or reception using antenna 4. For example, in the context of signal transmission, the phase of the transmission signal applied to antenna 4 is such that the signals radiated from antenna 4 are combined using constructive and destructive interference to generate an aggregated transmission signal that exhibits a beam-like quality of signal strength propagating in a given direction. In the context of signal reception, the phase is controlled so that more signal energy is received when the signal arrives at antenna 4 from a specific direction. In a given implementation example, antenna 4 includes one or more arrays of multiple antenna elements to improve beamforming.

[0042] Baseband system 1 is coupled to user interface 7 to facilitate the processing of various user inputs and outputs (I / O ) such as voice and data. Baseband system 1 provides a digital representation of the transmission signal to be processed to transceiver 2 for generating an RF signal for transmission. Baseband system 1 also receives the received​​​​​​ Process the digital representation of the signal. As shown in FIG. 1, the baseband system 1 is coupled to the memory 6 to facilitate the operation of the mobile device 100. It is coupled to the memory 6 to facilitate the operation of the mobile device 100.

[0043] The memory 6 can be used for a variety of purposes, such as storing data and / or instructions to facilitate the operation of the mobile device 100 and / or to provide storage for user information. It can be used for a variety of purposes, such as storing data and / or instructions to facilitate the operation of the mobile device 100 and / or to provide storage for user information. It can be used for a variety of purposes.

[0044] The power management system 5 provides a certain number of power management functions for the mobile device 100. The power management system 5 in FIG. 1 includes an envelope tracker 60. As shown in FIG. 1, the power management system 5 receives the battery voltage from the battery 8. The battery 8 can be any suitable battery used in the mobile device 100, including, for example, a lithium-ion battery. The power management system 5 in FIG. 1 includes an envelope tracker 60. As shown in FIG. 1, the power management system 5 receives the battery voltage from the battery 8. The battery 8 can be any suitable battery used in the mobile device 100, including, for example, a lithium-ion battery. The power management system 5 receives the battery voltage from the battery 8. The battery 8 can be any suitable battery used in the mobile device 100, including, for example, a lithium-ion battery. The battery 8 can be any suitable battery used in the mobile device 100, including, for example, a lithium-ion battery.

[0045] The mobile device 100 in FIG. 1 shows an example of an RF communication system that may include a power amplifier implemented according to one or more features of the present disclosure. However, the teachings herein are applicable to RF communication systems implemented in a variety of forms. The mobile device 100 in FIG. 1 shows an example of an RF communication system that may include a power amplifier implemented according to one or more features of the present disclosure. However, the teachings herein are applicable to RF communication systems implemented in a variety of forms. The teachings herein are applicable to RF communication systems implemented in a variety of forms.

[0046] FIG. 2 is a schematic diagram of an embodiment of a transmission system 130 for transmitting an RF signal from a mobile device. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing and switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital predistortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital calculation (CORDIC) circuit 122. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing and switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital predistortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital calculation (CORDIC) circuit 122. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing and switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital predistortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital calculation (CORDIC) circuit 122. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing and switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital predistortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital calculation (CORDIC) circuit 122. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing and switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital predistortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital calculation (CORDIC) circuit 122. The transmission system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, a directional coupler 104, a diplexing and switching circuit 105, an antenna 106, a baseband processor 107, a signal delay circuit 108, a digital predistortion (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, an intermodulation detection circuit 112, an envelope delay circuit 121, a coordinate rotation digital calculation (CORDIC) circuit 122. It includes a shaping circuit 123, a digital / analog converter 124, and a reconstruction filter 125.

[0047] The transmission system 130 in FIG. 2 includes a power amplifier implemented according to one or more features of the present disclosure and shows an example of an RF communication system that can be obtained. However, the teachings herein are applicable to RF communication systems implemented in a variety of manners and are applicable to RF communication systems implemented in a variety of manners.

[0048] The baseband processor 107 operates to generate an I signal and a Q signal corresponding to the signal components of a sine wave or signal with a desired amplitude, frequency, and phase. For example, the I signal is used to represent the in-phase component of the sine wave, and the Q signal is used to represent the quadrature phase component of the sine wave and can be used to represent the in-phase component of the sine wave, and the Q signal can be used to represent the quadrature phase component of the sine wave. These can be an equivalent representation of the sine wave. In a given implementation example, the I signal and the Q signal are provided to the I / Q modulator 110 in digital format. The baseband processor 107 can be any suitable processor configured to process baseband signals and can be any suitable processor configured to process baseband signals. For example, the baseband processor 107 may include a digital signal processor, a micro processor, a programmable core, or any combination thereof.

[0049] The signal delay circuit 108 provides an adjustable delay to the I signal and the Q signal for the purpose of assisting in controlling the relative alignment between the envelope signal and the RF signal RF IN and the RF signal RF. The amount of delay provided by the signal delay circuit 108 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112 IN and the RF signal RF. The amount of delay provided by the signal delay circuit 108 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112 and the RF signal RF. The amount of delay provided by the signal delay circuit 108 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112 and the RF signal RF. The amount of delay provided by the signal delay circuit 108 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112 and is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112.

[0050] The DPD circuit 109 operates to digitally shape the delayed I signal and Q signal from the signal delay circuit 108 to generate a digitally pre-distorted I signal and Q signal and operates to digitally shape the delayed I signal and Q signal from the signal delay circuit 108 to generate a digitally pre-distorted I signal and Q signal It is done. In the illustrated embodiment, the DPD provided by the DPD circuit 109 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112. The DPD circuit 109 serves to reduce the distortion of the power amplifier 1 03 and / or increase the efficiency of the power amplifier 103.

[0051] The I / Q modulator 110 receives the digitally pre-distorted I and Q signals and these signals are processed to generate the RF signal RF IN . For example, the I / Q modulator 110 may include a DAC configured to convert the I and Q signals to an analog format , a mixer that up-converts the I and Q signals to a radio frequency, and a signal combiner that combines the up-converted I and Q signals into an RF signal suitable for amplification by the power amplifier 103. In a given implementation example, the I / Q modulator 110 may include one or more filters configured to filter the frequency content of the signals being processed . The envelope delay circuit 121 delays the I and Q signals from the baseband processor 107. Additionally, the CORDIC circuit 122 processes the delayed I and Q signals to generate a digital envelope signal representing the envelope of the RF signal RF . Although FIG. 2 shows an implementation example using the CORDIC circuit 122, the envelope signal can also be obtained in other ways.

[0052] The shaping circuit 123 operates to shape the digital envelope signal to enhance the performance of the transmission system 130. In a given implementation example, the shaping circuit 123 adjusts each level of the digital envelope signal of the digital envelope signal. IN Figure 2 shows an implementation example using the CORDIC circuit 122, but the envelope signal can be obtained in other ways. It can also be obtained.

[0053] The shaping circuit 123 operates to shape the digital envelope signal to enhance the performance of the transmission system 130. In a given implementation example, the shaping circuit 123 operates to shape the digital envelope signal to enhance the performance of the transmission system 130. In a given implementation example, the shaping circuit 123 adjusts each level of the digital envelope signal ​It includes a shaping table that maps the bell to the corresponding shaped envelope signal level. Envelope By shaping the line, it is possible to assist in controlling the linearity, distortion, and / or efficiency of the power amplifier 103 .

[0054] In the illustrated embodiment, the shaped envelope signal is a digital signal that is converted into an analog envelope signal by the DAC 124. Additionally, the analog envelope signal is filtered by the reconstruction filter 125 to generate an envelope signal suitable for use by the envelope tracker 102. In a given implementation example, the reconstruction filter 125 includes a low-pass filter .

[0055] Continuing to refer to FIG. 2, the envelope tracker 102 receives the envelope signal from the reconstruction filter 125 and also receives the battery voltage V from the battery 101, and uses the envelope signal to generate a power amplifier supply voltage V BATT for the power amplifier 103 that varies in relation to the envelope of the RF signal RF . The power amplifier 103 receives the RF signal RF IN from the I / Q modulator 110 and, in this example, supplies the amplified RF signal RF to the antenna 106 via the diplexing switching circuit 105 PA . IN OUT .

[0056] The directional coupler 104 is disposed between the output of the power amplifier 103 and the input of the diplexing switching circuit 105. This allows the output power of the power amplifier 103 without including the insertion loss of the diplexing switching circuit 105 to be measured. The detected output signal from the directional coupler 104 is provided to the observation receiver 111. Observation ​​​​​​The reception detector 111 includes a mixer that down-converts the detected I-signal component and Q-signal component of the output signal, and a DAC that generates an I observation signal and a Q observation signal from the down-converted signal. The intermodulation detection circuit 112 determines the intermodulation product between the I observation signal and Q observation signal and the I-signal and Q-signal from the baseband processor 107. Additionally, the intermodulation detection circuit 112 controls the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108 to control the relative alignment between the envelope signal and the RF signal RF

[0057] The intermodulation detection circuit 112 determines the intermodulation product between the I observation signal and Q observation signal and the I-signal and Q-signal from the baseband processor 107. Additionally, the intermodulation detection circuit 112 controls the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108 to control the relative alignment between the envelope signal and the RF signal RF controls the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108 to control the relative alignment between the envelope signal and the RF signal RF controls the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108 to control the relative alignment between the envelope signal and the RF signal RF IN and the RF signal RF. .

[0058] By including the output section of the power amplifier 103 and the feedback path from the baseband, the I-signal and Q-signal can be dynamically adjusted to optimize the operation of the transmission system 130. For example, by configuring the transmission system 130 in this manner, power control can be provided, transmitter faults can be compensated for, and / or DPD can be assisted. By including the output section of the power amplifier 103 and the feedback path from the baseband, the I-signal and Q-signal can be dynamically adjusted to optimize the operation of the transmission system 130. For example, by configuring the transmission system 130 in this manner, power control can be provided, transmitter faults can be compensated for, and / or DPD can be assisted.

[0059] Although the power amplifier 103 is shown as a single stage, it may include one or more stages. Further, an RF communication system such as a mobile device may include a number of power amplifiers. In such an implementation, separate envelope trackers can be provided for different power amplifiers, and / or one or more shared envelope trackers can be used. one or more shared envelope trackers can be used. and / or one or more shared envelope trackers can be used.

[0060] Composite cascode power amplifier for envelope tracking applications

[0061] Envelope tracking is related to the envelope of the RF signal amplified by the power amplifier to supply power to the power amplifier. A technique that can be used to increase the power added efficiency (PAE ) of a power amplifier by efficiently controlling the voltage level of the supply voltage. That is, when the envelope of the RF signal rises , the voltage supplied to the power amplifier can also rise. Similarly, when the envelope of the RF signal falls , the voltage supplied to the power amplifier also falls and power consumption decreases.

[0062] In one example, the envelope tracker includes a DC / DC converter that operates in combination with an error amplifier to generate a power amplifier supply voltage based on the envelope signal. For example, the DC / D C converter and the error amplifier can be electrically connected in parallel with each other, and while the DC / DC converter can track the low-frequency components of the envelope signal, the error amplifier can track the high-frequency components of the envelope signal. For example, the switching frequency of the DC / DC converter can be reduced to be lower than the maximum frequency component of the envelope signal, and the error amplifier can operate to smooth the gap at the output of the converter to generate a power amplifier supply voltage. In a given implementation example, the DC / DC converter and the error amplifier can be coupled via a coupler. In another example, the envelope tracker includes a multi-output boost switch that generates regulated voltages of different voltage levels, a bank of multiple switches that controls the selection of an appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switch bank to generate a power amplifier supply voltage.

[0063] A composite cascode power amplifier for envelope tracking applications is provided herein.

[0064] ​​​​In a given embodiment, an envelope tracking system includes a combined cascode power amplifier that amplifies an RF signal, the combined cascode power amplifier receiving power from a power amplifier supply voltage section, and an envelope tracker that generates a power amplifier supply voltage based on an envelope of the RF signal. The combined cascode power amplifier includes an enhancement mode (E-mode) field effect transistor (FET) that amplifies the RF signal and a depletion mode (D-mode) FET cascode coupled to the E-mode FET. Implementing the power amplifier in this manner realizes the benefits obtained by the E-mode and D-mode transistors while avoiding the negative aspects of these transistor types. For example, E-mode FETs have many desirable characteristics such as a high transition frequency (f ), the ability to be biased by an easily available positive voltage, and / or a low phase distortion (AM / PM) resulting from a high linearity gate capacitance and negligible gate current.

[0065] However, E-mode FETs also suffer from insufficient breakdown voltage, channel length modulation, drain-induced barrier lowering, and / or other transistor non-idealities. In contrast, D-mode FETs typically have a high breakdown voltage but suffer from a negative voltage bias for operation, a very high negative voltage bias for standby operation, and / or poor phase distortion due to non-linear gate current.

[0066] In a given implementation example, the E-mode FET is implemented as a short-channel metal oxide semiconductor (MOS) transistor, while the D-mode FET is here a Schottky gate FET t

[0067] ​ implemented as a metal semiconductor FET (MESFET), also referred to as a Schottky gate D mode FET typically has a higher breakdown voltage than an E-mode MOS transistor, so a composite cascode power amplifier operates at a higher breakdown voltage compared to a common source E-mode MOS power amplifier. The high breakdown voltage allows the composite cascode power amplifier to be used in envelope tracking applications where the power amplifier supply voltage operates over a wide voltage range is acceptable. Further, the composite cascode power amplifier also exhibits high f , high linearity, low t , low phase distortion, low quiescent current, and / or low gain variation with respect to the power amplifier supply voltage . Further, the composite cascode power amplifier does not need to be operated by a negative voltage bias, which increases static and dynamic power consumption and generates spurious emissions and can typically avoid the need for a negative charge pump that includes an oscillator.

[0068] The D-mode FET can be biased in various manners. In a first example, the gate of the D mode FET is biased using ground. In another example, the gate of the D mode FET is biased using a positive common gate voltage. Biasing the gate of the D-mode FET by a positive voltage provides a mechanism for balancing gain variation and PAE .

[0069] The E-mode transistor is also herein referred to as a normally-on transistor. This is because the E-mode transistor conducts when operating with a gate-source voltage of 0V . The D-mode transistor is also herein referred to as a normally-off transistor.

[0070] FIG. 3 is a schematic diagram of a power amplifier 250 according to an embodiment. The power amplifier 250 includes an E-mode MOS transistor 241, a D-mode Schottky gate FET 242, an input DC block capacitor 243, an output DC block capacitor 244, a gate bias inductor 245 and a choke inductor 246.

[0071] Although FIG. 3 depicts one embodiment of a composite cascode power amplifier, the teachings herein are also applicable to composite cascode power amplifiers implemented in a variety of manners.

[0072] The power amplifier 250 receives an RF input signal RF IN at an RF input terminal and provides an amplified RF output signal RF OUT at an RF output terminal. In the illustrated embodiment, the input DC block capacitor 243 is connected between the RF input terminal and the gate of the E-mode MOS transistor 241 to allow biasing of the gate voltage of the E-mode MOS transistor 241 separately from the DC voltage of the RF input terminal. Additionally, the output DC block capacitor 244 is connected between the drain of the D-mode Schottky gate FET 242 and the RF output terminal to decouple the drain voltage of the FET 242 from the DC voltage of the RF output terminal.

[0073] As shown in FIG. 3, the choke inductor 246 supplies a power amplifier supply voltage V to the drain of the D-mode Schottky gate FET 242. The power amplifier supply voltage V PA PA includes, but is not limited to, any of the envelope trackers disclosed herein. ​​​​​​​can be generated by.

[0074] The E-mode MOS transistor 241 includes a gate that receives the RF input signal RF IN . . The D-mode FET 242 is cascode-connected to the E-mode MOS OUT transistor 241 to generate the RF output signal RF . In the illustrated embodiment, the gate of the E-mode MO S transistor 241 is biased by the gate bias voltage V provided by the gate bias inductor 245, while the gate of the D-mode Schottky gate GBIAS FET 242 is biased by the ground voltage (ground). In a predetermined actual installation example, the E-mode MOS transistor 241 is a short-channel n-type metal-oxide-semiconductor (NMOS) transistor.

[0075] FIG. 4A is a graph of an example of the power gain versus the output power of a common-source n-type metal-oxide-semiconductor (NMOS) power amplifier.

[0076] FIG. 4B is a graph of an example of the power gain versus the output power of a composite cascode power amplifier.

[0077] As shown by the comparison between FIG. 4A and FIG. 4B, by implementing the power amplifier as a composite cascode power amplifier, the variation in gain is reduced (for example, in this example, it is reduced from about 15 dB to about 3 dB).

[0078] FIG. 4C is a graph of an example of the quiescent drain current versus the supply voltage of a common-source NMOS power amplifier.

[0079] FIG. 4D is a graph of an example of the quiescent drain current versus the supply voltage of a composite cascode power amplifier. ​

[0080] As shown by comparing FIG. 4C and FIG. 4D, the power amplifier may be a composite cascode power amplifier. By implementing the device as a drain, the variation in the quiescent drain current is reduced (for example, In the example, the reduction is from about 12x to about 1.25x.

[0081] FIG. 5A is a graph of an example of power gain versus output power for a composite cascode amplifier.

[0082] FIG. 5B shows an example graph of power added efficiency (PAE) versus output power of a composite cascode power amplifier. It's rough.

[0083] FIG. 5C is a graph of an example of quiescent current versus power amplifier supply voltage for a composite cascode power amplifier. It is.

[0084] FIG. 6 is a schematic diagram of a power amplifier 280 according to another embodiment. , E-mode MOS transistor 241, D-mode Schottky gate FET 242, input DC blocking capacitor 243, output DC blocking capacitor 244, gate bias in The inductor 245 and the choke inductor 246 .

[0085] Power amplifier 280 in FIG. 5 is similar to power amplifier 250 in FIG. 3, except that power amplifier 280 in FIG. At 280, a cascode gate bias voltage C having a positive voltage above ground CB IAS The difference is that the D-mode Schottky gate FET 242 is biased by become.

[0086] By biasing the gate of the D-mode FET 242 with a positive voltage, the gain is This provides a mechanism for balancing between variability and PAE.

[0087] Figure 7A is a graph of an example of drain current versus drain voltage of a short-channel MOS transistor. Drain current versus drain voltage plots at different gate-source voltages of the short-channel MOS transistor are drawn. Both plots are included: the case without considering channel length modulation (dashed-line plot) and the case considering channel length modulation (solid-line plot). Figure 7B is a graph of an example of drain current versus gate voltage of a short-channel MOS transistor. An example of the shift of the transistor threshold voltage caused by drain-induced barrier lowering is drawn in the graph. Figures 8A and 8B show two examples of power amplifier supply voltage versus time. In Figure 8A, graph 447 shows an example of the voltage of RF signal 441 and power amplifier supply voltage 443 versus time. RF signal 441 has an envelope 442. Importantly, the power amplifier supply voltage 443 of the power amplifier has a voltage greater than that of the RF signal 441. For example, supplying power to the power amplifier using a power amplifier supply voltage having an amplitude smaller than the amplitude of the RF signal may clip the RF signal, and thus may cause signal distortion and / or other problems. That is, it may be important to set the power amplifier supply voltage 443 to be larger than the envelope 442. However, the voltage difference between the power amplifier supply voltage 443 and the envelope 442 of the RF signal 441 is desirably reduced. The area between the power amplifier supply voltage 443 and the envelope 442 reduces the battery life.

[0088]

[0089]

[0090]

[0091] ​​​​​​​​​​​​​ This is because it can represent the lost energy that can increase the heat generated in the wireless device while causing it. occurs.

[0092] In FIG. 8B, graph 448 shows an example of the voltage of RF signal 441 and the power amplifier supply voltage 444 versus time. In contrast to the power amplifier supply voltage 443 in FIG. 8A, the power amplifier supply voltage 444 in FIG. 8B changes in relation to the envelope 442 of the RF signal 441. In FIG. 8B the area between the power amplifier supply voltage 444 and the envelope 442 is smaller than the area between the power amplification supply voltage 443 and the envelope 442 in FIG. 8A, so the graph 4 48 in FIG. 8B can be associated with a power amplifier with high energy efficiency.

[0093] FIG. 9A is a schematic diagram of an envelope tracking system 500 according to an embodiment. The envelope tracking system 500 includes a power amplifier 501 and an envelope tracker 502. The power amplifier 50 1 amplifies the radio frequency signal 503.

[0094] The envelope tracker 502 receives an envelope signal 504 corresponding to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 502 generates a power amplifier supply voltage V to supply power to the power amplifier 501. PA

[0095] The illustrated envelope tracker 502 includes a DC / DC converter 511 and an error amplifier 512, which are combined with each other and operate to generate a power amplifier supply voltage V PA based on the envelope signal 504. In the illustrated embodiment, the output of the DC / DC converter 511 and the output of the error amplifier 512 are combined using a coupler 515.

[0096] ​ The envelope tracker 502 of FIG. 9A shows an example of analog envelope tracking where switching regulators operate in parallel with each other to track the envelope of the R F signal.

[0097] FIG. 9B is a schematic diagram of an envelope tracking system 540 according to another embodiment. The envelope tracking system 540 includes a power amplifier 501 and an envelope tracker 532. The power amplifier 50 1 amplifies the radio frequency signal 503.

[0098] The envelope tracker 532 receives an envelope signal 504 corresponding to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 532 generates a power amplifier supply voltage V for supplying power to the power amplifier 501. PA

[0099] The illustrated envelope tracker 532 includes a multi-level switching circuit 535. In a given implementation example, the multi-level switching circuit includes a multi-output DC / DC converter that generates regulated voltages of different voltage levels, a plurality of switches that control the selection of an appropriate regulated voltage over time based on the envelope signal, and a filter that filters the output of the switches to generate the power amplifier supply voltage.

[0100] The envelope tracker 532 of FIG. 9B shows an example of MLS envelope tracking.

[0101] FIG. 10 is a schematic diagram of an envelope tracking system according to another embodiment. The envelope tracking system 600 includes a power amplifier 501 and an envelope tracker 602. The power amplifier 501 amplifies the radio frequency signal 503.

[0102] ​​​​​​​​The envelope tracker 602 receives an envelope signal corresponding to the envelope of the radio frequency signal 503. In this example, the envelope signal is differential. Additionally, the envelope tracker 602 generates a power amplifier supply voltage V that supplies power to the power amplifier 501. PA

[0103] The illustrated envelope tracker 602 includes an envelope amplifier 611, a first comparator 621, a second comparator 622, a third comparator 623, a coding and dithering circuit 624, a multi-output boost switch 625, a filter 626, a switch bank 627, and a capacitor bank 630. The capacitor bank 630 includes a first capacitor 631, a second capacitor 632, and a third capacitor 633. Additionally, the switch bank 627 includes a first switch 641, a second switch 642, and a third switch 643.

[0104] The envelope amplifier 611 amplifies the envelope signal and provides the amplified envelope signal to the first comparator 621 to the third comparator 623. The first comparator 621 to the third comparator 623 compare the amplified envelope signal with a first threshold T1, a second threshold T2, and a third threshold T3, respectively. The comparison results are provided to the coding and dithering circuit 624. The coding and dithering circuit 624 processes the results to control the selection of the switches in the switch bank 627. The coding and dithering circuit 624 can use coding and / or dithering while activating the switches to reduce artifacts resulting from the opening and closing of the switches.

[0105] Although an example with three comparators is shown, more or fewer comparators may be used. ​​​​​​​​​​​​​​The device may be used. Further, the coding dithering circuit 624 may be omitted, and other aspects may choose to control the switch bank. In the first example, coding is used but dithering is not used. In the second example, dithering is used but coding is not used. In the third example, neither coding nor dithering is used.

[0106] The multi-output boost switch 625 provides DC / DC conversion of the battery voltage V BATT to generate a first regulated voltage V , a second regulated voltage V MLS1 , and a third regulated voltage V MLS2 . Although an example with three regulated voltages is shown, the multi-output boost switch 625 can generate more or fewer regulated voltages than this. In a given implementation example, at least a portion of these regulated voltages are boosted with respect to the battery voltage V . In some configurations, one or more of these regulated voltages are buck voltages having a voltage lower than the battery voltage V MLS3 . BATT BATT

[0107] The capacitor bank 630 assists in stabilizing the regulated voltages generated by the multi-output boost switch 625. For example, the capacitors 631 - 633 operate as decoupling capacitors.

[0108] The filter 626 processes the output of the switch bank 627 to generate the power amplifier supply voltage V PA . The selection of the switches 641 - 643 is controlled over time based on the envelope signal. As a result, a power amplifier supply voltage V that tracks the envelope signal is generated. PA is generated.

[0109] FIG. 11A is a schematic diagram of an embodiment of a package-like module 800. FIG. 11 B is a schematic cross-sectional view of the package-like module 800 taken along line 11B-11B of FIG. 11A. is a diagram.

[0110] The package-like module 800 includes an IC or die 801, a surface mount component 80 3, wire bonds 808, a package substrate 820, and an encapsulation structure 840. The package substrate 820 includes pads 806 formed from conductors disposed therein. Additionally, the die 801 includes pads 804, and the wire bonds 808 are used to electrically connect the pads 804 of the die 801 to the pads 806 of the package substrate 820.

[0111] The die 801 includes a power amplifier 846 that can be implemented according to any of the embodiments herein.

[0112] The package substrate 820 is configured to receive a plurality of components, including the die 801 and surface mount components 803 that may include, for example, surface mount capacitors and / or inductors. can be configured.

[0113] As shown in FIG. 11B, the package-like module 800 is shown to include a plurality of contact pads 832 disposed on the side of the package-like module 800 opposite the side used to attach the die 801. By configuring the package-like module 800 in this manner, the package-like module 800 can be used as a telephone board of a wireless device, for example. is shown to include. configured in this manner, the package-like module 800 can be used as a telephone board of a wireless device, for example. is assisted in connecting to a printed circuit board. An example of contact pad 832 is for providing an RF signal, a bias signal, a power supply low voltage and / or a power supply high voltage to die 801 and / or surface-mounted component 803. As shown in FIG. 11B, the electrical connection between contact pad 832 and die 801 can be facilitated by connection 833 through package substrate 820. Connection 833 may represent an electrical path formed to pass through package substrate 820, such as a connection associated with vias and conductors of a multi-layer laminate package substrate.

[0114] In some embodiments, package module 800 may also include one or more package structures, for example, to provide protection for and / or facilitate handling of package module 800. Such package structures may include an overmold or encapsulation structure 840 formed to cover package substrate 820 and the components and die disposed thereon.

[0115] It is understood that although package module 800 is described in the context of wirebond-based electrical connection, one or more features of the present disclosure can also be implemented in other package configurations, including, for example, a flip-chip configuration.

[0116] FIG. 12 is a schematic diagram of an embodiment of a telephone substrate. Telephone substrate 900 includes module 800 shown in accompanying FIGS. 11A and 11B. Although not shown explicitly in FIG. 12 for clarity, telephone substrate 900 may include additional components and structures.

[0117] Application​​​​

[0118] Some of the above-described embodiments have been given by way of example in relation to wireless devices or mobile phones. However, the principles and advantages of those embodiments can be used in any other system or apparatus that requires a power amplifier.

[0119] Such an envelope tracker can be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics products, components of such consumer electronics products, electronic test equipment, etc. Examples of electronic devices may also include, but are not limited to, memory chips, memory modules, optical network or other communication network circuits, and disk driver circuits. Consumer electronics products include, but are not limited to, mobile phones, telephones, televisions, computer monitors, computers, handheld computers, personal digital assistants (PDAs), microwave ovens, refrigerators, automobiles, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, MP3 players, radios, video cameras, cameras, digital cameras, portable memory chips, washing machines, dryers, washing / drying machines, copiers, fax machines, scanners, multifunctional peripheral devices, wristwatches, table clocks, etc. Further, the electronic devices may include unfinished products.

[0120] Summary

[0121] Throughout this specification and the claims, unless the context clearly dictates otherwise, terms such as "comprising" are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to". As used herein, the singular forms ​ The term "coupled" refers to two or more elements that can be either directly connected or connected through one or more intervening elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be either directly connected or connected through one or more intervening elements. In addition, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular portion thereof. Where the context permits, the terms in the foregoing detailed description using the singular or plural number may each include the plural or singular number, respectively. The words "or" and "and / or" referring to a list of two or more items cover all of the following interpretations of that word, namely, any item in the list, all items in the list, and any combination of items in the list. Furthermore, conditional language such as, among others, "can", "may", "is permitted", "might", "such as", "for example", etc. as set forth herein is generally intended to convey that a particular embodiment includes a particular feature, element and / or state while other embodiments do not, unless specifically stated otherwise or understood from the context of use to be the contrary. That is, such conditional language is generally not intended to imply that a feature, element and / or state is in any way required for one or more embodiments or that one or more embodiments necessarily include, with or without author input or prompting, logic to determine whether or not such features, elements and / or states are included in or performed by any particular embodiment. The term "coupled" refers to two or more elements that can be either directly connected or connected through one or more intervening elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be either directly connected or connected through one or more intervening elements. In addition, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular portion thereof. Where the context permits, the terms in the foregoing detailed description using the singular or plural number may each include the plural or singular number, respectively. The words "or" and "and / or" referring to a list of two or more items cover all of the following interpretations of that word, namely, any item in the list, all items in the list, and any combination of items in the list. That is, such conditional language is generally not intended to imply that a feature, element and / or state is in any way required for one or more embodiments or that one or more embodiments necessarily include, with or without author input or prompting, logic to determine whether or not such features, elements and / or states are included in or performed by any particular embodiment. Furthermore, conditional language such as, among others, "can", "may", "is permitted", "might", "such as", "for example", etc. as set forth herein is generally intended to convey that a particular embodiment includes a particular feature, element and / or state while other embodiments do not, unless specifically stated otherwise or understood from the context of use to be the contrary. The term "coupled" refers to two or more elements that can be either directly connected or connected through one or more intervening elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be either directly connected or connected through one or more intervening elements. In addition, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular portion thereof.

[0122] Furthermore, conditional language such as, among others, "can", "may", "is permitted", "might", "such as", "for example", etc. as set forth herein is generally intended to convey that a particular embodiment includes a particular feature, element and / or state while other embodiments do not, unless specifically stated otherwise or understood from the context of use to be the contrary. That is, such conditional language is generally not intended to imply that a feature, element and / or state is in any way required for one or more embodiments or that one or more embodiments necessarily include, with or without author input or prompting, logic to determine whether or not such features, elements and / or states are included in or performed by any particular embodiment. The words "or" and "and / or" referring to a list of two or more items cover all of the following interpretations of that word, namely, any item in the list, all items in the list, and any combination of items in the list. Where the context permits, the terms in the foregoing detailed description using the singular or plural number may each include the plural or singular number, respectively. In addition, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular portion thereof. Furthermore, conditional language such as, among others, "can", "may", "is permitted", "might", "such as", "for example", etc. as set forth herein is generally intended to convey that a particular embodiment includes a particular feature, element and / or state while other embodiments do not, unless specifically stated otherwise or understood from the context of use to be the contrary. That is, such conditional language is generally not intended to imply that a feature, element and / or state is in any way required for one or more embodiments or that one or more embodiments necessarily include, with or without author input or prompting, logic to determine whether or not such features, elements and / or states are included in or performed by any particular embodiment. The term "coupled" refers to two or more elements that can be either directly connected or connected through one or more intervening elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be either directly connected or connected through one or more intervening elements. In addition, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular portion thereof.

[0123] The above detailed description of the embodiments of the present invention is not exclusive, that is, the present invention is not intended to be limited to the exact form of the above disclosure. Specific embodiments of the present invention and examples thereof have been described above for illustrative purposes, but as will be appreciated by those skilled in the art, various equivalent modifications are possible within the scope of the present invention. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times. The teachings of the present invention provided herein are not necessarily limited to the system described above and can also be applied to other systems. The various embodiment elements and acts described above can be combined to provide further embodiments. Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times. Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times. For example, although processes or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or use systems with blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. These processes or blocks can each be implemented in various different ways. Also, although processes or blocks may be shown as being performed serially, these processes or blocks can instead be performed in parallel or at different times.

[0124] The teachings of the present invention provided herein are not necessarily limited to the system described above and can also be applied to other systems. The various embodiment elements and acts described above can be combined to provide further embodiments. The teachings of the present invention provided herein are not necessarily limited to the system described above and can also be applied to other systems. The various embodiment elements and acts described above can be combined to provide further embodiments. The teachings of the present invention provided herein are not necessarily limited to the system described above and can also be applied to other systems. The various embodiment elements and acts described above can be combined to provide further embodiments.

[0125] Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. Although several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents define the scope of the present disclosure. It is intended to cover such forms or modifications as fall within the scope and spirit.

Claims

1. 1. A mobile device comprising: a transceiver configured to generate a radio frequency signal; configured to generate a power amplifier supply voltage that varies in relation to the envelope of the radio frequency signal. a power management system including an envelope tracker configured to a power amplifier configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage; A front-end system including a composite cascode power amplifier. Including, The composite cascode power amplifier comprises: an enhancement mode field effect transistor configured to receive the radio frequency signal; Sta. and Depletion cascoded to the enhancement mode field effect transistor Mode Field Effect Transistor , including mobile devices.

2. The enhancement mode field effect transistor is a metal oxide semiconductor transistor. The mobile device of claim 1.

3. The depletion mode field effect transistor is a Schottky gate field effect transistor. The mobile device of claim 1 , wherein the mobile device is a digital camera.

4. the source of the enhancement mode field effect transistor is connected to a ground voltage; The drain of the enhancement mode field effect transistor is a mode field effect transistor connected to the output terminal of the composite cascode power amplifier; The mobile device of claim 1 .

5. The gate of the depletion mode transistor is biased by the ground voltage. The mobile device of claim 4 .

6. The gate of the depletion mode transistor is connected to a positive voltage above the ground voltage. The hand-held device of claim 4, further biased.

7. The composite cascode power amplifier further comprises a power amplifier supply voltage and a depletion voltage. A choke inductor electrically connected between the drain of the on-mode field effect transistor and the The mobile device of claim 1 , further comprising:

8. The composite cascode power amplifier further comprises: a gate bias inductor configured to provide a gate bias voltage to the gate of the transistor; The mobile device of claim 1 .

9. The envelope tracker comprises: a DC / DC converter configured to output a plurality of regulated voltages; At the output, a modulation is performed based on the plurality of regulated voltages and the envelope of the radio frequency signal. a modulator configured to generate a modulator output voltage; and a modulator output filter coupled between the modulator output and a power amplifier supply voltage; The mobile device of claim 1 .

10. The envelope trackers are configured to operate in parallel with one another to generate the power amplifier supply voltage.

2. The portable device of claim 1 , comprising a DC / DC converter and an error amplifier configured as follows:

11. 1. An envelope tracking system comprising: configured to generate a power amplifier supply voltage that varies in relation to the envelope of a radio frequency signal; an envelope tracker for a power amplifier configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage; A composite cascode power amplifier formed by Including, The composite cascode power amplifier comprises: an enhancement mode field effect transistor configured to receive the radio frequency signal; Sta. and Depletion cascoded to the enhancement mode field effect transistor Mode Field Effect Transistor An envelope tracking system comprising:

12. The enhancement mode field effect transistor is a short channel n-type metal oxide semiconductor transistor.

12. The envelope tracking system of claim 11, wherein the transistor is a transistor.

13. the source of the enhancement mode field effect transistor is connected to a ground voltage; The drain of the enhancement mode field effect transistor is a mode field effect transistor connected to the output terminal of the composite cascode power amplifier; The envelope tracking system of claim 11 .

14. The gate of the depletion mode transistor is biased by the ground voltage. The envelope tracking system of claim 13 .

15. The gate of the depletion mode transistor is connected to a positive voltage above the ground voltage. The envelope tracking system of claim 13, further biased.

16. The envelope tracker comprises: a DC / DC converter configured to output a plurality of regulated voltages; At the output, a modulation is performed based on the plurality of regulated voltages and the envelope of the radio frequency signal. a modulator configured to generate a modulator output voltage; and a modulator output filter coupled between the modulator output and a power amplifier supply voltage; The envelope tracking system of claim 11 , comprising:

17. The envelope trackers are configured to operate in parallel with one another to generate the power amplifier supply voltage.

12. The envelope tracking system of claim 11, comprising a DC / DC converter and an error amplifier configured as follows: Hmm.

18. 1. A method of radio frequency signal amplification in a mobile device, comprising: An envelope tracker is used to track the power amplifier supply voltage which varies in relation to the envelope of the radio frequency signal. Generating pressure; said power amplifier supply voltage being used to power a composite cascode power amplifier. The composite cascode power amplifier includes enhancement mode field effect transistors and A depletion transistor cascoded to the enhancement mode field effect transistor a first mode field effect transistor; amplifying said radio frequency signal using said composite cascode power amplifier; The method includes:

19. The enhancement mode field effect transistor is a metal oxide semiconductor transistor. the law of nature, The depletion mode field effect transistor is a Schottky gate field effect transistor. The method of claim 18, wherein the

20. the source of the enhancement mode field effect transistor is connected to a ground voltage; The method further comprises: switching the depletion mode using a positive voltage above the ground voltage.

20. The method of claim 18, further comprising biasing a gate of the transistor.

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