Amplitude limiting amplification circuit and radio frequency transceiver chip

Abstract

The embodiment of the utility model provides an amplitude limiting amplification circuit and a radio frequency transceiver chip, the amplitude limiting amplification circuit comprises one stage of amplification units or multiple stages of amplification units connected in series, and each stage of amplification unit at least comprises an amplification transistor; the detection unit is connected with the signal input end of the amplitude limiting amplification circuit and used for detecting the input signal received by the amplitude limiting amplification circuit and then outputting a detection signal, and the amplitude of the detection signal is in positive correlation with the power of the input signal; at least one stage of amplification unit is provided with an amplitude limiting unit, the signal input end is connected with the control end of the amplification unit and the signal input end of the amplitude limiting amplification circuit, and the control end is connected with the signal output end of the detection unit; the detection signal is used for controlling on and off of the amplitude limiting unit; at least one end of the diode protection unit is connected with the control end of the amplification transistor, the diode protection unit comprises a forward diode string and / or a backward diode string, and the diode string comprises a diode or a plurality of diodes connected in series.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of radio frequency circuits, and in particular to a limiting amplifier circuit and a radio frequency transceiver chip. Background Art

[0002] To reduce the size and weight of phased array systems and improve overall performance, highly integrated systems often integrate transmit and receive channels on the same array surface, even sharing a common antenna. To meet the demands of long-distance communications or radar detection, phased array systems typically require high transmit power. However, transmitting power entering the receive channel can damage components such as amplifiers on the receiving end. Therefore, effective measures are needed to prevent transmit power leakage into the receive channel and protect receiving-end components from damage. Utility Model Content

[0003] In view of this, the embodiments of the present application hope to provide a stable and effective limiting amplifier circuit and radio frequency transceiver chip.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present application is implemented as follows:

[0005] An embodiment of the present application provides a limiting amplifier circuit, the limiting amplifier circuit comprising:

[0006] One stage or multiple stages of amplifier units connected in series, each stage of the amplifier unit comprising at least one amplifier transistor;

[0007] a detection unit connected to the signal input terminal of the limiting amplifier circuit, configured to detect the input signal received by the limiting amplifier circuit and output a detection signal, wherein the amplitude of the detection signal is positively correlated with the power of the input signal;

[0008] At least one stage of the amplification unit is configured with a limiting unit, the signal input end of the limiting unit is respectively connected to the control end of the amplification unit and the signal input end of the limiting amplifier circuit, and the control end of the limiting unit is connected to the signal output end of the detection unit; the detection signal is used to control the opening and closing of the limiting unit;

[0009] One or more diode protection units, at least one end of each diode protection unit is connected to the control end of the amplifying transistor, and each diode protection unit includes a forward diode string and / or a reverse diode string, and each diode string includes one diode or multiple diodes connected in series.

[0010] In some embodiments, the limiting amplifier circuit further includes an input matching unit connected between the signal input terminal of the limiting unit and the control terminal of the amplifier unit;

[0011] The input matching unit includes at least one of the following passive elements: a capacitor, an inductor, and a resistor.

[0012] The input matching unit is used to match the impedance between the input signal and the control end of the amplifying unit;

[0013] One end of the diode protection unit is connected to the gate of the amplifying transistor through the passive element; the other end is connected to the source of the amplifying transistor or is grounded.

[0014] In some embodiments, the limiting unit includes at least one limiting transistor, the gate of the limiting transistor is connected to the signal output terminal of the detection unit, the drain is connected to the signal input terminal of the limiting amplifier circuit, and the source is grounded;

[0015] The equivalent capacitance of the limiting transistor and the input matching unit are used together to match the impedance between the input signal and the control terminal of the amplifying unit.

[0016] In some embodiments, the detection unit includes a half detection circuit and / or a full detection circuit;

[0017] The full detection circuit is composed of two half detection circuits connected in reverse parallel.

[0018] In some embodiments, the half detection circuit includes:

[0019] The detection diode and detection resistor are connected in series.

[0020] One end of the detection diode is connected to the signal input end of the limiting amplifier circuit, and the other end is respectively connected to the control end of the limiting unit and the detection resistor. The other end of the detection resistor is grounded.

[0021] In some embodiments, the limiting amplifier circuit further includes a first DC amplifier, one end of which is connected to the signal output end of the detection unit and the other end of which is connected to the control end of the limiting unit.

[0022] The first DC amplifier is used to amplify the detection signal and control the opening and closing of the limiter unit according to the amplified detection signal.

[0023] In some embodiments, the limiting amplifier circuit further includes:

[0024] a bias unit connected to the gate of the amplifying transistor and configured to provide a bias current or a bias voltage;

[0025] a switch, wherein a first end is connected to the bias unit, a second end is grounded, and a control end is connected to the signal output end of the detection unit, and the switch is used to control the opening and closing of the bias unit according to the detection signal;

[0026] A second DC amplifier has one end connected to the signal output end of the detection unit and the other end connected to the control end of the switch; the second DC amplifier is used to amplify the detection signal and control the opening and closing of the bias unit according to the amplified detection signal.

[0027] In some embodiments, the bias unit includes a current source, a bias transistor, and a bias resistor;

[0028] The gate of the bias transistor is connected to the control terminal of the amplifying unit through the bias resistor, the drain is connected to the power supply terminal through the current source, and the source is grounded;

[0029] A first end of the switch is connected to the drain of the bias transistor, and a second end of the switch is connected to the source of the bias transistor.

[0030] In some embodiments, the amplifying unit includes a first amplifying transistor and a second amplifying transistor connected in series;

[0031] The bias unit includes a bias input terminal;

[0032] The gate of the first amplifying transistor is connected to the signal input terminal of the limiting amplifying circuit, the drain is connected to the source of the second amplifying transistor, and the source is grounded;

[0033] The gate of the second amplifying transistor is connected to the bias input terminal, and the drain is connected to the signal output terminal of the limiting amplifier circuit;

[0034] A first end of the switch is connected to the bias input end, and a second end of the switch is grounded.

[0035] The embodiment of the present application further provides a radio frequency transceiver chip, the radio frequency transceiver chip comprising a receiving channel and a transmitting channel;

[0036] The receiving channel includes the above-mentioned limiting amplifier circuit.

[0037] The limiting amplifier circuit provided in the embodiment of the present application, on the one hand, is provided with a detection unit and a limiting unit at the signal input end of the limiting amplifier circuit, and the working state of the limiting unit is controlled by the detection voltage output by the detection unit, thereby limiting the power level of the input signal and reducing the terminal voltage swing of the amplifying transistor in the amplifying unit; on the other hand, by providing a diode protection unit on the transmission path of the input signal, the response time of the limiting amplifier circuit is reduced, and the possibility of the amplifying transistor in the amplifying unit being broken down is effectively reduced, thereby providing higher protection capabilities for the limiting amplifier circuit and subsequent circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the structure of the amplifying transistor in the embodiment of this application

[0039] Figure 2 A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 1 ;

[0040] Figure 3 A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 2 ;

[0041] Figures 4A-4C Schematic diagram of the diode protection unit in the embodiment of the present application Figures 1 to 3 ;

[0042] Figure 5 A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 3 ;

[0043] Figure 6 This is a comparison diagram of the voltage swing of the amplifying transistor terminal in the embodiment of the present application;

[0044] Figure 7 Schematic diagram 4 of a limiting amplifier circuit provided in an embodiment of the present application;

[0045] Figures 8A-8B Schematic diagram of the input matching unit in the embodiment of this application Figures 1 and 2 ;

[0046] Figures 9A-9B A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figures 5 to 6 ;

[0047] Figure 10 A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 7 ;

[0048] Figures 11A-11C This is a schematic diagram of the connection of the limiting unit in the embodiment of the present application. Figures 1 to 3 ;

[0049] Figure 12 Schematic diagram 8 of a limiting amplifier circuit provided in an embodiment of the present application;

[0050] Figure 13A Schematic diagram of a half-detection circuit in an embodiment of the present application;

[0051] Figure 13B Schematic diagram of a full detection circuit in an embodiment of the present application;

[0052] Figure 14 Schematic diagram 9 of a limiting amplifier circuit provided in an embodiment of the present application;

[0053] Figure 15A A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 10;

[0054] Figure 15B A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 10 one;

[0055] Figure 16 A schematic diagram of a limiting amplifier circuit provided in an embodiment of the present application Figure 10 two;

[0056] Figure 17 A schematic diagram of the structure of a radio frequency transceiver chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the embodiments of this application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0058] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0059] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0060] During wireless communication, the RF signal received by the antenna is often weak and may be affected by various interferences and noises. Therefore, it is necessary to enhance the received RF signal through an amplifier to improve the signal-to-noise ratio and receiving sensitivity of the RF signal. Specifically, the amplifier can amplify the weak RF signal received at the RF input (RFIN) end and output it to the RF output (RFOUT) end for subsequent circuits or systems to process. The amplification process is usually completed by transistors inside the amplifier. The transistor can be a metal oxide semiconductor (MOS) transistor. For example Figure 1As shown, a gate oxide layer 104 is included between the gate 101 and the channel (between the source 102 and the drain 103) of the MOS transistor. Common failure modes of MOS transistors include gate oxide breakdown and hot carrier injection. Gate oxide breakdown refers to the formation of a current path in the gate oxide layer 104 when the transistor gate voltage (gate-source voltage or gate-drain voltage) is high, causing the oxide layer performance to degrade, which can accumulate over time and lead to gate damage. Hot carrier injection refers to the generation of hot carriers in the channel when the drain-source voltage of the MOS transistor is high, which scatters in all directions and may destroy the lattice, leading to device degradation or damage. Due to the amplification effect of the amplifier, as the input signal power increases, the signal voltage swing increases. After transistor amplification, the voltage swing is further increased. This results in the MOS transistor failing when a high-power signal is input, causing the transistor terminal voltage in the amplifier circuit to be too high, resulting in irreversible damage to the circuit.

[0061] In view of this, an embodiment of the present application provides a limiting amplifier circuit, such as Figure 2 As shown, the limiting amplifier circuit 200 includes:

[0062] One or more stages of amplifier units 201 connected in series, each stage of amplifier unit 201 comprising at least one amplifier transistor;

[0063] The detection unit 202 is connected to the signal input terminal of the limiting amplifier circuit (i.e., the above-mentioned RFIN terminal), and is used to detect the input signal received by the limiting amplifier circuit and output a detection signal. The amplitude of the detection signal is positively correlated with the power of the input signal.

[0064] At least one stage of the amplification unit 201 is configured with a limiting unit 203. The signal input terminal of the limiting unit 203 is respectively connected to the control terminal of the amplification unit 201 and the signal input terminal of the limiting amplifier circuit (i.e., the aforementioned RFIN terminal). The control terminal of the limiting unit 203 is connected to the signal output terminal of the detection unit 202. The detection signal is used to control the opening and closing of the limiting unit 203.

[0065] One or more diode protection units 204, at least one end of each diode protection unit 204 is connected to the control end of the amplifying transistor, the diode protection unit includes a forward diode string and / or a reverse diode string, and the diode string includes one diode or multiple diodes connected in series.

[0066] Detection unit 202 is used to detect power. Based on the power of the input signal, it outputs a detection voltage to limiter unit 203, thereby controlling the on / off state of limiter unit 203. The amplitude of the detection signal is positively correlated with the power of the input signal. Specifically, when the power of the input signal is low, detection unit 202 outputs a low detection voltage. When the power of the input signal is high, detection unit 202 outputs a high detection voltage, and limiter unit 203 begins operating, limiting the power level of the input signal and protecting subsequent circuits from damage.

[0067] Considering that when a high-power signal is input, the switching of the detection unit 202 and the limiter unit 203 requires a certain amount of time to respond, and during this response process, the voltage at the terminal of the amplifier transistor will still be relatively high. Therefore, the embodiment of the present application utilizes the fast response speed of the diode. The diode in the diode protection unit 204 can quickly conduct during the response of the limiter unit 203 to form a low-resistance path, thereby quickly releasing power and reducing the terminal voltage swing of the amplifier transistor.

[0068] It should be noted that at least one end of the diode protection unit 204 needs to be connected to the control end of the amplifying transistor. That is, one end of the diode protection unit 204 is directly connected to the gate of the amplifying transistor, or one end of the diode protection unit 204 is indirectly connected to the gate of the amplifying transistor through other electronic components. It can be seen that the diode protection unit 204 can be added to any node in the limiting amplifier circuit. Among them, one end of the diode protection unit can be directly connected to the gate of the amplifying transistor, or indirectly connected to the amplifying transistor through other electronic components. The other end of the diode protection unit can be directly connected to the source of the amplifying transistor or indirectly connected to the drain of the amplifying transistor through electronic components; or grounded (directly grounded, or indirectly grounded through passive components). That is, the diode protection unit only needs to meet the requirement that one end is connected to the RF signal channel.

[0069] Figure 3 FIG. 1 shows a schematic structural diagram of a limiting amplifier circuit in an embodiment of the present application. Figure 3 As shown, the limiting amplifier circuit includes a first-stage amplifier unit 201. Amplifier unit 201 includes an amplifier transistor M0. The gate of amplifier transistor M0 is connected to the signal input terminal of detection unit 202 and the signal input terminal of limiting unit 203. The drain of amplifier transistor M0 is connected to the signal output terminal RFOUT of the limiting amplifier circuit, and the source is grounded. Amplifier transistor M0 is configured with a diode protection unit 204 connected between the gate and source of amplifier transistor M0. In other embodiments, diode protection unit 204 can also be connected between the gate and drain of amplifier transistor M0.

[0070] Figures 4A-4CThree different diode protection units 204 in the limiting amplifier circuit are shown respectively. Figure 4A As shown, the diode protection unit 204 includes a forward diode string, and the forward diode includes two diodes connected in series. Specifically, the positive electrode of the diode is connected to the gate of the amplifying transistor M0, and the negative electrode is connected to the source of the amplifying transistor M0. Figure 4B As shown, the diode protection unit 204 includes a reverse diode string, and the reverse diode includes two diodes connected in series. Specifically, the cathode of the diode is connected to the gate of the amplifying transistor M0, and the anode is connected to the source of the amplifying transistor M0. Figure 4C As shown, the diode protection unit includes a forward diode string and a reverse diode string connected in parallel. The forward diode string includes two diodes connected in series, and the reverse diode string includes two diodes. It should be noted that the embodiments of the present application do not limit the specific number of diodes in the forward diode string and the reverse diode string.

[0071] Figure 5 FIG. 1 shows a schematic structural diagram of a limiting amplifier circuit in another embodiment of the present application. Figure 5 As shown, the limiting amplifier circuit includes two cascaded amplifier units. Specifically, an input signal flows into the RFIN terminal, is amplified by the first-stage amplifier unit 201a, then flows into the second-stage amplifier unit 201b, and after further amplification, flows out of the RFOUT terminal. The first-stage amplifier unit 201a includes a first amplifier transistor M1 and a second amplifier transistor M2 connected in series. The second-stage amplifier unit 201b includes a third amplifier transistor M3 and a fourth amplifier transistor M4 connected in series. The gate of the first amplifier transistor M1 is connected to the RFIN terminal; the drain is connected to the source of the second amplifier transistor M2; and the source is grounded. The gate of the second amplifier transistor M2 is connected to a first bias voltage V1; the drain is connected to the control terminal of the second-stage amplifier unit (the gate of the third transistor M3). The drain of the third amplifier transistor M3 is connected to the source of the fourth amplifier transistor M4; the source is grounded. The gate of the fourth amplifier transistor M2 is connected to a second bias voltage V2; and the drain is connected to the RFOUT terminal. The first-stage amplifier unit 201a is equipped with a limiting unit 203 and a diode protection unit 204. Specifically, the gate of the first amplifying transistor M1 is connected to the signal input terminal of the detection unit 202 and the signal input terminal of the amplitude limiting unit 203. The diode protection unit 204 is connected between the gate and the source of the first amplifying transistor M1.

[0072] It should be noted that for a limiting amplifier circuit including multiple amplification units, even if the power and voltage at the signal input are limited within the reliability range, the amplification effect of the pre-amplification unit may cause the subsequent amplification unit or device to exceed the reliability operating range. Therefore, the embodiments of the present application do not limit the specific number and specific location of the limiting units and diode protection units, and the limiting units and diode protection units can be added at any location in the RF signal path.

[0073] Figure 6 This is a comparison diagram of the voltage swing of the amplifier transistor provided in the embodiment of the present application. Figure 6 As shown in the figure, the horizontal axis is the time (in nanoseconds) after the circuit is injected with the input signal, and the vertical axis represents the swing of the terminal voltage of the amplifier transistor (gate-source voltage Vgs or gate-drain voltage Vgd). Among them, the first curve represents the terminal voltage swing of the amplifier transistor after the input signal is injected when the input signal is directly amplified using the amplifier unit; the second curve represents the terminal voltage swing of the amplifier transistor after the input signal is injected when a limiter unit is set at the signal input end and a diode protection unit is set between stages. Compared with directly using the amplifier circuit to amplify the input signal, setting a limiter unit at the signal input end and a diode protection unit between stages can not only reduce the response process under high-power signal input, but also reduce the terminal voltage swing of the amplifier transistor after stabilization.

[0074] The limiting amplifier circuit provided in the embodiment of the present application, on the one hand, is provided with a detection unit and a limiting unit at the signal input end of the limiting amplifier circuit, and the working state of the limiting unit is controlled by the detection voltage output by the detection unit, thereby limiting the power level of the input signal and reducing the terminal voltage swing of the amplifying transistor in the amplifying unit; on the other hand, by providing a diode protection unit on the transmission path of the input signal, the response time of the limiting amplifier circuit is reduced, and the possibility of the amplifying transistor in the amplifying unit being broken down is effectively reduced, thereby providing higher protection capabilities for the limiting amplifier circuit and subsequent circuits.

[0075] It should be noted that the input end of the limiting unit can be directly connected to the control end of the amplifying unit, and the input end of the limiting unit can also be connected to the control end of the amplifying unit through other electronic components. However, the RF signal received by the signal input end enters the control end of the amplifying unit through the signal input end of the limiting unit and is amplified by the amplifying transistor. The embodiment of the present application does not limit the specific structure of the amplifying unit. The amplifying unit can change the number of amplification stages according to actual conditions, and can also change the number of amplifying transistors in each stage, but the essence is to amplify the input signal of the RFIN end and output the amplified signal from the RFOUT end. In addition, the embodiment of the present application does not limit the specific type of the amplifying transistor. The amplifying transistor can be a MOS transistor, or a silicon on an insulating substrate (Silicon On Insulator, SOI) transistor, or a bipolar junction transistor (Bipolar Junction Transistor, BJT).

[0076] In some embodiments, as Figure 7 As shown, the limiting amplifier circuit further includes an input matching unit 701 connected between the signal input terminal of the limiting unit 203 and the control terminal of the amplifier unit 201;

[0077] The input matching unit 701 includes at least one of the following passive elements: a capacitor, an inductor, and a resistor.

[0078] The input matching unit 701 is used to match the impedance between the input signal and the control terminal of the amplifying unit 201;

[0079] One end of the diode protection unit 204 is connected to the gate of the amplifying transistor through a passive component; the other end is connected to the source of the amplifying transistor or grounded.

[0080] The input matching unit 701 can adjust the impedance of the input signal to match the input impedance of the amplifying unit 201, thereby reducing reflection and loss of the input signal during transmission and improving the efficiency of signal transmission.

[0081] Figure 8A FIG. 1 is a schematic diagram showing the structure of an input matching unit in an embodiment of the present application. Figure 8A As shown, the input matching unit 701 includes an inductor L1, a first capacitor C1, and a second capacitor C2. Inductor L1 is connected in series between the first and second capacitors C1 and C2, forming a π-shaped input matching unit. By adjusting the capacitance and inductance values, the impedance seen from the signal input terminal can be made equal to the input impedance of the amplifier unit, thereby achieving impedance matching. This allows the signal from the signal input terminal RFIN to be transmitted to the amplifier unit without reflection, thereby improving overall system performance.

[0082] Similarly, in some embodiments, Figure 8B As shown, an output matching unit 801 may be provided between the signal output terminal of the amplifying unit (the drain of the fourth amplifying transistor) and the RFOUT terminal, and / or an inter-stage matching unit 802 may be provided between the multi-stage amplifying units. It should be noted that the embodiments of the present application do not limit the specific structure of passive matching units such as the input matching unit and the output matching unit.

[0083] Continue to refer Figure 8B , the diode protection unit 204 can be set in the input matching unit 701. Specifically, one end of the diode protection unit 204 is connected to the gate of the first amplifying transistor M1 through the inductor L1, and the other end is connected to the source of the first amplifying transistor M1. It should be noted that the diode protection unit 204 can also be set in the inter-stage matching unit 802 or the output matching unit 801; it can also be set between the gate-source or gate-drain of any amplifying transistor. Of course, multiple diode protection units can also be set in the limiting amplifier circuit. For example, Figure 9A As shown, one diode protection unit 204 is provided in the input matching unit 701, and another diode protection unit 204 is provided between the gate and drain of the third amplifying transistor M3. Figure 9B As shown, one diode protection unit 204 is disposed between the gate and source of the first amplifying transistor M1, and another diode protection unit 204 is disposed between the gate and drain of the third amplifying transistor M3. Furthermore, to further enhance the stability of the limiting amplifier circuit, a source feedback circuit (not shown) may be disposed between the source and ground of the first and third amplifying transistors.

[0084] In some embodiments, as Figure 10 As shown, a third capacitor Cin is further included between the signal input terminal RFIN and the input matching unit 701, and a fourth capacitor Cout is further included between the output matching unit 801 and the signal output terminal RFOUT. For example, one end of the third capacitor Cin is connected to the signal output terminal of the limiting unit 203, and the other end is connected to the gate of the amplifying transistor M0. One end of the fourth capacitor Cout is connected to the signal output terminal of the output matching unit 802, and the other end is connected to the FROUT terminal. The third capacitor Cin and the fourth capacitor Cout can prevent the DC signals in the previous and next stage circuits from having an adverse effect on the circuit, thereby improving the stability of the circuit. Similarly, in a limiting amplifier circuit including multiple stages of amplifying units, inter-stage capacitors can also be set between the multiple stages of amplifying units.

[0085] Figures 11A-11C FIG. 1 shows a schematic structural diagram of a clipping unit in an embodiment of the present application. Figures 11A-11CAs shown, the limiting unit 203 includes at least one limiting transistor, the gate of the limiting transistor is connected to the signal output terminal of the detection unit 202, the drain is connected to the signal input terminal RFIN of the limiting amplifier circuit, and the source is grounded;

[0086] The equivalent capacitance of the limiting transistor and the input matching unit are used together to match the impedance between the input signal and the control terminal of the amplifying unit 201 .

[0087] Specifically, continue to refer to Figures 11A-11B The limiting unit 203 includes a first limiting transistor M5 and a second limiting transistor M6 connected in series. The gate of the first limiting transistor M5 is connected to the signal output terminal of the detection unit 202 via a first resistor R1, and the drain is connected to the control terminal of the amplification unit 201 via a third capacitor Cin and the output matching unit 801. The source is connected to the drain of the second limiting transistor M6. The gate of the second limiting transistor M6 is connected to the signal output terminal of the detection unit 202 via a second resistor R2, and the source is grounded.

[0088] When a low-power signal is input, the detection voltage is low, and the first and second limiting transistors M5 and M6 are turned off. When a high-power signal is input, the detection voltage increases, turning on the first and second limiting transistors M5 and M6, forming a low-impedance RF path to ground. The high-power signal is released to ground by the limiting transistors, reducing the power reaching the gate of the amplifier transistor, thereby reducing the voltage swing at the amplifier transistor terminal and achieving a protective function.

[0089] Although the limiting unit can limit the signal power entering the receiving channel to prevent it from exceeding the processing capacity of the amplifying unit in the receiving channel, thereby protecting devices such as the amplifying transistor. However, the limiting unit itself will produce a certain amount of insertion loss during operation, which will cause the overall gain of the limiting amplifier circuit to decrease. In addition, the limiting unit itself will also introduce a certain amount of noise, which may also increase the noise level of the limiting amplifier circuit. Considering that when a low-power signal is input, the first limiting transistor M5 and the second limiting transistor M6 are turned off, which can be equivalent to a capacitor to the ground, the limiting unit 203 can also be used to match the impedance between the input signal and the control end of the amplifying unit 201. For example, continue to refer to Figures 11B-11C , compared to Figure 11B The limiting amplifier circuit shown is Figure 11C The limiting amplifier circuit shown in FIG uses the equivalent capacitance of the limiting unit 203 when receiving a low-power signal as a part of the input matching unit, which can reduce the need to set the first capacitor C1 and / or the second capacitor C2 ( Figure 11C(For example, the first capacitor is reduced.) In this embodiment of the present application, by integrating the limiter unit with the input matching unit, the equivalent capacitance of the limiter unit when receiving a low-power signal is used as part of the input matching unit, thereby reducing the number of matching electronic components and reducing additional losses. Of course, a passive matching circuit can also be provided within the limiter unit. When the limiter transistor is turned off, the limiter unit and the input matching unit are combined to reduce input losses.

[0090] It should be noted that the embodiment of the present application does not limit the specific number of the limiting transistors in the limiting unit, which can be adjusted according to actual conditions.

[0091] Although the detection unit and the limiter unit can limit the amplitude of the input signal power, after the limiter unit is turned on, a certain amount of power signal will still enter the receiving channel. This part of power may still damage the subsequent stage devices after being amplified by the first stage amplification unit. Figure 12 As shown, a multi-stage limiting unit can be set in the limiting amplifier circuit, and a limiting unit 203 can be configured for each of the first-stage amplifying unit 201a and the second-stage amplifying unit 201b. In this way, even if the first-stage limiting unit fails to completely limit the power, the subsequent stage limiting units can continue to play a role, further improving the reliability of protecting the subsequent stage devices. It should be noted that it is necessary to reasonably control the gain effect of the first-stage amplifying unit to avoid excessive gain resulting in excessive power output when a low-power signal is input. It is understandable that the limiting unit is used to match the impedance between the input signal and the control end of the amplifying unit, and it can also be used to Figure 12 Some matching electronic components in the inter-stage matching unit 802 in the limiting amplifier circuit are omitted.

[0092] In some embodiments, the detection unit includes a half detection circuit or a full detection circuit;

[0093] The full detection circuit is composed of two half detection circuits connected in reverse parallel.

[0094] The half detection circuit can be used to detect the positive half cycle or negative half cycle of the input signal. The full detection circuit can be used to detect the entire cycle of the input signal.

[0095] Figure 13A FIG. 1 shows a schematic diagram of the structure of a half-detection circuit in one embodiment of the present application. Figure 13A As shown, the half detection circuit includes:

[0096] The detection diode D1 and detection resistor R3 are connected in series.

[0097] One end of the detection diode D1 is connected to the signal input terminal RFIN of the limiting amplifier circuit, and the other end is connected to the control terminal of the limiting unit 203 and the detection resistor R3. The other end of the detection resistor R3 is grounded.

[0098] Specifically, the anode of the first detection diode D1 is connected to the RFIN terminal, and the cathode is grounded through the first detection resistor R3. The cathode of the first detection diode D1 serves as the signal output terminal of the detection unit 202, and outputs the detection voltage after half-wave detection of the high-power signal to the limiter unit 203.

[0099] Figure 13B FIG. 1 shows a schematic diagram of the structure of a full detection circuit in one embodiment of the present application. Figure 13B As shown, the detection unit 202 includes a second detection diode D2 and a third detection diode D3 connected in reverse parallel. The positive electrode of the second detection diode D2 is connected to the RFIN end through the fifth capacitor C5, and the negative electrode serves as the signal output end of the detection unit 202, outputting the detection voltage after full-wave detection of the high-power signal to the limiting unit 203.

[0100] In some embodiments, as Figure 14 As shown, the limiting amplifier circuit further includes a first DC amplifier A1, one end of which is connected to the signal output end of the detection unit 202, and the other end is connected to the control end of the limiting unit 203.

[0101] The first DC amplifier A1 is used to amplify the detection signal and control the on and off of the limiter unit 203 according to the amplified detection signal.

[0102] The detection voltage output by the detection unit 202 is positively correlated with the input signal power. This may result in a situation where the detection voltage is low, preventing the limiting transistor in the limiting unit 203 from fully conducting. However, the power of the amplifier transistor has already exceeded the reliability range. A first DC amplifier A1 can be added to the output of the detection unit 202 to amplify the low detection voltage, thereby controlling the limiting unit 203 to conduct in advance. Specifically, the signal output of the detection unit 202 is connected to the control terminals of the first-stage limiting unit and the second-stage limiting unit, respectively, via the first DC amplifier A1. Of course, in other embodiments, the first DC amplifier can be used to connect the signal output of the detection unit to the control terminals of some of the limiting units.

[0103] In some embodiments, as Figure 15A and Figure 15B As shown, the limiting amplifier circuit also includes:

[0104] Bias unit (such as Figure 15A The first bias unit 1501, the second bias unit 1502 or the third bias unit 1503 shown is connected to the gate of the amplifying transistor M1, M2 or M4 to provide a bias current or a bias voltage;

[0105] Switch (such as Figure 15A The first switch SW1 shown and Figure 15BThe second switch SW2 shown in FIG2 has a first end connected to the bias unit, a second end grounded, and a control end connected to the signal output end of the detection unit 202. The switch is used to control the on and off of the bias unit according to the detection signal.

[0106] The second DC amplifier A2 has one end connected to the signal output end of the detection unit 202 and the other end connected to the control end of the switch; the second DC amplifier A2 is used to amplify the detection signal and control the opening and closing of the bias unit according to the amplified detection signal.

[0107] The bias unit sets an appropriate bias current or voltage for the amplifier transistor, ensuring a stable current or voltage during operation. When the input signal power is high, the switch closes based on the detection voltage after amplification by the second DC amplifier. The amplifier transistor no longer amplifies the input signal, thus better protecting subsequent circuits.

[0108] Figure 15A FIG. 1 shows a schematic structural diagram of the first bias unit in an embodiment of the present application. Figure 15A As shown, the first bias unit 1501 includes a current source Ibias, a bias transistor M7 and a bias resistor Rg0;

[0109] The gate of the bias transistor M7 is connected to the control terminal of the amplifying unit through the first bias resistor Rg0, the drain is connected to the power supply terminal (VDD terminal) through the current source Ibias, and the source is grounded;

[0110] A first end of the first switch SW1 is connected to the drain of the bias transistor M7 , and a second end of the first switch SW1 is connected to the source of the bias transistor M7 .

[0111] The control terminal of the first switch SW1 is connected to the signal output terminal of the first DC amplifier A1. Based on the detection voltage amplified by the first DC amplifier A1, the first bias unit 1501 is turned on and off. When the input signal power is high, the first switch SW1 is closed, forming a low-impedance path. The amplifier transistor M1 no longer amplifies the signal, preventing subsequent circuitry from being damaged by the excessive input signal power.

[0112] Figure 15B FIG. 1 shows a schematic structural diagram of the second bias unit in an embodiment of the present application. Figure 15B As shown, the amplifying unit includes a first amplifying transistor M1 and a second amplifying transistor M2 connected in series;

[0113] The bias unit 1502 includes a bias input terminal (V1 terminal); the gate of the first amplifying transistor M1 is connected to the signal input terminal RFIN of the limiting amplifier circuit, the drain is connected to the source of the second amplifying transistor M2, and the source is grounded;

[0114] The gate of the second amplifying transistor M2 is connected to the bias input terminal (terminal V1 ), and the drain is connected to the signal output terminal RFOUT of the limiting amplifier circuit.

[0115] Continue to refer Figure 15B The second bias unit 1502 may further include a sixth resistor Rg1 and a sixth capacitor Cp1. One end of the sixth resistor Rg1 is connected to the V1 terminal, and the other end is connected to the gate of the second amplifying transistor M2. One end of the sixth capacitor Cp1 is connected to the gate of the second amplifying transistor M2, and the other end is grounded.

[0116] A first end of the second switch SW2 is connected to the bias input end (V1 end), and a second end thereof is grounded.

[0117] The control end of the switch SW2 is connected to the signal output end of the first DC amplifier A2, and controls the conduction and shutdown of the bias unit 1502 according to the detection voltage amplified by the second DC amplifier A2. Specifically, when the input signal power is large, the second switch SW2 is closed to form a low-resistance path, and the amplifier transistor M2 no longer has an amplification effect, so that the subsequent circuit will not be damaged due to excessive input signal power. Among them, one implementation method of the bias input terminal V1 can be referred to Figure 16 .like Figure 16 As shown, the bias unit further includes a digital power supply Vdig, a resistor string (including Rp0-Rpn) connected between the digital power supply Vdig and ground, and a third switch SW3. The first and second terminals of the third switch SW3 are connected to different positions in the resistor string to provide different operating points. The third switch SW3 provides different bias voltages to the gate of the second amplifying transistor M2 based on an enable signal provided by the EN terminal.

[0118] It should be noted that any amplifying transistor may be configured with a bias unit, and the specific implementation form of the bias unit may be any one of the above embodiments.

[0119] The limiting amplifier circuit provided in the embodiment of the present application, on the one hand, is provided with a detection unit and a limiting unit at the input end of the limiting amplifier circuit, and the working state of the limiting unit is controlled by the detection voltage output by the detection unit, thereby limiting the power level of the input signal and reducing the terminal voltage swing of the amplifying transistor; on the other hand, by providing a diode protection unit between the stages of the amplifying units, the response time of the limiting amplifier circuit is reduced, the possibility of the amplifying transistor being broken down is effectively reduced, and a higher protection capability is provided for the limiting amplifier circuit and subsequent circuits.

[0120] The present application also provides a radio frequency transceiver chip. Figure 17 As shown, the RF transceiver chip 300 includes a receiving channel 1701 and a transmitting channel 1702;

[0121] The receiving channel 1701 includes the aforementioned limiting amplifier circuit 200 .

[0122] Since the radio frequency transceiver chip includes the above-mentioned limiting amplifier circuit, it has similar beneficial effects as the limiting amplifier circuit, which will not be described in detail here.

[0123] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.

[0124] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A limiting amplifier circuit, characterized in that: include: One stage or multiple stages of amplifier units connected in series, each stage of the amplifier unit comprising at least one amplifier transistor; a detection unit connected to the signal input terminal of the limiting amplifier circuit, configured to detect the input signal received by the limiting amplifier circuit and output a detection signal, wherein the amplitude of the detection signal is positively correlated with the power of the input signal; At least one stage of the amplification unit is configured with a limiting unit, the signal input end of the limiting unit is respectively connected to the control end of the amplification unit and the signal input end of the limiting amplifier circuit, and the control end of the limiting unit is connected to the signal output end of the detection unit; the detection signal is used to control the opening and closing of the limiting unit; One or more diode protection units, at least one end of each diode protection unit is connected to the control end of the amplifying transistor, and each diode protection unit includes a forward diode string and / or a reverse diode string, and each diode string includes one diode or multiple diodes connected in series.

2. The limiting amplifier circuit according to claim 1, wherein: The limiting amplifier circuit further includes an input matching unit connected between the signal input terminal of the limiting unit and the control terminal of the amplifier unit; The input matching unit includes at least one of the following passive elements: a capacitor, an inductor, and a resistor. The input matching unit is used to match the impedance between the input signal and the control end of the amplifying unit; One end of the diode protection unit is connected to the gate of the amplifying transistor through the passive element; the other end is connected to the source of the amplifying transistor or is grounded.

3. The limiting amplifier circuit according to claim 2, wherein: The limiting unit includes at least one limiting transistor, the gate of the limiting transistor is connected to the signal output end of the detection unit, the drain is connected to the signal input end of the limiting amplifier circuit, and the source is grounded; The equivalent capacitance of the limiting transistor and the input matching unit are used together to match the impedance between the input signal and the control terminal of the amplifying unit.

4. The limiting amplifier circuit according to claim 1, wherein: The detection unit includes a half detection circuit and / or a full detection circuit; The full detection circuit is composed of two half detection circuits connected in reverse parallel.

5. The limiting amplifier circuit according to claim 4, characterized in that: The half detection circuit comprises: The detection diode and detection resistor are connected in series. One end of the detection diode is connected to the signal input end of the limiting amplifier circuit, and the other end is connected to the control end of the limiting unit and the detection resistor. The other end of the detection resistor is grounded.

6. The limiting amplifier circuit according to claim 1, wherein: The limiting amplifier circuit further includes a first DC amplifier, one end of which is connected to the signal output end of the detection unit and the other end is connected to the control end of the limiting unit. The first DC amplifier is used to amplify the detection signal and control the opening and closing of the limiter unit according to the amplified detection signal.

7. The limiting amplifier circuit according to claim 1, wherein: The limiting amplifier circuit also includes: a bias unit connected to the gate of the amplifying transistor and configured to provide a bias current or a bias voltage; a switch, wherein a first end is connected to the bias unit, a second end is grounded, and a control end is connected to the signal output end of the detection unit, and the switch is used to control the opening and closing of the bias unit according to the detection signal; A second DC amplifier has one end connected to the signal output end of the detection unit and the other end connected to the control end of the switch; the second DC amplifier is used to amplify the detection signal and control the opening and closing of the bias unit according to the amplified detection signal.

8. The limiting amplifier circuit according to claim 7, characterized in that: The bias unit includes a current source, a bias transistor and a bias resistor; The gate of the bias transistor is connected to the control terminal of the amplifying unit through the bias resistor, the drain is connected to the power supply terminal through the current source, and the source is grounded; A first end of the switch is connected to the drain of the bias transistor, and a second end of the switch is connected to the source of the bias transistor.

9. The limiting amplifier circuit according to claim 7, wherein: The amplifying unit includes a first amplifying transistor and a second amplifying transistor connected in series; The bias unit includes a bias input terminal; The gate of the first amplifying transistor is connected to the signal input terminal of the limiting amplifying circuit, the drain is connected to the source of the second amplifying transistor, and the source is grounded; The gate of the second amplifying transistor is connected to the bias input terminal, and the drain is connected to the signal output terminal of the limiting amplifier circuit; A first end of the switch is connected to the bias input end, and a second end of the switch is grounded.

10. A radio frequency transceiver chip, characterized in that: The radio frequency transceiver chip includes a receiving channel and a transmitting channel; The receiving channel includes the limiting amplifier circuit according to any one of claims 1 to 9.

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