Semiconductor device

Abstract

The utility model provides a semiconductor device, and relates to the technical field of semiconductors. The device comprises a substrate, a gate structure, a first epitaxial layer and a first metal silicide layer, the gate structure is convexly arranged on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer; the first epitaxial layer covers the top surface of the gate layer, the upper surface of the first epitaxial layer is a curved surface, and the first epitaxial layer is a Si layer; the first metal silicide layer covers the first epitaxial layer in a conformal manner, the upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer. According to the semiconductor device provided by the invention, the first epitaxial layer is formed on the substrate, so that the line width of the device is increased, the line width effect is overcome, the forming quality of the metal silicide layer is improved, and the overall performance of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device. Background Art

[0002] In the field of semiconductors, metal silicide can be used as a low-resistance contact layer between a metal layer and a semiconductor layer due to its low resistivity property, thereby improving the performance of the device and reducing the power consumption of the device.

[0003] Currently, with the miniaturization of the feature size of semiconductor devices, it has also had a greater impact on the material selection and formation quality of the metal silicide layer. For example, cobalt silicide material can be used to form a metal silicide layer suitable for high-temperature semiconductor processes. However, the cobalt silicide film has high requirements for the feature size of the device. When the feature size is small, with the increase of the process temperature, the cobalt silicide film will have agglomeration defects, resulting in film breakage and unusability. Existing devices with such feature sizes cannot form a metal silicide layer with good performance, small resistance value and complete film layer.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Utility Model

[0005] In view of this, a semiconductor device is provided. The semiconductor device has a relatively large line width, thereby reducing the line width effect of forming a metal silicide layer, and at the same time, it can reduce the thermal stability difference and avoid the generation of agglomeration defects during the subsequent formation process of the metal silicide layer.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or will be partially learned through the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a semiconductor device is provided, which includes:

[0008] A substrate;

[0009] A gate structure, the gate structure protruding on the surface of the substrate, the gate structure includes a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the side walls formed by the gate oxide layer and the gate layer together, and the top surface of the gate protection layer is not higher than the top surface of the gate layer;

[0010] A first epitaxial layer, the first epitaxial layer covering the top surface of the gate layer, and the upper surface of the first epitaxial layer is a curved surface, and the first epitaxial layer is a Si layer;

[0011] A first metal silicide layer, the first metal silicide layer conformally covering the first epitaxial layer, and an upper surface of the first metal silicide layer being a curved surface, the first metal silicide layer being CoSi 2 layer.

[0012] In an exemplary embodiment of the present disclosure, a top surface of the gate protection layer is lower than a top surface of the gate layer, the gate protection layer exposing sidewalls of a part of the gate layer, and the first epitaxial layer covering the top surface and the exposed sidewalls of the gate layer.

[0013] In an exemplary embodiment of the present disclosure, the top surface of the gate protection layer is flush with the top surface of the gate layer, the first epitaxial layer covering the top surface of the gate layer, and sidewalls of the first epitaxial layer being flush with sidewalls of the gate layer.

[0014] In an exemplary embodiment of the present disclosure, a middle part of the upper surface of the first metal silicide layer protrudes away from the substrate.

[0015] In an exemplary embodiment of the present disclosure, the device further includes a first source / drain and a second source / drain, the first source / drain and the second source / drain being respectively located on two sides of the gate structure, a surface of the first source / drain being flush with a surface of the substrate, and a surface of the second source / drain being flush with the surface of the substrate;

[0016] The device further includes a second epitaxial layer and a second metal silicide layer;

[0017] The second epitaxial layer covers at least one of the surface of the first source / drain or the surface of the second source / drain, and the second epitaxial layer protrudes from the surface of the substrate, an upper surface of the second epitaxial layer being a curved surface, the second epitaxial layer being a Si layer;

[0018] The second metal silicide layer conformally covers the surface of the second epitaxial layer, an upper surface of the second metal silicide layer being a curved surface, the second metal silicide layer being CoSi 2 layer.

[0019] In an exemplary embodiment of the present disclosure, a middle part of the upper surface of the second metal silicide layer protrudes away from the substrate.

[0020] In an exemplary embodiment of the present disclosure, the thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

[0021] In an exemplary embodiment of the present disclosure, the semiconductor device is selected from at least one of a PMOS device, an NMOS device, or a COMS device.

[0022] According to another aspect of the present disclosure, a semiconductor device is provided, which includes:

[0023] A substrate;

[0024] A gate structure, which protrudes on the surface of the substrate. The gate structure includes a gate oxide layer, a gate layer, and a gate protection layer. The gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewalls formed by the gate oxide layer and the gate layer together, and the top surface of the gate protection layer is not higher than the top surface of the gate layer;

[0025] A first metal silicide layer, which covers the top surface of the gate layer, and the upper surface of the first metal silicide layer is a curved surface. The first metal silicide layer is a CoSi 2 layer.

[0026] In an exemplary embodiment of the present disclosure, the top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes part of the sidewall of the gate layer, and the first metal silicide layer covers the top surface and the exposed sidewall of the gate layer.

[0027] In an exemplary embodiment of the present disclosure, the top surface of the gate protection layer is flush with the top surface of the gate layer, the first metal silicide layer covers the top surface of the gate layer, and the sidewall of the first metal silicide layer is flush with the sidewall of the gate layer.

[0028] In an exemplary embodiment of the present disclosure, the middle part of the upper surface of the first metal silicide layer protrudes away from the substrate.

[0029] In an exemplary embodiment of the present disclosure, the device further includes a first source / drain and a second source / drain, the first source / drain and the second source / drain are respectively located on both sides of the gate structure, the surface of the first source / drain is flush with the surface of the substrate, and the surface of the second source / drain is flush with the surface of the substrate;

[0030] The device further includes a second metal silicide layer, which covers at least one of the surface of the first source / drain or the surface of the second source / drain. The upper surface of the second metal silicide layer is a curved surface. The second metal silicide layer is a CoSi 2 layer.

[0031] In an exemplary embodiment of the present disclosure, the middle part of the upper surface of the second metal silicide layer protrudes away from the substrate.

[0032] In an exemplary embodiment of the present disclosure, the thicknesses of the first metal silicide layer and the second metal silicide layer are 6 nm to 14 nm.

[0033] In an exemplary embodiment of the present disclosure, the semiconductor device is selected from at least one of a PMOS device, an NMOS device, or a COMS device.

[0034] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0035] Providing a substrate;

[0036] Forming a gate structure protruding from the surface of the substrate, the gate structure including a gate oxide layer, a gate layer, and a gate protection layer, the gate oxide layer being formed on the surface of the substrate, the gate layer being formed on the surface of the gate oxide layer, the gate protection layer being formed on the sidewalls jointly formed by the gate layer and the gate oxide layer, and the top surface of the gate protection layer not being lower than the top surface of the gate layer;

[0037] Forming a first initial epitaxial layer protruding from the top surface of the gate layer, the upper surface of the first initial epitaxial layer being a curved surface, and the first initial epitaxial layer being a Si layer;

[0038] Forming a Co metal layer, the Co metal layer conformally covering the first initial epitaxial layer;

[0039] Performing a heat treatment on the Co metal layer to cause Co in the Co metal layer to diffuse into the first initial epitaxial layer, so that at least a part of the first initial epitaxial layer is converted into a first metal silicide layer, the first metal silicide layer being a CoSi 2 layer, and the remaining unconverted first initial epitaxial layer being a first epitaxial layer.

[0040] In an exemplary embodiment of the present disclosure, the performing a heat treatment on the Co metal layer to cause Co in the Co metal layer to diffuse into the first initial epitaxial layer includes: Co in the Co metal layer diffuses from the top surface to the bottom surface of the first initial epitaxial layer until the first initial epitaxial layer is completely converted into the first metal silicide layer.

[0041] In an exemplary embodiment of the present disclosure, before forming the first initial epitaxial layer protruding from the top surface of the gate layer, the method further includes:

[0042] Performing a laser annealing treatment on the gate layer to convert the gate layer into a single crystal structure.

[0043] In an exemplary embodiment of the present disclosure, the method further includes:

[0044] A first source / drain and a second source / drain are formed in the substrate, the first source / drain and the second source / drain are respectively located on two sides of the gate structure, the surface of the first source / drain is flush with the surface of the substrate, and the surface of the second source / drain is flush with the surface of the substrate;

[0045] A second initial epitaxial layer is formed, the second initial epitaxial layer covers at least one of the surface of the first source / drain or the surface of the second source / drain, and the second initial epitaxial layer protrudes from the surface of the substrate. The upper surface of the second initial epitaxial layer is a curved surface, and the second initial epitaxial layer is a Si layer.

[0046] In an exemplary embodiment of the present disclosure, forming the Co metal layer further includes: the Co metal layer conformally covers the second initial epitaxial layer.

[0047] In an exemplary embodiment of the present disclosure, heat-treating the Co metal layer further includes:

[0048] The Co metal layer is heat-treated to cause Co in the Co metal layer to diffuse into the second initial epitaxial layer, so that at least part of the second initial epitaxial layer is converted into a second metal silicide layer, and the second metal silicide layer is CoSi 2 layer, and the remaining unconverted second initial epitaxial layer is the second epitaxial layer.

[0049] In an exemplary embodiment of the present disclosure, heat-treating the Co metal layer to cause Co in the Co metal layer to diffuse into the second initial epitaxial layer includes: Co in the Co metal layer diffuses from the top surface to the bottom surface of the second initial epitaxial layer until the second initial epitaxial layer is completely converted into the second metal silicide layer.

[0050] In an exemplary embodiment of the present disclosure, the thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

[0051] In an exemplary embodiment of the present disclosure, the middle part of the upper surface of the first metal silicide layer or the second metal silicide layer protrudes away from the substrate.

[0052] In an exemplary embodiment of the present disclosure, forming a gate structure protruding from the surface of the substrate on the substrate includes:

[0053] A stacked structure is formed on the surface of the substrate, and the stacked structure sequentially includes an oxide material layer, a gate material layer, and an etch stop layer;

[0054] Patterning the stacked structure to form an initial gate structure;

[0055] Forming a gate protection layer, which conformally covers the surface of the initial gate structure and extends onto the surface of the substrate;

[0056] Simultaneously removing the gate protection layer and the etch stop layer located on the top surface of the initial gate structure to expose the surface of the gate layer.

[0057] In an exemplary embodiment of the present disclosure, the method further includes:

[0058] Continuing to remove the gate protection layer in a direction perpendicular to the substrate to expose the sidewalls of a part of the gate layer;

[0059] The first initial epitaxial layer simultaneously covers the top surface and the exposed sidewalls of the gate protection layer.

[0060] In an exemplary embodiment of the present disclosure, the heat treatment includes a first sub - heat treatment and a second sub - heat treatment. Heat - treating the Co metal layer includes:

[0061] Performing a first sub - heat treatment on the Co metal layer to cause Co in the Co metal layer to diffuse into the first initial epitaxial layer, so as to form a first sub - metal silicide layer in the first initial epitaxial layer.

[0062] In an exemplary embodiment of the present disclosure, after forming the first sub - metal silicide layer, the method further includes:

[0063] Performing a second sub - heat treatment on the first sub - metal silicide layer to cause at least part of the first sub - metal silicide layer to be converted into the first metal silicide layer, wherein the resistivity of the first metal silicide layer is less than the resistivity of the first sub - metal silicide layer.

[0064] In an exemplary embodiment of the present disclosure, after forming the first sub - metal silicide layer and before the first sub - metal silicide layer is converted into the first metal silicide layer, the method further includes: removing the remaining unreacted Co metal layer.

[0065] On the one hand, the present disclosure provides a semiconductor device. A first epitaxial layer is formed between the metal silicide layer and the gate layer, and the upper surface of the first epitaxial layer is a curved surface, thereby increasing the line width of the device. During the process of forming the metal silicide layer, the influence of the line width effect on the formation quality of the metal silicide film layer is overcome, the generation of agglomeration defects in the metal silicide film layer is avoided, and the formed metal silicide film layer has characteristics such as a smaller resistivity, which helps to reduce the contact resistance of the device; in addition, due to the presence of the first epitaxial layer, the difference in thermal stability caused by factors such as doping during the process of the device can be balanced, the thermal stability of the device is improved, and thus the overall performance of the device is enhanced.

[0066] On the other hand, the present disclosure provides a semiconductor device. A metal silicide layer is formed on the surface of the gate layer, and the upper surface of the metal silicide layer is a curved surface. Since this metal silicide layer is formed outside the gate structure and is different from directly doping the gate layer to form the metal silicide layer, such a device overcomes the line width effect, the formed metal silicide layer has a good formation quality, overcomes the agglomeration defects caused by the small line width, and thus enhances the overall performance of the device.

[0067] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0069] Figure 1 It is a flowchart of a manufacturing method of a semiconductor device in an exemplary embodiment of the present disclosure.

[0070] Figure 2 It is a schematic structural diagram of a device with a gate oxide layer and a gate layer in an exemplary embodiment of the present disclosure.

[0071] Figure 3 It is a schematic structural diagram of a device with a protective material layer in an exemplary embodiment of the present disclosure.

[0072] Figure 4 It is a schematic structural diagram of a gate layer after laser annealing in an exemplary embodiment of the present disclosure.

[0073] Figure 5 It is a schematic structural diagram of a device with a gate structure, a first source / drain, and a second source / drain in an exemplary embodiment of the present disclosure.

[0074] Figure 6 Schematic diagram of a device structure having a first initial epitaxial layer and a second initial epitaxial layer in an exemplary embodiment of the present disclosure.

[0075] Figure 7 Schematic diagram of a device structure having a first metal silicide layer and a second metal silicide layer in an exemplary embodiment of the present disclosure.

[0076] Figure 8 Schematic diagram of a device structure having a protective layer in an exemplary embodiment of the present disclosure.

[0077] Figure 9 Schematic diagram of a device structure having a via hole in an exemplary embodiment of the present disclosure.

[0078] Figure 10 Schematic diagram of another device structure having a first initial epitaxial layer and a second initial epitaxial layer in an exemplary embodiment of the present disclosure.

[0079] Figure 11 Schematic diagram of another device structure having a first metal silicide layer and a second metal silicide layer in an exemplary embodiment of the present disclosure.

[0080] Figure 12 Schematic diagram of another device structure having a protective layer in an exemplary embodiment of the present disclosure.

[0081] Figure 13 Schematic diagram of another device structure having a via hole in an exemplary embodiment of the present disclosure.

[0082] Among them, the reference numerals are explained as follows:

[0083] 100, substrate; 200, gate structure; 210, gate oxide layer; 220, gate layer; 230, gate protection layer; 310, first source / drain; 320, second source / drain; 410, first initial epitaxial layer; 411, first epitaxial layer; 420, second initial epitaxial layer; 421, second epitaxial layer; 510, first metal silicide layer; 520, second metal silicide layer; 610, etch stop layer; 620, protective material layer; 700, isolation structure; 800, protective layer; 900, via hole. Detailed implementation manners

[0084] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0085] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0086] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0087] In the related art, due to the increasing requirement for the integration degree of semiconductor devices, the size of semiconductor devices has been continuously miniaturized, which poses a huge challenge to semiconductor manufacturing processes. In particular, the change in the film layer performance inside the device brought about by the reduction of the feature size directly or indirectly changes the overall performance of the device. In a semiconductor structure, metal silicide is usually one of the indispensable film layers in semiconductor devices because it can reduce contact resistance, improve thermal stability, and improve device performance. When it contacts the source / drain or gate in the device, it can significantly reduce the resistance and improve the conductivity of the current, which is crucial for improving the overall electrical performance of the device; in addition, the metal silicide film layer has good thermal stability and is not easily decomposed or degraded in high-temperature processes, and also plays an important role in semiconductor manufacturing processes. Therefore, it is necessary to ensure the formation of a uniform and low-resistance metal silicide film layer.

[0088] Currently, the formation of metal silicide is usually achieved by depositing a metal layer on the surface of a silicon-based material and then performing a high-temperature annealing treatment, causing the metal to react with silicon to form metal silicide. During the formation of the metal silicide layer, there are multiple resistance phases. Under lower temperature conditions, the formed metal silicide layer is in a high-resistance state. By continuously increasing the temperature, silicon ions continue to diffuse into the high-resistance metal silicide film layer, causing the metal silicide to transform from a high-resistance state to a low-resistance state.

[0089] However, due to the reduction of the device's feature size, during the process of diffusing silicon ions in the silicon-based material into the already formed high-resistance metal silicide layer through a heat treatment process, the silicon ions are inhibited by the film layer boundary during diffusion and it is difficult to uniformly diffuse into the already formed metal silicide layer, resulting in the surface layer of the metal silicide layer still being in a high-resistance molecular structure, making it impossible to form a metal silicide film layer with a uniform structure and a small resistance value, thus reducing the performance of the metal silicide layer.

[0090] Based on this, the embodiments of the present disclosure provide a manufacturing method for a semiconductor device, as Figure 1 shown, this manufacturing method includes: step S10 to step S50.

[0091] Among them, step S10: Provide a substrate;

[0092] Step S20: Form a gate structure protruding from the surface of the substrate. The gate structure includes a gate oxide layer, a gate layer, and a gate protection layer. The gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the surface of the gate oxide layer, and the gate protection layer is formed on the sidewalls jointly formed by the gate layer and the gate oxide layer. The top surface of the gate protection layer is not lower than the top surface of the gate layer;

[0093] Step S30: Form a first initial epitaxial layer protruding from the top surface of the gate layer. The upper surface of the first initial epitaxial layer is a curved surface, and the first initial epitaxial layer is a Si layer;

[0094] Step S40: Form a Co metal layer, and the Co metal layer conformally covers the first initial epitaxial layer;

[0095] Step S50: Perform heat treatment on the Co metal layer to cause Co in the Co metal layer to diffuse into the first initial epitaxial layer, so that at least part of the first initial epitaxial layer is transformed into a first metal silicide layer. The first metal silicide layer is a CoSi 2 layer, and the remaining untransformed first initial epitaxial layer is the first epitaxial layer.

[0096] The manufacturing method of the semiconductor device provided by the present disclosure forms a first initial epitaxial layer on the surface of the gate layer, forms a metal layer on the first initial epitaxial layer, and converts at least part of the first initial epitaxial layer into a metal silicide layer through a diffusion doping process. By forming an epitaxial layer to increase the line width of the device, the influence of the line width effect on the formation quality of the metal silicide layer is overcome, the formation quality of the metal silicide layer is improved, thereby reducing the contact resistance within the device and improving the overall performance of the device.

[0097] The following will describe in detail each step of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure with reference to the accompanying drawings:

[0098] In the embodiment provided by the present disclosure, as Figure 2 shown, in step S10, a substrate 100 is provided.

[0099] Among them, the substrate 100 may be a silicon (Si) substrate, an SOI (Silicon On Insulator), etc., on the surface of which an epitaxial layer with a single-crystalline silicon structure can be directly formed. In some embodiments, the substrate 100 may also be other types of substrates, such as a sapphire (Al 2 O 3 ) substrate, an SOS (Silicon-on-Sapphire), or a GOI (Germanium On Insulator), and may also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs), etc. It should be noted that when the substrate 100 is other types of substrates, it can be used as a hetero-substrate, and a silicon buffer layer can be grown on it to provide a film layer basis for the subsequent growth of the epitaxial layer. The embodiment provided by the present disclosure takes the substrate 100 as a silicon (Si) substrate as an example for illustration. Of course, for other types of substrates, the corresponding deformation or improvement can be made to the embodiments of the present disclosure, which are all within the protection scope of the present disclosure.

[0100] In the embodiment provided by the present disclosure, in order to form a plurality of active regions on the substrate 100, the positions of a plurality of active regions on the substrate 100 can be predefined, and a plurality of isolation structures 700 are formed in the substrate 100 to divide the substrate 100 to form a plurality of active regions. Among them, as Figure 2 shown, the plurality of isolation structures 700 can be arranged at intervals on the substrate 100 and can be distributed in an array. Each isolation structure 700 can electrically isolate and insulate the semiconductor devices located in adjacent active regions, improving the electrical performance of the device. At least one semiconductor device is arranged in each active region, and the distribution form of the semiconductor devices and the distance between adjacent semiconductor structures can be selected according to the actual design requirements of the device.

[0101] A method for forming the isolation structure 700 on the substrate 100 may include: defining, by photolithography, a region for forming the isolation structure 700 on the substrate 100, and etching a shallow trench in the defined region by dry or wet etching; filling the shallow trench with an insulating material such as silicon oxide (SiO 2 ), to form an isolation film layer in the shallow trench; and then performing a planarization process to expose the surface of the substrate 100. By providing the isolation structure 700 on the substrate 100, current leakage between devices can be effectively prevented, and the performance and reliability of the devices can be improved.

[0102] In the embodiment provided by the present disclosure, in step S20, a gate structure 200 protruding from the surface of the substrate 100 is formed on the substrate 100. The gate structure 200 includes a gate oxide layer 210, a gate layer 220, and a gate protection layer 230. The gate oxide layer 210 is formed on the surface of the substrate 100, the gate layer 220 is formed on the surface of the gate oxide layer 210, the gate protection layer 230 is formed on the sidewalls jointly formed by the gate layer 220 and the gate oxide layer 210, and the top surface of the gate protection layer 230 is not lower than the top surface of the gate layer 220.

[0103] After forming the isolation structure 700 in the substrate 100, as Figure 5 shown, the manufacturing method further includes: forming a gate structure 200 protruding from the surface of the substrate 100 on the substrate 100. Specifically, the gate structure 200 includes a gate oxide layer 210, and the gate oxide layer 210 is formed on the surface of the substrate 100. Among them, the gate oxide layer 210 may be silicon dioxide (SiO 2 ) or other high-k dielectric material layers such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ) or yttrium oxide (Y 2 O 3 ) or one or more of them. It can be formed by one or more of methods such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Sputtering, Molecular Beam Epitaxy (MBE), or Plasma Enhanced CVD (PECVD). The specific formation method can be adaptively selected and adjusted according to characteristics such as the material of the gate oxide layer 210.

[0104] The gate structure 200 further includes a gate layer 220. As Figure 2 shown, the gate layer 220 is formed on the surface of the gate oxide layer 210. Among them, the gate layer 220 is formed on the surface of the gate oxide layer 210. The gate layer 220 can be polysilicon (poly) or other metal materials, such as one or more of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), cobalt (Co), nickel (Ni), ruthenium (Ru), or iridium (Ir). It can be formed by one or a combination of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALE), sputtering, photolithography, or etching, and can be selected according to the characteristics of the material of the gate layer 220. In the embodiments provided in the present disclosure, the gate layer 220 is taken as an example of polysilicon for illustration. However, it should be noted that the gate layer 220 of the present disclosure can also be made of materials other than polysilicon. If the gate layer 220 is other metal materials, in order to form an epitaxial layer on the gate layer 220 in subsequent processes, a buffer layer can be formed on the exposed top surface of the gate layer 220 to provide a structural basis for the growth of the subsequent epitaxial layer.

[0105] The gate structure 200 further includes a gate protection layer 230. The gate protection layer 230 is formed on the sidewalls formed by the gate layer 220 and the gate oxide layer 210 together. Among them, the gate protection layer 230 can include at least one insulating layer and at least one passivation layer formed in sequence along the sidewall direction away from the gate layer 220. Of course, according to the actual structural requirements of the device, the gate protection layer 230 can also be formed by one insulating layer or one passivation layer. If the number of insulating layers and passivation layers is multiple, the multiple insulating layers and multiple passivation layers are alternately distributed on the sidewalls of the gate layer 220 in sequence along the sidewall direction away from the gate layer 220, and the film layer farthest from the gate sidewall can be a passivation layer. In the embodiments of the present disclosure, the gate protection layer 230 is taken as an example of a multi-layer structure for illustration.

[0106] Among them, the insulating layer in the gate protection layer 230 can be silicon dioxide (SiO 2 ) or other high-k material layers, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), or yttrium oxide (Y 2 O 3) or one or more of them. It can be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The specific formation method can be adaptively selected and adjusted according to characteristics such as the material of the insulating layer.

[0107] The passivation layer can be made of materials such as silicon nitride (Si 3 N 4 ). It can be formed by methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Of course, the material of the passivation layer can also be formed by other materials and process formation methods according to the actual structural requirements of the device.

[0108] In some embodiments, forming a gate structure 200 protruding from the surface of the substrate 100 on the substrate 100 may include: step S201 to step S204.

[0109] Among them, step S201: forming a stacked structure on the surface of the substrate 100, the stacked structure sequentially includes an oxide material layer, a gate material layer, and an etch stop layer 610;

[0110] Step S202: performing a patterning process on the stacked structure to form an initial gate structure 200;

[0111] Step S203: forming a gate protection layer 230, the gate protection layer 230 conformally covers the surface of the initial gate structure 200 and extends to the surface of the substrate 100;

[0112] Step S204: simultaneously removing the gate protection layer 230 and the etch stop layer 610 located on the top surface of the initial gate structure 200 to expose the surface of the gate layer 220.

[0113] Among them, in order to facilitate the formation of subsequent film layers on the surface of the gate layer 220, the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. Such as Figure 5As shown, when the top surface of the gate protection layer 230 is lower than the top surface of the gate layer 220, after the surface of the gate layer 220 is exposed, in order to further increase the line width of the gate and provide a device structure foundation with better structure for the formation of subsequent film layers, the method may further include: continuing to remove the gate protection layer 230 in a direction perpendicular to the substrate 100 to expose part of the sidewalls of the gate layer 220; the first initial epitaxial layer 410 covers both the top surface of the gate protection layer 230 and the exposed sidewalls. By removing the gate protection layer 230 in a direction close to the substrate 100 to expose part of the sidewalls of the gate layer 220 close to the top surface, the exposed sidewalls can jointly form the process line width of the gate structure 200 with the top surface, so as to increase the line width of the gate structure 200 and provide a larger line width for the formation of the metal silicide layer.

[0114] It should be noted that since the gate protection layer 230 can be formed by alternating multiple layers of passivation layers and multiple layers of insulating layers, and their etching selectivity ratios are different under the same process conditions, it is difficult to ensure that the sizes of the insulating layer and the passivation layer removed are the same or approximately the same through the same process. Therefore, a two-step or more-step processing process can be adopted to separately remove the insulating layer and the passivation layer to achieve the purpose of exposing the sidewalls of the gate layer 220. The specific etching process can be selected according to the actual process requirements. Among them, the height of the exposed sidewalls of the gate layer 220 can be 10% - 30% of the overall height of the gate layer 220, which not only ensures the insulation and isolation functions of the gate protection layer 230, but also ensures that the gate structure 200 achieves the purpose of increased line width, so as to provide a device foundation for the formation of subsequent film layers.

[0115] In the embodiment provided by the present disclosure, after the gate structure 200 is formed on the substrate 100, the manufacturing method may further include: forming a first source-drain 310 and a second source-drain 320 in the substrate 100. The first source-drain 310 and the second source-drain 320 are respectively located on both sides of the gate structure 200. The surface of the first source-drain 310 is flush with the surface of the substrate 100, and the surface of the second source-drain 320 is flush with the surface of the substrate 100.

[0116] Among them, the single semiconductor device composed of the gate structure 200, the first source / drain 310, and the second source / drain 320 can be any one selected from NMOS (N-type Metal-Oxide-Semiconductor Field-Effect Transistor) devices, PMOS (P-type Metal-Oxide-Semiconductor Field-Effect Transistor) devices, or CMOS (Complementary Metal-Oxide-Semiconductor) devices.

[0117] When the single semiconductor device is an NMOS device, the substrate 100 can be a P-type silicon substrate, and an N-type well or N-type isolation region is formed on the substrate 100; two high-concentration N-type regions are formed in the N-type well through ion implantation or diffusion processes to form the source or drain.

[0118] When the single semiconductor device is a PMOS device, the substrate 100 can be a P-type silicon substrate, and an epitaxial layer is formed on the substrate 100. The epitaxial layer can be N-type; an N-type well or N-type isolation region is formed in the epitaxial layer through ion implantation or diffusion processes; two high-concentration P-type regions are formed in the N-type well through ion implantation or diffusion processes to form the source or drain. In the present disclosure, it can be understood that the substrate 100 proposed herein includes the epitaxial layer required for forming a PMOS device.

[0119] Of course, the single semiconductor device can also be a CMOS device. Its formation method can be analogous to the formation methods of PMOS or NMOS, or an adaptive deformation of the combination of the above two formation methods can be used to obtain the formation process of the CMOS device, which will not be elaborated here. The embodiments provided in the present disclosure are described by taking the single semiconductor device as a CMOS device as an example. However, it should be noted that when the single semiconductor device has different types of device structures, they can all be formed by the manufacturing method provided in the present disclosure through adaptive deformation.

[0120] The inventor found that in the above device structure, the line width of the formed device is fixed. Especially for existing small line width (line width less than 40 nm) devices, it is difficult to achieve the purpose of increasing the top line width of the device through etching processes and the like, which severely limits the subsequent processes. Especially for the formed metal silicide film layer, due to the line width effect, agglomeration defects will occur, affecting the contact resistance and performance of the device.

[0121] In the embodiment provided by the present disclosure, in step S30, a first initial epitaxial layer 410 protruding from the top surface of the gate layer 220 is formed. The upper surface of the first initial epitaxial layer 410 is a curved surface, and the first initial epitaxial layer 410 is a Si layer.

[0122] Wherein, before forming the first initial epitaxial layer 410, as Figure 4 shown, the method further includes: performing a laser annealing treatment on the gate layer 220 to convert the gate layer 220 into a single crystal structure. Since the gate layer 220 is made of polycrystalline silicon material, it is difficult to grow an epitaxial layer when using the epitaxial process. Therefore, it is necessary to perform a laser annealing treatment on the gate layer 220 to convert the polycrystalline silicon structure of the gate layer 220 into a single crystal structure, so as to facilitate the subsequent formation of an epitaxial layer on its surface.

[0123] Before performing the laser degradation treatment on the gate layer 220, as Figure 3 shown, the method further includes: forming a protective material layer 620, and the protective material layer 620 conformally covers the surface of the gate layer 220 and extends to the surface of the substrate 100. The protective material layer 620 can protect the gate layer 220 and can also control the heat distribution in the laser annealing treatment to ensure that heat can be evenly transferred into the gate layer 220, avoiding damage to the gate layer 220 caused by thermal non-uniformity.

[0124] Wherein, the protective material layer 620 can be made of materials such as silicon nitride (Si 3 N 4 ), etc., and it can be formed by methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Of course, the material of the protective material layer 620 can also be formed by other materials and process formation methods according to the actual structure requirements of the device.

[0125] As Figure 6 shown, the formation of the first initial epitaxial layer 410 on the top surface of the gate layer 220 includes: when the top surface of the gate protective layer 230 is flush with the top surface of the gate layer 220, the first initial epitaxial layer 410 is formed on the top surface of the gate layer 220; when the top surface of the gate protective layer 230 is lower than the top surface of the gate layer 220, the first initial epitaxial layer 410 is formed on the top surface of the gate layer 220 and its exposed sidewalls.

[0126] Among them, the first initial epitaxial layer 410 can be formed on the gate layer 220 through an epitaxial process. For example, the first initial epitaxial layer 410 composed of single-crystalline silicon can be formed on the surface of the gate layer 220 by methods such as chemical vapor deposition (CVD). The thickness of the first initial epitaxial layer 410 can be 6 nm to 14 nm. For example, it can be 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, etc. The thickness of the first initial epitaxial layer 410 can refer to one of the maximum thickness value, minimum thickness value, or average thickness value between the upper surface and the lower surface of the first initial epitaxial layer 410. When measuring and comparing the thickness value of the first initial epitaxial layer 410, one of the above values can be used as a standard, but other film layers for comparison also need to be based on the same standard. Among them, the upper surface and the lower surface respectively refer to the surface of the film layer on the side away from the substrate 100 and the surface on the side close to the substrate 100. The up and down do not limit the specific position of the film layer.

[0127] In some embodiments, the upper surface of the first initial epitaxial layer 410 is a curved surface, which can be a concave surface or a convex surface relative to the surface of the substrate 100. In the present disclosure, the middle part of the upper surface of the first initial epitaxial layer 410 protrudes in the direction away from the substrate 100, that is, the upper surface of the first initial epitaxial layer 410 is a convex surface relative to the surface of the substrate 100, so as to increase the surface area of the upper surface of the first initial epitaxial layer 410 and increase the line width of the device gate structure 200. Of course, different process parameters can also be set to control the upper surface of the first initial epitaxial layer 410 to be a concave surface relative to the surface of the substrate 100, and the purpose of increasing the device line width can also be achieved.

[0128] When forming the first initial epitaxial layer 410, as Figure 6 shown, the method may further include: forming a second initial epitaxial layer 420, the second initial epitaxial layer 420 covering at least one of the surfaces of the first source-drain 310 or the second source-drain 320, and the second initial epitaxial layer 420 protruding from the surface of the substrate 100. The upper surface of the second initial epitaxial layer 420 is a curved surface, and the second initial epitaxial layer 420 is an Si layer. The first initial epitaxial layer 410 and the second initial epitaxial layer 420 can be formed simultaneously by an epitaxial process, and the two can be formed in the same process step to save process steps and simplify the process. Of course, according to process requirements, the two can also be formed step by step. The process and thickness used to form the second initial epitaxial layer 420 can be the same as or similar to those of the first initial epitaxial layer 410, which will not be elaborated here.

[0129] The second initial epitaxial layer 420 covers at least one of the surfaces of the first source / drain 310 or the second source / drain 320. For example, the second initial epitaxial layer 420 may cover the surfaces of both the first source / drain 310 and the second source / drain 320; or the second initial epitaxial layer 420 may only cover the surface of the first source / drain 310; or the second initial epitaxial layer 420 may only cover the surface of the second source / drain 320. To simultaneously increase the line widths of the first source / drain 310 and the second source / drain 320, the second initial epitaxial layer 420 may cover the surfaces of both the first source / drain 310 and the second source / drain 320.

[0130] The second initial epitaxial layer 420 protrudes from the surface of the substrate 100. The upper surface of the second initial epitaxial layer 420 is a curved surface, and the second initial epitaxial layer 420 is a Si layer. Among them, if the first source / drain 310 and the second source / drain 320 are the source / drains of an NMOS device, the second initial epitaxial layer 420 may cover the first source / drain 310 and the second source / drain 320, and the edges of the second initial epitaxial layer 420 may be aligned with the edge positions of the first source / drain 310 and the second source / drain 320; if the first source / drain 310 and the second source / drain 320 are the source / drains of a PMOS device, the second initial epitaxial layer 420 may cover the first source / drain 310 and the second source / drain 320 and extend to the surface of the substrate 100, and the orthographic projection of the second initial epitaxial layer 420 on a certain cross-section of the substrate 100 covers the orthographic projections of the first source / drain 310 and the second source / drain 320 on the same cross-section.

[0131] In some embodiments, the upper surface of the second initial epitaxial layer 420 is a curved surface, which may be a concave surface or a convex surface relative to the surface of the substrate 100. In the present disclosure, the middle part of the upper surface of the second initial epitaxial layer 420 protrudes away from the substrate 100, that is, the upper surface of the second initial epitaxial layer 420 is a convex surface relative to the surface of the substrate 100, so as to increase the surface area of the upper surface of the second initial epitaxial layer 420 to increase the line widths of the source and drain of the device. Of course, different process parameters may also be set to control the upper surface of the second initial epitaxial layer 420 to be a concave surface relative to the surface of the substrate 100, and the purpose of increasing the line widths of the source and drain of the device can also be achieved.

[0132] The shapes of the first initial epitaxial layer 410 and the second initial epitaxial layer 420 may be the same or different according to process requirements, but for process convenience, the same shape is usually selected, such as both being convex surfaces relative to the surface of the substrate 100.

[0133] In the embodiments provided by the present disclosure, in step S40, a Co metal layer is formed, and the Co metal layer conformally covers the first initial epitaxial layer 410. During the formation of the metal silicide layer in the device, due to CoSi 2It has the molecular structure characteristics that can form a low-resistance state in high-temperature processes and is commonly used to prepare the metal silicide layer in semiconductor devices to reduce the contact resistance of the devices and improve the overall performance of the devices. CoSi 2 The formation of CoSi can be achieved by controlling the process temperature to enable the mutual diffusion of the metals in the Si film layer and the Co film layer and controlling their molecular structure to form a low-resistance state film layer structure.

[0134] In some embodiments, the Co metal layer can conformally cover the first initial epitaxial layer 410 and the second initial epitaxial layer 420 at the same time. The thickness of the Co metal layer can be 5 nm to 20 nm. For example, the thickness can be 5 nm, 10 nm, 15 nm, 20 nm, etc. The Co metal layer can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other methods. The specific formation process and parameters of the Co metal layer can be selected according to the actual process requirements.

[0135] To avoid the influence of external impurities on the Co metal layer, especially to avoid the oxidation of the Co metal layer by oxygen, after the formation of the Co metal layer, the method can further include: forming a capping film that conformally covers the surface of the Co metal layer. Among them, the capping film can be one or more of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), etc. It can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), etc. The specific material and formation process of the capping film can be adaptively selected and adjusted according to the device process design. Taking the capping film as titanium nitride (TiN) as an example, the thickness of the capping film can be 5 nm to 15 nm. For example, the thickness of the capping film can be 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, etc.

[0136] In the embodiments provided by the present disclosure, as Figure 7 shown, in step S50, the Co metal layer is heat-treated to diffuse the Co in the Co metal layer into the first initial epitaxial layer 410, so that at least part of the first initial epitaxial layer 410 is converted into the first metal silicide layer 510, and the first metal silicide layer 510 is the CoSi 2 layer.

[0137] If the device further includes a second initial epitaxial layer 420, as Figure 7 shown, the method further includes: heat-treating the Co metal layer to diffuse the Co in the Co metal layer into the second initial epitaxial layer 420, so that at least part of the second initial epitaxial layer 420 is converted into the second metal silicide layer 520, and the second metal silicide layer 520 is the CoSi 2 layer.

[0138] Through the above heat treatment process, CoSi is formed in the regions near the top of the first initial epitaxial layer 410 and the second initial epitaxial layer 420. 2 layer. Since this CoSi 2 layer is formed in the first initial epitaxial layer 410 and the second initial epitaxial layer 420, it has larger lines, overcomes the agglomeration defects caused by the line width effect, can reduce the contact resistance of the device. In addition, due to the formation of the first initial epitaxial layer 410 and the second initial epitaxial layer 420, the difference in thermal stability inside the device can be effectively balanced, further improving the formation quality of the device and enhancing the performance of the device.

[0139] In some embodiments, the Co metal layer is heat-treated to cause Co in the Co metal layer to diffuse into the first initial epitaxial layer 410, as Figure 10 and Figure 11 shown, including: Co in the Co metal layer diffuses from the top surface to the bottom surface of the first initial epitaxial layer 410 until the first initial epitaxial layer 410 is completely converted into the first metal silicide layer 510. By completely converting the first initial epitaxial layer 410 into the first metal silicide layer 510, the thickness of the first initial epitaxial layer 410 is reduced, the resistance of the device can be lowered, and at the same time, since the thickness of the first metal silicide layer 510 is increased, the contact resistance of the device is further reduced.

[0140] In some embodiments, the Co metal layer is heat-treated to cause Co in the Co metal layer to diffuse into the second initial epitaxial layer 420, as Figure 10 and Figure 11 shown, including: Co in the Co metal layer diffuses from the top surface to the bottom surface of the second initial epitaxial layer 420 until the second initial epitaxial layer 420 is completely converted into the second metal silicide layer 520. By completely converting the second initial epitaxial layer 420 into the second metal silicide layer 520, the thickness of the second initial epitaxial layer 420 is reduced, the resistance of the device can be lowered, and at the same time, since the thickness of the second metal silicide layer 520 is increased, the contact resistance of the device is further reduced.

[0141] The conversion processes of the first initial epitaxial layer 410 and the second initial epitaxial layer 420 in the above two embodiments can be carried out simultaneously to save process steps and improve process convenience.

[0142] It should be noted that during the heat treatment of the Co metal layer to form the first metal silicide, due to the uncertainty of the diffusivity of the Co metal, a first metal silicide layer 510 will also be formed in the top region of the gate layer 220. The first metal silicide layer 510 formed in the gate layer 220 is included in the first metal silicide layer 510 provided in the present disclosure, and it also has the function of reducing the contact resistance and improving the device performance.

[0143] During the heat treatment of the Co metal layer to form the second metal silicide, due to the uncertainty of the diffusivity of the Co metal, a second metal silicide layer 520 will also be formed in the top regions of the first source / drain 310 and the second source / drain 320. The second metal silicide layer 520 formed in the first source / drain 310 and the second source / drain 320 is included in the second metal silicide layer 520 provided by the present disclosure, and it also has the effect of reducing the contact resistance and improving the device performance.

[0144] In the embodiment provided by the present disclosure, since the CoSi 2 layer is formed by the mutual diffusion doping between Si and Co, at different heat treatment temperatures, the molecular morphology of the formed metal silicide layer is different, resulting in different resistance values. In order to obtain a low-resistance state of CoSi 2 layer, the heat treatment may include a first sub-heat treatment and a second sub-heat treatment. The heat treatment of the Co metal layer includes: performing a first sub-heat treatment on the Co metal layer to cause the Co in the Co metal layer to diffuse into the first initial epitaxial layer 410, so as to form a first sub-metal silicide layer in the first initial epitaxial layer 410.

[0145] Wherein, the first sub-metal silicide layer may include cobalt disilicide (Co 2 Si) and cobalt silicide (CoSi). The thickness of the first sub-metal silicide layer may be 6 nm to 14 nm. For example, it may be a thickness such as 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm or 14 nm. According to the different ratios between cobalt disilicide (Co 2 Si) and cobalt silicide (CoSi) in the first sub-metal silicide layer, the thickness of the formed first sub-metal silicide layer may be different. In this embodiment, the thickness of the first sub-metal silicide layer refers to the dimension of the film layer in the direction perpendicular to the substrate 100.

[0146] The first sub-heat treatment can be divided into two steps. Among them, the first step of the first sub-heat treatment includes: at a temperature of 250 °C to 410 °C, using the cobalt in the Co metal layer as a diffusion source, so that cobalt is doped into the first initial epitaxial layer 410 and the second initial epitaxial layer 420, and cobalt disilicide (Co 2 Si) is formed in the first initial epitaxial layer 410 and the second initial epitaxial layer 420. Especially at the positions close to the surface of the first initial epitaxial layer 410 and the second initial epitaxial layer 420, the concentration of cobalt ions is relatively high, and more cobalt disilicide (Co 2 Si) is formed.

[0147] The second step of the first sub-thermal treatment includes: at a temperature of 410°C to 700°C, cobalt continues to act as a diffusion source and further diffuses into the first initial epitaxial layer 410 and the second initial epitaxial layer 420, forming cobalt silicide (CoSi) in the first initial epitaxial layer 410 and the second initial epitaxial layer 420. Among them, after the heat treatment, cobalt disilicide (Co 2 Si) and cobalt silicide (CoSi) can coexist in the first sub-metal silicide layer. The resistivity of both cobalt disilicide (Co 2 Si) and cobalt silicide (CoSi) is relatively high, and the resistance value of the formed first sub-metal silicide layer is also relatively large. The temperature ranges in the first step and the second step of the above first sub-thermal treatment are only shown as exemplary embodiments. In the actual heat treatment process, the above temperature ranges do not have strict boundaries and can be adjusted adaptively according to actual process requirements.

[0148] In order to further form a metal silicide film layer with a smaller resistance value, after forming the first sub-metal silicide layer, the method further includes: performing a second sub-thermal treatment on the first sub-metal silicide layer to convert at least part of the first sub-metal silicide layer into a first metal silicide layer 510, wherein the resistivity of the first metal silicide layer 510 is less than that of the first sub-metal silicide layer.

[0149] As the heat treatment temperature further increases, such as when the temperature rises above 700°C, at this time, silicon in the device acts as a diffusion source and diffuses into the first sub-metal silicide layer. The formed cobalt disilicide (Co 2 Si) and cobalt silicide (CoSi) continue to combine with silicon to form cobalt disilicide (CoSi 2 ). The resistivity of cobalt disilicide (CoSi 2 ) is smaller than that of both cobalt disilicide (Co 2 Si) and cobalt silicide (CoSi). The resistance value of cobalt disilicide (CoSi 2 ) is smaller, which can effectively reduce the contact resistance and improve the overall electrical performance of the device.

[0150] Among them, the temperature of the second sub-thermal treatment can be greater than 700°C, such as 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C or even higher temperatures. The time of the second sub-thermal treatment can also adopt different treatment times according to the different temperatures within the temperature conditions. The time of the second sub-thermal treatment can be in the nanosecond to millisecond range. For example, under higher temperature conditions, the treatment time can be appropriately shortened; under lower temperature conditions, the treatment time can be appropriately increased.

[0151] In some embodiments, after forming the first sub-metal silicide layer and before the first sub-metal silicide layer is transformed into the first metal silicide layer 510, the method further includes: removing the remaining unreacted Co metal layer. Among them, the remaining unreacted Co metal layer can be removed by methods such as wet chemical etching, dry etching, mechanical polishing, laser etching, electrochemical etching, etc., and the specific process can be selected according to the actual process design requirements.

[0152] Before removing the remaining unreacted Co metal layer, the method further includes: removing the capping film. Taking the capping film as TiN as an example, methods such as wet etching, dry etching, chemical mechanical polishing or laser lift-off can be used, and the specific method can be selected according to the actual process design requirements.

[0153] In some embodiments, the thickness of the first metal silicide layer 510 and the second metal silicide layer 520 can be 6 nm to 14 nm, such as 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm or 14 nm, etc. The thickness of the first metal silicide layer 510 and the second metal silicide layer 520 can be adaptively selected and adjusted according to process requirements, and the thicknesses of the two can be the same or different.

[0154] In some embodiments, the middle part of the upper surface of the first metal silicide layer 510 or the second metal silicide layer 520 protrudes away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 or the second metal silicide layer 520 is a convex surface relative to the surface of the substrate 100. This structural shape facilitates process manufacturing, simplifies the process, and at the same time achieves the purpose of increasing the device line width.

[0155] In some embodiments, after forming the first metal silicide layer 510 and the second metal silicide layer 520, as Figure 8 and Figure 12 shown, the method further includes: forming a protective layer 800 covering the surface of the device structure. The protective layer 800 can protect the device structure located thereunder. The protective layer 800 can be prepared from materials such as silicon nitride (Si 3 N 4 ) and can be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).

[0156] In some embodiments, after forming the protective layer 800, multiple stacked film layers may be formed on the device with the protective layer 800, and then through processes such as etching, multiple connection holes 900 are etched in the stacked film layers, as Figure 9 and Figure 13 shown. The connection holes 900 can be filled with a conductive material, and through the connection holes 900, the device can be electrically connected to the outside. Of course, the semiconductor device provided by the present disclosure may also have other film layers and structures not shown, such as the structures and film layers necessary for the semiconductor device to achieve its conventional functions. Although these structures are not specifically described herein, it should be understood that the semiconductor device in the present disclosure also includes other film layers and structures required for achieving its conventional functions.

[0157] The manufacturing method of the semiconductor device provided by the present disclosure forms a first initial epitaxial layer 410 on the surface of the gate layer 220, forms a Co metal layer on the first initial epitaxial layer 410, and through a diffusion doping process, at least part of the first initial epitaxial layer 410 is converted into a metal silicide layer. By forming an epitaxial layer to increase the line width of the device, the influence of the line width effect on the formation quality of the metal silicide layer is overcome, the formation quality of the metal silicide layer is improved, thereby reducing the contact resistance in the device and improving the overall performance of the device.

[0158] It should be noted that although the steps of the manufacturing method of the semiconductor device in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be executed in that specific order, or that all the shown steps must be executed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0159] The embodiments of the present disclosure provide a semiconductor device, as Figure 9 shown. The device includes: a substrate 100, a gate structure 200, a first epitaxial layer 411, and a first metal silicide layer 510.

[0160] Among them, the gate structure 200 protrudes from the surface of the substrate 100. The gate structure 200 includes a gate oxide layer 210, a gate layer 220, and a gate protection layer 230. The gate oxide layer 210 is formed on the surface of the substrate 100. The gate layer 220 is formed on the gate oxide layer 210. The gate protection layer 230 covers the sidewalls formed by the gate oxide layer 210 and the gate layer 220 together, and the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. The first epitaxial layer 411 covers the top surface of the gate layer 220, and the upper surface of the first epitaxial layer 411 is a curved surface. The first epitaxial layer 411 is a Si layer. The first metal silicide layer 510 conformally covers the first epitaxial layer 411, and the upper surface of the first metal silicide layer 510 is a curved surface. The first metal silicide layer 510 is CoSi 2 layer.

[0161] In the semiconductor device provided by the present disclosure, a first epitaxial layer 411 is formed between the metal silicide layer and the gate layer 220, and the upper surface of the first epitaxial layer 411 is a curved surface, thereby increasing the line width of the device. During the process of forming the metal silicide layer, the influence of the line width effect on the formation quality of the metal silicide film layer is overcome, the generation of agglomeration defects in the metal silicide film layer is avoided, and the formed metal silicide film layer has characteristics such as a smaller resistivity, which helps to reduce the contact resistance of the device. In addition, due to the presence of the first epitaxial layer 411, the difference in thermal stability caused by factors such as doping during the process of the device can be balanced, the thermal stability of the device is improved, and thus the overall performance of the device is enhanced.

[0162] Next, each part of the semiconductor device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings:

[0163] The semiconductor device provided by the present disclosure can be manufactured by the above manufacturing method.

[0164] Among them, the substrate 100 can be a silicon (Si) substrate, a SOI (Silicon On Insulator), etc., and a single-crystalline silicon structure epitaxial layer can be directly formed on its surface. In some embodiments, the substrate 100 can also be other types of substrates, such as sapphire (Al 2 O 3The substrate may be a silicon (Si) substrate, an SOS (Silicon-on-Sapphire), or a GOI (Germanium On Insulator), and may also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs), etc. It should be noted that when the substrate 100 is other types of substrates, it can be used as a hetero-substrate, and a silicon buffer layer can be grown thereon to provide a film layer basis for the subsequent growth of the epitaxial layer. The embodiments provided in the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates, the corresponding deformations or improvements can be made to the embodiments of the present disclosure, which are all within the protection scope of the present disclosure.

[0165] In some embodiments, the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. Among them, the top surface of the gate protection layer 230 may be lower than the top surface of the gate layer 220, and the gate protection layer 230 exposes part of the sidewall of the gate layer 220. The first epitaxial layer 411 covers the top surface and the exposed sidewall of the gate layer 220. The exposed sidewall may jointly form the process line width of the gate structure 200 with the top surface to increase the line width of the gate structure 200 and provide a larger line width for the formation of the metal silicide layer. Among them, the top surface of the gate protection layer 230 may be flush with the top surface of the gate layer 220. The first epitaxial layer 411 covers the top surface of the gate layer 220, and the sidewall of the first epitaxial layer 411 is flush with the sidewall of the gate layer 220.

[0166] Among them, the exposed height of the sidewall of the gate layer 220 may be 10% - 30% of the overall height of the gate layer 220, which not only ensures the insulation and isolation effects of the gate protection layer 230 but also ensures that the gate structure 200 achieves the purpose of increasing the line width, providing a device basis for the formation of subsequent film layers.

[0167] In some embodiments, the upper surface of the first epitaxial layer 411 is a convex surface or a concave surface relative to the surface of the substrate 100, and such surfaces can both achieve the purpose of increasing the line width of the device gate structure 200. Among them, the first metal silicide layer 510 is conformally formed on the first epitaxial layer 411. When the first epitaxial layer 411 is a convex surface, the middle part of the upper surface of the first metal silicide layer 510 protrudes away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is a convex surface relative to the surface of the substrate 100; when the first epitaxial layer 411 is a concave surface, the middle part of the upper surface of the first metal silicide layer 510 is recessed away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is a concave surface relative to the surface of the substrate 100. In order to adapt to the film layer shape formed in the epitaxial process and simplify the device manufacturing process steps, the first epitaxial layer 411 and the first metal silicide layer 510 may be convex surfaces relative to the surface of the substrate 100.

[0168] In the embodiments provided by the present disclosure, the device further includes a first source / drain 310 and a second source / drain 320. The first source / drain 310 and the second source / drain 320 are respectively located on both sides of the gate structure 200. The surface of the first source / drain 310 is flush with the surface of the substrate 100, and the surface of the second source / drain 320 is flush with the surface of the substrate 100. The device further includes a second epitaxial layer 421 and a second metal silicide layer 520. The second epitaxial layer 421 covers at least one of the surface of the first source / drain 310 or the surface of the second source / drain 320, and the second epitaxial layer 421 protrudes from the surface of the substrate 100. The upper surface of the second epitaxial layer 421 is a curved surface, and the second epitaxial layer 421 is a Si layer. The second metal silicide layer 520 conformally covers the surface of the second epitaxial layer 421. The upper surface of the second metal silicide layer 520 is a curved surface, and the second metal silicide layer 520 is a CoSi 2 layer.

[0169] Among them, the structures, materials, shapes, and formation methods of the gate structure 200, the first source / drain 310, and the second source / drain 320 in the semiconductor device are as shown in the embodiments of the above manufacturing method, and will not be elaborated here.

[0170] In the embodiments provided by the present disclosure, the first epitaxial layer 411 and the second epitaxial layer 421 can be formed simultaneously by an epitaxial process, and the two can be formed in the same process step to save process steps and simplify the process. Of course, according to process requirements, the two can also be formed step by step. The process and thickness used to form the second epitaxial layer 421 can be the same as or similar to those of the first epitaxial layer 411, and will not be elaborated here.

[0171] In some embodiments, the upper surface of the second epitaxial layer 421 is a convex surface or a concave surface with respect to the surface of the substrate 100. Such surfaces can both achieve the purpose of increasing the line width of the gate structure 200 of the device. Among them, the second metal silicide layer 520 is conformally formed on the second epitaxial layer 421. When the second epitaxial layer 421 is a convex surface, the middle part of the upper surface of the second metal silicide layer 520 protrudes away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is a convex surface with respect to the surface of the substrate 100. When the second epitaxial layer 421 is a concave surface, the middle part of the upper surface of the second metal silicide layer 520 is recessed away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is a concave surface with respect to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the preparation process steps of the device, the second epitaxial layer 421 and the second metal silicide layer 520 can be convex surfaces with respect to the surface of the substrate 100.

[0172] Among them, the thickness of the first epitaxial layer 411 and the second epitaxial layer 421 can be 6 nm to 14 nm. For example, the thickness can be 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, or 14 nm, etc. The thickness of the first metal silicide layer 510 and the second metal silicide layer 520 can be 6 nm to 14 nm. For example, the thickness can be 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, or 14 nm, etc. Since the first metal silicide layer 510 is formed by doping and diffusing the first epitaxial layer 411, the thicknesses of the first epitaxial layer 411 and the first metal silicide layer 510 can be coordinated with each other. Similarly, the thicknesses of the second epitaxial layer 421 and the second metal silicide layer 520 can be coordinated with each other.

[0173] In the embodiments provided by the present disclosure, the semiconductor device can be at least one selected from NMOS devices, PMOS devices, or CMOS devices. The semiconductor device can be a semiconductor composed of multiple NMOS devices, or a semiconductor composed of multiple PMOS devices, or a semiconductor composed of multiple CMOS devices, or a semiconductor device composed of any two or three of the above three devices. The specific device type can be selected according to actual requirements.

[0174] For the composition and formation method of other film layers and structures of the semiconductor device provided in this embodiment, reference can be made to the manufacturing method embodiments shown, and details are not described herein again.

[0175] In the semiconductor device provided by the present disclosure, a first epitaxial layer 411 is formed between the metal silicide layer and the gate layer 220, and the upper surface of the first epitaxial layer 411 is a curved surface, thereby increasing the line width of the device. During the process of forming the metal silicide layer, the influence of the line width effect on the formation quality of the metal silicide film layer is overcome, the generation of agglomeration defects in the metal silicide film layer is avoided, and the formed metal silicide film layer has characteristics such as a smaller resistivity, which helps to reduce the contact resistance of the device; in addition, due to the existence of the first epitaxial layer 411, the difference in thermal stability caused by factors such as doping during the process of the device can be balanced, the thermal stability of the device is improved, and thus the overall performance of the device is enhanced.

[0176] The embodiments of the present disclosure provide a semiconductor device, as Figure 13 shown, the device includes: a substrate 100, a gate structure 200, and a first metal silicide layer 510.

[0177] Among them, the gate structure 200 protrudes from the surface of the substrate 100. The gate structure 200 includes a gate oxide layer 210, a gate layer 220, and a gate protection layer 230. The gate oxide layer 210 is formed on the surface of the substrate 100. The gate layer 220 is formed on the gate oxide layer 210. The gate protection layer 230 covers the sidewalls formed by the gate oxide layer 210 and the gate layer 220 together, and the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. The first metal silicide layer 510 covers the top surface of the gate layer 220, and the upper surface of the first metal silicide layer 510 is a curved surface. The first metal silicide layer 510 is a CoSi 2 layer.

[0178] In the semiconductor device provided by the present disclosure, a metal silicide layer is formed on the surface of the gate layer 220, and the upper surface of the metal silicide layer is a curved surface. Since the metal silicide layer is formed outside the gate structure 200, which is different from directly doping the gate layer 220 to form a metal silicide layer, such a device overcomes the line width effect, and the formed metal silicide layer has better formation quality, overcomes the agglomeration defects caused by the small line width, and thus improves the overall performance of the device.

[0179] Next, each part of the semiconductor device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings:

[0180] The semiconductor device provided by the present disclosure can be manufactured by the above manufacturing method.

[0181] Among them, the substrate 100 can be a silicon (Si) substrate, an SOI (Silicon On Insulator), etc., and an epitaxial layer with a single crystal silicon structure can be directly formed on its surface. In some embodiments, the substrate 100 can also be other types of substrates, such as a sapphire (Al 2 O 3 ) substrate, an SOS (Silicon-on-Sapphire), or a GOI (Germanium On Insulator), and can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs), etc. It should be noted that when the substrate 100 is other types of substrates, it can be used as a hetero-substrate, and a silicon buffer layer can be grown on it to provide a film layer basis for subsequent growth of the epitaxial layer. The embodiments provided by the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, which are all within the protection scope of the present disclosure.

[0182] In some embodiments, the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. Among them, the top surface of the gate protection layer 230 can be lower than the top surface of the gate layer 220, and a part of the side wall of the gate layer 220 is exposed by the gate protection layer 230. The first epitaxial layer 411 covers the top surface and the exposed side wall of the gate layer 220. The exposed side wall can jointly form the process line width of the gate structure 200 with the top surface to increase the line width of the gate structure 200 and provide a larger line width for the formation of the metal silicide layer. Among them, the top surface of the gate protection layer 230 can be flush with the top surface of the gate layer 220. The first epitaxial layer 411 covers the top surface of the gate layer 220, and the side wall of the first epitaxial layer 411 is flush with the side wall of the gate layer 220.

[0183] Among them, the exposed height of the side wall of the gate layer 220 can be 10% - 30% of the overall height of the gate layer 220, which not only ensures the insulation and isolation functions of the gate protection layer 230, but also ensures that the gate structure 200 achieves the purpose of increasing the line width, providing a device basis for the formation of subsequent film layers.

[0184] In some embodiments, the middle part of the upper surface of the first metal silicide layer 510 protrudes away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is a convex surface relative to the surface of the substrate 100; or the middle part of the upper surface of the first metal silicide layer 510 is recessed away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is a concave surface relative to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the device manufacturing process steps, the first metal silicide layer 510 can be a convex surface relative to the surface of the substrate 100.

[0185] In the embodiments provided by the present disclosure, the device further includes a first source / drain 310 and a second source / drain 320. The first source / drain 310 and the second source / drain 320 are respectively located on both sides of the gate structure 200. The surface of the first source / drain 310 is flush with the surface of the substrate 100, and the surface of the second source / drain 320 is flush with the surface of the substrate 100; the device further includes a second metal silicide layer 520; the second metal silicide layer 520 covers at least one of the surface of the first source / drain 310 or the surface of the second source / drain 320. The upper surface of the second metal silicide layer 520 is a curved surface, and the second metal silicide layer 520 is a CoSi 2 layer.

[0186] Among them, the structures, materials, shapes and formation methods of the gate structure 200, the first source / drain 310 and the second source / drain 320 in the semiconductor device are as shown in the embodiments of the above manufacturing method, and will not be elaborated here.

[0187] In the embodiments provided by the present disclosure, the first metal silicide layer 510 and the second metal silicide layer 520 can be formed in the same process step to save process steps and simplify the process. Of course, according to process requirements, they can also be formed step by step. The process and thickness used to form the second metal silicide layer 520 can be the same as or similar to those of the first metal silicide layer 510, which will not be elaborated here.

[0188] In some embodiments, the middle part of the upper surface of the second metal silicide layer 520 protrudes away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is a convex surface relative to the surface of the substrate 100; the middle part of the upper surface of the second metal silicide layer 520 is recessed away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is a concave surface relative to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the process steps of device preparation, the second metal silicide layer 520 can be a convex surface relative to the surface of the substrate 100.

[0189] Among them, the thickness of the first metal silicide layer 510 and the second metal silicide layer 520 can be 6 nm to 14 nm. For example, the thickness can be 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm or 14 nm, etc.

[0190] In the embodiments provided by the present disclosure, the semiconductor device can be at least one selected from NMOS devices, PMOS devices or CMOS devices. The semiconductor device can be a semiconductor composed of multiple NMOS devices, or a semiconductor composed of multiple PMOS devices, or a semiconductor composed of multiple CMOS devices, or a semiconductor device composed of any two or three of the above three devices. The specific device type can be selected according to actual needs.

[0191] For the composition and formation method of other film layers and structures of the semiconductor device provided in this embodiment, reference can be made to the manufacturing method embodiments, which will not be elaborated here.

[0192] The semiconductor device provided by the present disclosure forms a metal silicide layer on the surface of the gate layer 220, and the upper surface of the metal silicide layer is a curved surface. Since this metal silicide layer is formed outside the gate structure 200, different from directly doping the gate layer 220 to form a metal silicide layer, such a device overcomes the linewidth effect, the formed metal silicide layer has good formation quality, overcomes the aggregation defects caused by small linewidth, and thus improves the overall performance of the device.

[0193] The semiconductor device provided by the present disclosure can be applied to memories such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory, Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (ReRAM), etc. Of course, it can also be applied to other storage devices not listed here, and will not be enumerated one by one here.

[0194] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A gate structure, wherein the gate structure is protrudingly disposed on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewall formed by the gate oxide layer and the gate layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer; a first epitaxial layer, wherein the first epitaxial layer covers a top surface of the gate layer, and an upper surface of the first epitaxial layer is a curved surface, and the first epitaxial layer is a Si layer; A first metal silicide layer, wherein the first metal silicide layer conformally covers the first epitaxial layer, and an upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer.

2. The semiconductor device according to claim 1, wherein: The top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes a portion of the side wall of the gate layer, and the first epitaxial layer covers the top surface and the exposed side wall of the gate layer.

3. The semiconductor device according to claim 1, wherein: The top surface of the gate protection layer is flush with the top surface of the gate layer, the first epitaxial layer covers the top surface of the gate layer, and the side wall of the first epitaxial layer is flush with the side wall of the gate layer.

4. The semiconductor device according to claim 1, wherein: A middle portion of an upper surface of the first metal silicide layer protrudes in a direction away from the substrate.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The device further includes a first source and a drain and a second source and a drain, wherein the first source and the drain are respectively located on two sides of the gate structure, and a surface of the first source and the drain is flush with a surface of the substrate, and a surface of the second source and the drain is flush with a surface of the substrate; The device also includes a second epitaxial layer and a second metal silicide layer; The second epitaxial layer covers at least one of the surface of the first source and drain electrode or the surface of the second source and drain electrode, and the second epitaxial layer protrudes from the surface of the substrate, the upper surface of the second epitaxial layer is a curved surface, and the second epitaxial layer is a Si layer; The second metal silicide layer conformally covers the surface of the second epitaxial layer, the upper surface of the second metal silicide layer is a curved surface, and the second metal silicide layer is a CoSi2 layer.

6. The semiconductor device according to claim 5, characterized in that A middle portion of an upper surface of the second metal silicide layer protrudes in a direction away from the substrate.

7. The semiconductor device according to claim 5, characterized in that The thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

8. The semiconductor device according to claim 1, wherein: The semiconductor device is selected from at least one of a PMOS device, an NMOS device or a CMOS device.

9. A semiconductor device, characterized in that: include: substrate; A gate structure, wherein the gate structure is protrudingly disposed on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewall formed by the gate oxide layer and the gate layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer; A first metal silicide layer, wherein the first metal silicide layer covers the top surface of the gate layer, and the upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer.

10. The semiconductor device according to claim 9, characterized in that The top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes a portion of the side wall of the gate layer, and the first metal silicide layer covers the top surface and the exposed side wall of the gate layer.

11. The semiconductor device according to claim 9, characterized in that The top surface of the gate protection layer is flush with the top surface of the gate layer, the first metal silicide layer covers the top surface of the gate layer, and the side wall of the first metal silicide layer is flush with the side wall of the gate layer.

12. The semiconductor device according to claim 9, characterized in that A middle portion of an upper surface of the first metal silicide layer protrudes in a direction away from the substrate.

13. The semiconductor device according to any one of claims 9 to 12, characterized in that: The device further includes a first source and a drain and a second source and a drain, wherein the first source and the drain are respectively located on two sides of the gate structure, and a surface of the first source and the drain is flush with a surface of the substrate, and a surface of the second source and the drain is flush with a surface of the substrate; The device also includes a second metal silicide layer, which covers at least one of the surfaces of the first source and drain or the second source and drain, the upper surface of the second metal silicide layer is a curved surface, and the second metal silicide layer is a CoSi2 layer.

14. The semiconductor device according to claim 13, characterized in that A middle portion of an upper surface of the second metal silicide layer protrudes in a direction away from the substrate.

15. The semiconductor device according to claim 13, wherein: The thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

16. The semiconductor device according to claim 9, characterized in that The semiconductor device is selected from at least one of a PMOS device, an NMOS device or a CMOS device.

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