Packaging structure

Abstract

The utility model discloses a packaging structure, and the structure comprises a metal substrate, one side of the substrate is provided with at least one groove; the sintering connecting layer is arranged at the bottom of the groove; and the chip is arranged on the sintering connecting layer and is arranged in one corresponding groove through the sintering connecting layer, and the depth of the groove is greater than or equal to the thickness of the chip and the thickness of the sintering connecting layer. Through the mode, the defects existing in the chip installation process in the existing chip packaging process are overcome, the high-temperature and high-pressure working environment can be resisted, the packaging reliability is guaranteed, the production requirement is met, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a packaging structure. Background Art

[0002] In the current packaging structure, high-power chips are mainly installed on direct-bonded ceramic substrates through gold-tin eutectic welding or conductive adhesive, and electrical interconnection is achieved on the front side through gold or aluminum wire bonding.

[0003] However, traditional soldering and conductive adhesive processes have disadvantages such as poor conductivity and high thermal resistance. They are prone to degradation phenomena such as creep under conditions of large temperature changes, causing reliability problems such as fatigue failure, resulting in reduced reliability of the packaging structure. Utility Model Content

[0004] The main technical problem solved by the present application is to provide a packaging structure that overcomes the defects existing in chip installation during the existing chip packaging process, can withstand high temperature and high pressure working environment, ensure packaging reliability, meet production needs, and reduce production costs.

[0005] In order to solve the above technical problems, the technical solution adopted in the present application provides a packaging structure, wherein the packaging structure includes:

[0006] A metal substrate, with at least one groove arranged on one side of the substrate; a sintered connection layer arranged at the bottom of the groove, the sintered connection layer comprising a silver-containing sintered connection layer or a copper-containing sintered connection layer; a chip, placed on the sintered connection layer, installed in one of the corresponding grooves through the sintered connection layer, the depth of the groove being greater than or equal to the thickness of the chip and the sintered connection layer.

[0007] Wherein, the thickness of the metal substrate is greater than 1 mm.

[0008] Wherein, an insulating component is arranged between two adjacent grooves.

[0009] A spacing groove is arranged between the side walls of two adjacent grooves, a first insulating layer is arranged at the bottom of the spacing groove, the first insulating layer extends to the position corresponding to the bottom of the groove, and the projection of the groove along the stacking direction of the chip and the sintered connection layer all falls on the first insulating layer.

[0010] The packaging structure also includes: a carrier board having a through groove formed thereon, and a substrate with a chip mounted thereon is arranged in the through groove; an insulating layer, which covers the substrate, the chip, and a surface of one side of the carrier board close to the chip and fills all gaps in the through groove.

[0011] Among them, the packaging structure includes: an electrode layer, which is arranged on one side of the chip and penetrates the insulating layer; the electrode layer includes multiple transistors, each transistor corresponds to a chip, and the pins of each transistor are respectively connected to the substrate or the chip.

[0012] Among them, the first end of the transistor is connected to the first side wall of the corresponding groove, the second end and the control end of the transistor are respectively connected to the chip in the groove, and the second side wall of the groove is connected to the second end of the adjacent transistor corresponding to the adjacent groove, so that the first end of the transistor is connected to the second end of the adjacent transistor through the first side wall, bottom and second side wall of the groove.

[0013] A metal layer is also provided at the bottom of the substrate to support the carrier.

[0014] Wherein, the thickness of the sintered connecting layer is 10 to 100 microns.

[0015] Wherein, the vertical distance between the edge of the sintered connection layer and the side wall of the groove is 100 to 500 microns.

[0016] Different from the prior art, the packaging structure provided by the present application overcomes the defects existing in chip installation during the existing chip packaging process, improves the heat dissipation efficiency of the chip, reduces the thermal resistance of the chip to the ground, improves the working efficiency of the chip, withstands high temperature and high pressure working environment, ensures packaging reliability, meets production needs, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of an implementation method of the packaging structure of the present application;

[0018] Figure 2 It is a structural schematic diagram of an installation step of an implementation method of the packaging structure of the present application;

[0019] Figure 3 It is a structural schematic diagram of another implementation method of the packaging structure of the present application;

[0020] Figure 4 It is a structural schematic diagram of an installation step of another implementation method of the packaging structure of the present application. DETAILED DESCRIPTION

[0021] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0022] The present application provides a packaging structure 100, which is used to provide support, interconnection, protection for a chip 103 and to realize the connection between the chip 103 and an external circuit. The packaging structure 100 can overcome the defects existing in the installation of the chip 103 in the existing chip packaging process, can withstand a high temperature and high pressure working environment, ensure packaging reliability, meet production requirements, and reduce production costs.

[0023] See also Figure 1 , Figure 2 , Figure 1 It is a structural schematic diagram of an implementation method of the packaging structure of the present application; Figure 2 It is a structural schematic diagram of an installation step of an implementation method of the packaging structure of the present application.

[0024] The packaging structure 100 includes:

[0025] A metal substrate 101, with at least one groove 1011 disposed on one side of the metal substrate 101; a sintered connection layer 102, disposed at the bottom of the groove 1011, the sintered connection layer comprising a silver-containing sintered connection layer or a copper-containing sintered connection layer; a chip 103, disposed on the sintered connection layer 102, and installed in one of the corresponding grooves 1011 through the sintered connection layer 102, wherein the depth of the groove 1011 is greater than or equal to the thickness of the chip 103 and the sintered connection layer.

[0026] The metal substrate 101 may be a metal substrate or alloy metal substrate including but not limited to copper, silver, aluminum, nickel, and may also be provided with an insulating material such as ceramics, resin, or a sandwich layer with a metal circuit pattern.

[0027] In an optional embodiment, the thickness of the metal substrate 101 is greater than 1 mm.

[0028] The thickness of the metal substrate 101 may be greater than 1 mm, including but not limited to 1 mm, 1.1 mm, 1.2 mm, 1.5 mm, 1.6 mm, 2.0 mm, 2.5 mm, 2.6 mm, 3.0 mm, 4.0 mm, 5.0 mm, etc.

[0029] The preparation of the groove 1011 can be performed by mechanical drilling, laser drilling or etching. After the groove is etched, the thickness of the metal substrate is still greater than the depth of the groove 1011, which can achieve a good heat dissipation effect.

[0030] The sintered connection layer 102 may be formed by sintering an alloy paste or alloy powder consisting of silver and tin, gold, silicon, indium, lead, lead, or tin, or by sintering a silver paste or copper paste consisting of silver or copper and epoxy resin or conductive glue.

[0031] like Figure 1 As shown, in a specific embodiment, the sintered connection layer 102 can be formed by a nano silver-containing or copper-containing sintered material after sintering or other heat treatment. The thermal conductivity of the sintered connection layer 102 can reach 200W / (K·m), which is much higher than that of traditional welding or bonding materials, and the thickness of the sintered connection layer 102 is controllable. Compared with traditional solder alloy packaging, the use of silver-containing or copper-containing sintering hormones can improve the reliability of module temperature cycling by more than 5 times, so that the packaging structure 100 can achieve better heat dissipation effect, which can not only reduce the thermal resistance of the chip 103 to the ground, but also solve the voltage drop and heat consumption problems caused by high current transmission in the circuit pattern.

[0032] The chip 103 and the sintered connection layer 102 are accommodated in the groove 1011, so that the chip 103 and the top of the side wall (not shown) of the groove 1011 are in the same plane, which helps to ensure the flatness and consistency during packaging, thereby improving the reliability of the packaging structure 100. In other embodiments, the wall of the groove 1011 can be higher than the top of the chip 103 after installation, so that the chip 103 can be packaged more firmly.

[0033] In the packaging structure 100, the chip 103 is installed in one of the corresponding grooves 1011 through the sintered connection layer 102. Specifically, one or two chips 103 may be installed on a metal substrate 101, and a plurality of metal substrates 101 may be packaged to form the packaging structure 100; or two or more chips 103 may be accommodated on a metal substrate 101, and a metal substrate 101 may be packaged to form the packaging structure 100.

[0034] The chip 103 is installed in the groove 1011 of the metal substrate 101, so that the metal substrate 101 is set at the bottom of the chip 103. Therefore, when the packaging structure 100 is applied to high-power products, it can withstand the high-voltage and high-current working environment, which helps to more effectively transfer the heat generated by the chip 103 to the metal substrate 101.

[0035] In an optional implementation, an insulating component (not shown) is disposed between two adjacent grooves 1011 .

[0036] The insulating component can be formed by embedding or filling insulating materials such as ceramics and resins. The insulating component is arranged between the two grooves 1011 to ensure the insulation between the metal substrates 101, so that the signal transmission of the chip 103 meets the production requirements.

[0037] In an optional embodiment, the packaging structure also includes: a carrier 104, a through groove 1041 is formed on the carrier 104, and the substrate 101 with the chip 103 mounted on it is arranged in the through groove 1041; an insulating layer 105, the insulating layer 105 covers the substrate 101, the chip 103 and the side surface of the carrier 104 close to the chip 103, and fills all gaps in the through groove 1041.

[0038] The carrier 104 that accommodates the metal substrate 101 needs to be greater than or equal to the thickness of the metal substrate 101. The interior of the carrier 104 may be provided with an insulating material such as ceramic, resin, or a sandwich layer with a metal circuit pattern. Specifically, the thickness of the carrier 104 may be greater than 1 mm, including but not limited to 1 mm, 1.1 mm, 1.2 mm, 1.5 mm, 1.6 mm, 2.0 mm, 2.5 mm, 2.6 mm, 3.0 mm, 4.0 mm, 5.0 mm, etc.

[0039] The through slots 1041 may be prepared by mechanical drilling, laser drilling, or etching, and the size of the through slots 1041 is set according to the size of the metal substrate 101, so that each through slot 1041 can accommodate a metal substrate 101 with a chip 103 installed. In a specific embodiment, a metal substrate 101 with a chip 103 installed is arranged in each through slot 1041. In other embodiments, a metal substrate 101 with more than one chip 103 installed may be arranged in one through slot 1041.

[0040] like Figure 2 As shown, a sticky tape 109 is provided on one side of the through groove 1041 to temporarily fix the metal substrate 101 when it is installed, and then the metal substrate 101 is fixed in the carrier 104 through the insulating layer 105. In a specific embodiment, the insulating layer 105 of the package structure 100 is filled by pouring once, and in other embodiments, the metal substrate 101 with the chip 103 installed can be insulated and filled first, and then the metal substrate 101 can be installed on the frame for insulation filling.

[0041] The insulating layer 105 fills the through groove 1041 and wraps the metal substrate 101 on which the chip 103 is mounted. The insulating layer 105 may include but is not limited to one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), ceramic-based, etc.

[0042] In an optional embodiment, the packaging structure includes: an electrode layer 106, which is arranged on one side of the chip 103 and penetrates the insulating layer 105; the electrode layer 106 includes a plurality of transistors 107, each transistor 107 corresponds to a chip 103, and the pins of each transistor 107 are respectively connected to the substrate or the chip.

[0043] A circuit pattern is arranged on the electrode layer 106, a transistor 107 is arranged on the top of each chip 103, a blind hole is formed on the insulating layer 105 by mechanical drilling, laser drilling or etching, and the blind hole is electroplated to form the transistor 107. The circuit pattern is connected to the chip 103 through the transistor 107, so that the chip 103 forms a fan-out panel level package (FOPLP), realizing the interconnection of signals between the package structure 100 and external signals.

[0044] The chip 103 is arranged on the metal substrate 101, so that when manufacturing the transistor 107, the blind hole drilling depth can be the same and the blind hole depth can be shortened, which helps to avoid problems that affect conductivity such as uneven plating, depressions or gaps when electroplating to form the transistor 107. It can also reduce the parasitic inductance of the circuit pattern of the transistor 107 or the electrode layer 106, which can reduce the parasitic capacitance and assist in heat dissipation of the chip 103.

[0045] In an optional implementation, a metal layer 108 is further disposed at the bottom of the substrate to support the carrier 104 .

[0046] The bottom metal layer 108 supports the bottom of the metal substrate 101 and the carrier 104, thereby improving the hardness and toughness of the package structure and providing a heat dissipation path for the chip 103 at the bottom of the package structure 100. In other embodiments, the chip 103 is interconnected with the signal between the metal substrate 101 and the carrier 104, and further interconnected with the signal outside the package structure 100.

[0047] See also Figure 3 , Figure 4 , Figure 3 It is a structural schematic diagram of another implementation method of the packaging structure of the present application; Figure 4 It is a structural schematic diagram of an installation step of another implementation method of the packaging structure of the present application.

[0048] like Figure 3 As shown, the packaging structure 100 includes:

[0049] A metal substrate 101, with at least one groove 1011 disposed on one side of the metal substrate 101; a sintered connection layer disposed at the bottom of the groove 1011, the sintered connection layer comprising a silver-containing sintered connection layer or a copper-containing sintered connection layer; a chip 103, disposed on the sintered connection layer 102, and installed in one of the corresponding grooves 1011 through the sintered connection layer 102, wherein the depth of the groove 1011 is greater than or equal to the thickness of the chip 103 and the sintered connection layer 102.

[0050] The metal substrate 101 may be a metal substrate or alloy metal substrate including but not limited to copper, silver, aluminum, nickel, and may also be provided with an insulating material such as ceramics, resin, or a sandwich layer with a metal circuit pattern.

[0051] In an optional embodiment, the thickness of the metal substrate 101 is greater than 1 mm.

[0052] The thickness of the metal substrate 101 may be greater than 1 mm, including but not limited to 1 mm, 1.1 mm, 1.2 mm, 1.5 mm, 1.6 mm, 2.0 mm, 2.5 mm, 2.6 mm, 3.0 mm, 4.0 mm, 5.0 mm, etc.

[0053] The preparation of the groove 1011 can be performed by mechanical drilling, laser drilling or etching. After the groove is etched, the thickness of the metal substrate 101 is still greater than the depth of the groove 1011, which can achieve a good heat dissipation effect.

[0054] The sintered connection layer 102 may be formed by sintering an alloy paste or alloy powder consisting of silver and tin, gold, silicon, indium, lead, lead, or tin, or by sintering a silver paste or copper paste consisting of silver or copper and epoxy resin or conductive glue.

[0055] In a specific embodiment, the sintered connection layer 102 can be formed by sintering nano silver-containing or copper-containing sintered materials, etc. The thermal conductivity of the sintered connection layer 102 can reach 200W / (K·m), which is much higher than that of traditional welding or bonding materials, and the thickness of the sintered connection layer 102 is controllable. Compared with traditional solder alloy packaging, the use of silver-containing or copper-containing sintering technology can improve the reliability of module temperature cycling by more than 5 times, so that the packaging structure 100 can achieve better heat dissipation effect, which can not only reduce the thermal resistance of the chip 103 to the ground, but also solve the voltage drop and heat consumption problems caused by high current transmission in the circuit pattern.

[0056] The chip 103 and the sintered connection layer 102 are accommodated in the groove 1011, so that the chip 103 and the top of the side wall (not shown) of the groove 1011 are in the same plane, which helps to ensure the flatness and consistency during packaging, thereby improving the reliability of the packaging structure 100. In other embodiments, the wall of the groove 1011 can be higher than the top of the chip 103 after installation, so that the chip 103 can be packaged more firmly.

[0057] In the packaging structure 100, the chip 103 is installed in one of the corresponding grooves 1011 through the sintered connection layer 102. Specifically, one or two chips 103 may be installed on a metal substrate 101, and a plurality of metal substrates 101 may be packaged to form the packaging structure 100; or two or more chips 103 may be accommodated on a metal substrate 101, and a metal substrate 101 may be packaged to form the packaging structure 100.

[0058] The chip 103 is installed in the groove 1011 of the metal substrate 101, so that the metal substrate 101 is set at the bottom of the chip 103. Therefore, when the packaging structure 100 is applied to high-power products, it can withstand the high-voltage and high-current working environment, which helps to more effectively transfer the heat generated by the chip 103 to the metal substrate 101.

[0059] In an optional implementation, an insulating component (not shown) is disposed between two adjacent grooves 1011 .

[0060] The insulating component can be formed by embedding or filling insulating materials such as ceramics and resins. By setting the insulating component between the two grooves 1011, the insulation between the metal substrates 101 is guaranteed, so that the signal transmission of the chip 103 meets the production requirements.

[0061] In an optional embodiment, a spacing groove 1012 is arranged between the side walls of two adjacent grooves 1011, and a first insulating layer 1013 is arranged at the bottom of the spacing groove 1012. The first insulating layer 1013 extends to a position corresponding to the bottom of the groove 1011, and the projection of the groove 1011 along the stacking direction of the chip 103 and the sintered connection layer 102 all falls on the first insulating layer 1013.

[0062] The first insulating layer 1013 may include but is not limited to one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), ceramic-based, and the like.

[0063] After each chip 103 is mounted on the metal substrate 101 , the spacing grooves 1012 prevent the chips 103 from being directly connected to each other through the metal at the bottom of the groove 1011 , thereby improving the insulation effect of the package structure 100 .

[0064] In an optional embodiment, the packaging structure also includes: a carrier 104, a through groove 1041 is formed on the carrier 104, and the substrate 101 with the chip 103 mounted on it is arranged in the through groove 1041; an insulating layer 105, the insulating layer 105 covers the substrate 101, the chip 103 and the side surface of the carrier 104 close to the chip 103, and fills all gaps in the through groove 1041.

[0065] The carrier 104 that accommodates the metal substrate 101 needs to be greater than or equal to the thickness of the metal substrate 101. The interior of the carrier 104 may be provided with an insulating material such as ceramic, resin, or a sandwich layer with a metal circuit pattern. Specifically, the thickness of the carrier 104 may be greater than 1 mm, including but not limited to 1 mm, 1.1 mm, 1.2 mm, 1.5 mm, 1.6 mm, 2.0 mm, 2.5 mm, 2.6 mm, 3.0 mm, 4.0 mm, 5.0 mm, etc.

[0066] The through slots 1041 may be prepared by mechanical drilling, laser drilling, or etching, and the size of the through slots 1041 is set according to the size of the metal substrate 101, so that each through slot 1041 can accommodate a metal substrate 101 with a chip 103 installed. In a specific embodiment, a metal substrate 101 with a chip 103 installed is arranged in each through slot 1041. In other embodiments, a metal substrate 101 with more than one chip 103 installed may be arranged in one through slot 1041.

[0067] like Figure 4 As shown, a sticky tape 109 is provided on one side of the through groove 1041 to temporarily fix the metal substrate 101 when it is installed, and then the metal substrate 101 is fixed in the carrier 104 through the insulating layer 105. In a specific embodiment, the insulating layer 105 of the package structure 100 is filled by pouring once, and in other embodiments, the metal substrate 101 with the chip 103 installed can be insulated and filled first, and then the metal substrate 101 can be installed on the frame for insulation filling.

[0068] The insulating layer 105 fills the through groove 1041 and wraps the metal substrate 101 on which the chip 103 is mounted. The insulating layer 105 may include but is not limited to one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), ceramic-based, etc.

[0069] In an optional embodiment, the packaging structure includes: an electrode layer 106, which is arranged on one side of the chip 103 and penetrates the insulating layer 105; the electrode layer 106 includes a plurality of transistors 107, each transistor 107 corresponds to a chip 103, and the pins of each transistor 107 are respectively connected to the substrate 101 or the chip 103.

[0070] A circuit pattern is arranged on the electrode layer 106, and a transistor 107 is arranged on the top of each chip 103. A blind hole is formed on the insulating layer 105 by mechanical drilling, laser drilling or etching, and the blind hole is electroplated to form the transistor 107. The circuit pattern is connected to the chip 103 through the transistor 107, so that the chip 103 forms a fan-out panel level package (FOPLP), realizing the interconnection of signals between the package structure 100 and external signals.

[0071] The chip 103 is arranged on the metal substrate 101, so that when manufacturing the transistor 107, the blind hole drilling depth can be the same and the blind hole depth can be shortened, which helps to avoid problems that affect conductivity such as uneven plating, depressions or gaps when electroplating to form the transistor 107. It can also reduce the parasitic inductance of the transistor 107 or the circuit pattern, reduce the parasitic capacitance, and assist in heat dissipation of the chip 103.

[0072] In an optional embodiment, the first end of the transistor 107 is connected to the first side wall of the corresponding groove 1011 (not shown), the second end and the control end of the transistor 107 are respectively connected to the chip in the groove 1011, and the second side wall of the groove 1011 is connected to the second end of the adjacent transistor 107 corresponding to the adjacent groove 1011, so that the first end of the transistor 107 is connected to the second end of the adjacent transistor through the first side wall, bottom and second side wall of the groove.

[0073] The transistor 107 may have a first end that is a source and a second end that is a drain, or a first end that is a drain and a second end that is a source. The signal is connected to the adjacent chip through the sidewall of the groove 1011, and the blind hole depth of the gate and source of the transistor 107 of the chip 103 is reduced, which reduces the depression depth of the pad of the electrode layer 106 and maintains the consistency and flatness of the appearance.

[0074] In an optional implementation, a metal layer 108 is further disposed at the bottom of the substrate to support the carrier 104 .

[0075] The bottom metal layer 108 supports the bottom of the metal substrate 101 and the carrier 104, thereby improving the hardness and toughness of the package structure 100 and providing a heat dissipation path for the chip 103 to dissipate heat from the bottom of the package structure 100. In other embodiments, the chip 103 is interconnected with the signals between the metal substrate 101 and the carrier 104, and further interconnected with the signals outside the package structure 100.

[0076] In an optional embodiment, the packaging structure 100 includes: an electrode layer 106, which is arranged on a side surface of the insulating layer 105 away from the chip 103; a transistor 107 penetrates the insulating layer 105 to connect the electrode layer 106 and the chip 103 to achieve connection between the chips 103.

[0077] A circuit pattern is arranged on the electrode layer 106, a transistor 107 is arranged on the top of each chip 103, a blind hole is formed correspondingly by mechanical drilling, laser drilling or etching, and the blind hole is electroplated to form the transistor 107. The circuit pattern is connected to the chip 103 through the transistor 107, so that the chip 103 forms a fan-out panel-level package (FOPLP), realizing the interconnection of signals between the package structure 100 and external signals.

[0078] The chip 103 is arranged on the metal substrate 101, so that the blind hole drilling depth can be the same and the blind hole depth can be shortened when manufacturing the transistor 107, which helps to avoid problems that affect conductivity such as uneven plating, depressions or gaps when electroplating to form the transistor 107. It can also reduce the parasitic inductance of the transistor 107 or the circuit pattern, reduce the parasitic capacitance, and assist in heat dissipation of the chip 103.

[0079] In an optional implementation, the package structure 100 further includes: a portion of the transistor 107 is led out through the top of the side wall of the groove 1011 and connected to the electrode layer 106 .

[0080] The transistor 107 led out from the side wall of the groove 1011 allows the signal at the bottom of the chip 103 to be interconnected through the metal substrate 101, and the height is the same as the chip 103 after installation, so that the blind hole drilling depth is the same when making the transistor 107, and the blind hole depth is shortened, which helps to avoid problems that affect conductivity such as uneven plating, depression or missing filling when electroplating to form the transistor 107, and can also reduce the parasitic inductance of the circuit pattern of the transistor 107 or the electrode layer 106, reduce the parasitic capacitance, and assist the heat dissipation of the chip 103.

[0081] In an optional implementation, an electrode layer 106 is further disposed at the bottom of the metal substrate 101 , and the electrode layer 106 connects the metal substrate 101 and the carrier 104 .

[0082] The bottom electrode layer 106 connects the bottom of the metal substrate 101 and the carrier 104, providing a way for the chip 103 to dissipate heat from the bottom of the package structure 100. In other embodiments, the chip 103 interconnects the signals between the metal substrate 101 and the carrier 104 through the sintered connection layer 102, and further interconnects the signals outside the package structure 100.

[0083] Wherein, the thickness of the sintered connecting layer is 10 to 100 microns.

[0084] The thickness design of the sintered connection layer 102 is determined according to the size of the chip 103. The specific thickness is proportional to the size of the chip 103. The thickness can be 10 microns, 20 microns, 25 microns, 30 microns, 45 microns, 50 microns, 75 microns, 80 microns, 100 microns, etc.

[0085] In a specific embodiment, the size of the sintered connecting layer 102 projected to the bottom of the groove 1011 can be the same as the size of the chip 103, but the installation accuracy requirements will be higher, so the size of the sintered connecting layer 102 projected to the bottom of the groove 1011 can be larger than a certain difference in the size of the chip 103, such as 50 microns, 75 microns, 80 microns, 100 microns, 120 microns, 150 microns, 200 microns, etc., and the price of the sintered material needs to be taken into consideration. When the size of the sintered connecting layer 102 is larger, more sintered material needs to be printed, which will also result in higher production costs.

[0086] In an optional embodiment, the vertical distance between the edge of the sintered bonding layer 102 and the side wall of the groove 1011 is 100 to 500 micrometers.

[0087] In order to accommodate the printing frame, the size of the sintered connection layer 102 is designed according to the size of the groove 1011 and the edge of the printing frame, and in order to achieve the insulation effect, an insulating layer 105 is arranged between the side wall of the groove 1011 and the chip 103. The vertical distance can be 100 microns, 120 microns, 125 microns, 150 microns, 180 microns, 200 microns, 300 microns, 400 microns, 500 microns, etc., so as to fill the insulating material in the gap between the sintered connection layer 102 and the side wall of the groove 1011 and the chip 103 and the side wall of the groove 1011.

[0088] In an optional embodiment, the sintered connecting layer 102 is replaced by other sintered materials that are heat treated to form a connecting layer. The sintered material can be a sintered material formed by a metal or alloy of tin, gold, silicon, indium, lead, silver, lead, tin, or a sintered material formed by ceramics such as silicon nitride and silicon carbide.

[0089] Through the above method, a packaging structure 100 is provided, which overcomes the defects existing in the installation of the chip 103 in the existing chip packaging process, improves the heat dissipation efficiency of the chip 103, reduces the thermal resistance of the chip 103 to the ground, improves the working efficiency of the chip 103, withstands high temperature and high pressure working environment, ensures packaging reliability, meets production needs, and reduces production costs.

[0090] In the several embodiments provided in the present application, it should be understood that the disclosed systems and devices can be implemented in other ways. For the technical solutions in the embodiments of the present application, it is obvious that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. For example, the device implementation described above is only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0091] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0092] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "coupled", "connected", "connected", "set", and "installed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0093] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0094] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0095] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A packaging structure, characterized in that: The packaging structure comprises: A metal substrate, wherein at least one groove is provided on one side of the substrate; A sintered bonding layer, disposed at the bottom of the groove, wherein the sintered bonding layer includes a silver-containing sintered bonding layer or a copper-containing sintered bonding layer; The chip is placed on the sintered connection layer and installed in one of the corresponding grooves through the sintered connection layer, and the depth of the groove is greater than or equal to the thickness of the chip and the sintered connection layer.

2. The packaging structure according to claim 1, characterized in that: The thickness of the metal substrate is greater than 1 mm.

3. The packaging structure according to claim 1, characterized in that: An insulating component is arranged between two adjacent grooves.

4. The packaging structure according to claim 3, characterized in that: A spacing groove is arranged between the side walls of two adjacent grooves, and a first insulating layer is arranged at the bottom of the spacing groove. The first insulating layer extends to a position corresponding to the bottom of the groove, and the projection of the groove along the stacking direction of the chip and the sintered connection layer all falls on the first insulating layer.

5. The packaging structure according to any one of claims 1 to 4, characterized in that: The packaging structure further includes: A carrier board, wherein a through groove is formed on the carrier board, and the substrate on which the chip is mounted is arranged in the through groove; An insulating layer covers the substrate, the chip and a surface of a carrier close to the chip, and fills all gaps in the through groove.

6. The packaging structure according to claim 5, characterized in that: The packaging structure includes: an electrode layer, which is arranged on one side of the chip and penetrates the insulating layer; the electrode layer includes a plurality of transistors, each of which corresponds to one chip, and the pins of each transistor are respectively connected to the substrate or the chip.

7. The packaging structure according to claim 6, characterized in that: The first end of the transistor is connected to the first side wall of the corresponding groove, the second end and the control end of the transistor are respectively connected to the chip in the groove, and the second side wall of the groove is connected to the second end of the adjacent transistor corresponding to the adjacent groove, so that the first end of the transistor is connected to the second end of the adjacent transistor through the first side wall, bottom and second side wall of the groove.

8. The packaging structure according to claim 5, characterized in that: A metal layer is also disposed at the bottom of the substrate to support the carrier.

9. The packaging structure according to claim 1, characterized in that: The thickness of the sintered bonding layer is 10 to 100 microns.

10. The packaging structure according to claim 2, characterized in that: The vertical distance between the edge of the sintered connection layer and the side wall of the groove is 100 to 500 microns.

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