Power output circuit

Abstract

The utility model provides a power supply output circuit. The power supply output circuit comprises an MOS tube Q1, an MOS tube Q3, a resistor R1, a resistor R2, a switch control circuit and an energy storage capacitor C2. When the input power supply end Vin supplies power normally, the MOS tube Q3 is switched off, the switch control circuit controls the voltage of the node F to enable the MOS tube Q1 to be switched on, and when the input power supply end Vin is subjected to micro-interruption, the MOS tube Q3 is switched on, and the switch control circuit controls the voltage of the node F to enable the MOS tube Q1 to be switched off. Therefore, normal output of the load can be maintained when the low-resistance input power supply end is subjected to micro-interruption.

Description

[Technical field]

[0001] The utility model relates to the technical field of circuit design, in particular to a power output circuit. [Background technology]

[0002] In the automotive electrical system, contact failure, line failure or relay contact rebound may cause the automotive power supply to short to the ground. If the automotive electronic products involved cannot guarantee normal operation within the instantaneous time range of the power short circuit to the ground, it may bring certain risks. In order to ensure that automotive electronic products can work normally within the instantaneous time caused by the power short circuit, it is necessary to add energy storage capacitors in the circuit design of the product to ensure that the product can continue to work within the instantaneous time range of the power short circuit to the ground.

[0003] For the power input terminal, a diode or MOS tube is generally used as an anti-reverse connection circuit to prevent the power input terminal from being reversely connected and causing damage to the product. Figure 1 As shown, it is a circuit diagram of a power supply anti-reverse connection circuit, where Vin is the power supply input terminal, Vout is the output terminal of the input power through the anti-reverse circuit, and Cout represents the energy storage capacitor. Since the diode has a unidirectional conduction property, when the power supply is short-circuited to the ground instantaneously, the charge on the energy storage capacitor Cout will not be discharged to the ground of the power supply short circuit through the diode, thereby ensuring that the charge on the energy storage capacitor Cout is only used to maintain the product working within the instantaneous time range. However, diodes are only suitable for low-power, low-current products. If the product power is large, in order to prevent the diode from burning out due to the large power, the diode will not be selected as the anti-reverse connection circuit, and the PMOS tube will be selected as the anti-reverse connection circuit.

[0004] like Figure 2 As shown, it is a circuit diagram of another power supply reverse connection protection circuit, which selects PMOS tube Q2 as the reverse connection protection circuit, which can meet the needs of high power and large current. However, there is a problem when using PMOS tube Q2 as the reverse connection protection circuit. When a micro-interruption occurs at the input terminal Vin low-resistance power supply, that is, the power supply voltage is pulled down, at this time, due to the existence of energy storage capacitor Cout in the circuit, there is a voltage at the output terminal Vout. According to the conduction characteristics of PMOS tube Q2, when there is a voltage at the output terminal Vout, the voltage between the gate and the source of PMOS tube Q2 is greater than the turn-on voltage of PMOS tube Q2, and the conductive channel of PMOS tube Q2 will not be closed. Since the power supply terminal Vin is in a low-resistance state, the charge on the energy storage capacitor Cout will be discharged to the power supply terminal Vin through the conductive channel of PMOS tube Q2, thereby causing the charge on the energy storage capacitor Cout to decrease rapidly, and the product cannot be maintained to work continuously within the micro-interruption time requirement.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above problems. [Utility Model Content]

[0006] One of the purposes of the utility model is to provide a power output circuit, which can maintain normal output of a load when a micro interruption occurs at a low-resistance input power terminal.

[0007] According to one aspect of the utility model, the utility model provides a power output circuit, which includes a MOS tube Q1, a MOS tube Q3, a resistor R1, a resistor R2, a switch control circuit and an energy storage capacitor C2, wherein the first connection end of the MOS tube Q1 is connected to the input power supply end Vin, the second connection end thereof is connected to the node E, and the control end thereof is connected to the node F; one end of the resistor R1 is connected to the input power supply end Vin, and the other end thereof is connected to the node A; one end of the resistor R2 is connected to the node A, and the other end thereof is connected to the node E; the first connection end of the MOS tube Q3 is connected to the first input end of the switch control circuit, and the other end thereof is connected to the node E. , its control end is connected to the node A; the node E is connected to the output power supply end Vout, one end of the energy storage capacitor C2 is connected to the output power supply end Vout, and the other end thereof is grounded; the second input end of the switch control circuit is connected to the node E, and the output end of the switch control circuit is connected to the node F. When the input power supply end Vin is normally powered, the MOS tube Q3 is turned off, and the switch control circuit controls the voltage of the node F to turn on the MOS tube Q1. When a micro-interruption occurs at the input power supply end Vin, the MOS tube Q3 is turned on, and the switch control circuit controls the voltage of the node F to turn off the MOS tube Q1.

[0008] Compared with the prior art, the utility model can close the conductive channel of the PMOS tube as the anti-reverse connection circuit when a micro-interruption occurs in the low-resistance power supply, so that the charge of the energy storage capacitor in the circuit will not be discharged to the low-resistance part of the power supply end through the conductive channel of the MOS tube, so that the charge on the energy storage capacitor can be used to maintain the product (or load) to continue working within an instantaneous time range.

Brief Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0010] Figure 1 A circuit diagram of a power supply reverse connection protection circuit;

[0011] Figure 2 It is a circuit diagram of another power supply reverse connection protection circuit;

[0012] Figure 3 The schematic diagram of a circuit for maintaining normal output of a load in response to a micro-interruption of a low-resistance power supply at an input end in one embodiment of the utility model. [Specific implementation method]

[0013] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0014] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the utility model. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "coupled", "connected", "connected" and "connected" in this document that indicate electrical connection all mean direct or indirect connection. For example, A is connected to B, which includes both direct electrical connection between A and B and connection between A and B through electrical components or circuits.

[0015] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0016] Please refer to Figure 3 As shown, it is a schematic diagram of a circuit (also called a power output circuit) for maintaining normal output of a load in response to a micro-interruption of a low-resistance power supply at the input end (also called an input power supply end) in one embodiment of the utility model. Figure 3 The power output circuit shown includes a MOS transistor (metal oxide semiconductor, referred to as field effect transistor) Q1, a MOS transistor Q3, a switch control circuit 310 and an energy storage capacitor C2.

[0017] The first connection end of the MOS transistor Q1 is connected to the input power supply terminal Vin, the second connection end thereof is connected to the node E, and the control end thereof is connected to the node F; one end of the resistor R1 is connected to the input power supply terminal Vin, and the other end thereof is connected to the node A; one end of the resistor R2 is connected to the node A, and the other end thereof is connected to the node E; the first connection end of the MOS transistor Q3 is connected to the first input end of the switch control circuit, the other end thereof is connected to the node E, and the control end thereof is connected to the node A; the node E is connected to the output power supply terminal Vout, one end of the energy storage capacitor C2 is connected to the output power supply terminal Vout, and the other end thereof is grounded. The input power supply terminal Vin is a low-resistance power supply.

[0018] The second input end of the switch control circuit is connected to the node E, and the output end of the switch control circuit is connected to the node F. When the input power supply terminal Vin is supplying power normally, the MOS transistor Q3 is turned off, and the switch control circuit controls the voltage of the node F to turn on the MOS transistor Q1. When a micro-interruption occurs at the input power supply terminal Vin, the MOS transistor Q3 is turned on, and the switch control circuit controls the voltage of the node F to turn off the MOS transistor Q1. In this way, when a micro-interruption occurs at the low-resistance input power supply terminal Vin, the power output circuit can maintain normal output of the load, that is, output voltage normally through the output power supply terminal Vout, and also prevent the low-resistance input power supply terminal Vin from being discharged through the conduction channel of the MOS transistor Q1.

[0019] The switch control circuit 310 includes transistors Q2, Q4, Q5, resistors R3, R4, R5, R6, R7, R8, R9, and R10. One end of the resistor R8 is connected to the first connection end of the MOS transistor Q3 as the first input end of the switch control circuit, and the other end of the resistor R8 is connected to the node C. The first connection end of the transistor Q2 is connected to the node E as the second input end of the switch control circuit, the second connection end is connected to the node H, and the control end is connected to the node B; one end of the resistor R3 is connected to the node E, and the other end is connected to the node B; one end of the resistor R4 is connected to the node H, and the other end is grounded; one end of the resistor R5 is connected to the node H, and the other end is connected to the node G; one end of the resistor R6 is connected to the node F as the output end of the switch control circuit, and the other end is connected to the node G; the first connection end of the transistor Q4 is connected to the node G, the second connection end is grounded, and the control end is connected to the node D; one end of the resistor R9 is connected to the node D, and the other end is grounded; one end of the resistor R7 is connected to the node B, and the other end is connected to the node D; the first connection end of the transistor Q5 is connected to the node D, the second connection end is grounded, and the control end is connected to the node C; one end of the resistor R10 is connected to the node C, and the other end is grounded.

[0020] exist Figure 3 In the specific embodiment shown, the MOS transistor (or field effect transistor) Q1 is a PMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q1 are respectively the drain, the source and the gate of the PMOS transistor; the MOS transistor Q3 is a PMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q3 are respectively the drain, the source and the gate of the PMOS transistor; the transistor Q2 is a PNP transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q2 are respectively the emitter, the collector and the base of the PNP transistor; the transistor Q4 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q4 are respectively the collector, the emitter and the base of the NPN transistor; the transistor Q5 is an NPN transistor, and the first connection terminal, the second connection terminal and the control terminal of the transistor Q5 are respectively the collector, the emitter and the base of the NPN transistor.

[0021] The resistance values ​​of the resistors R3, R7 and R9 are selected to satisfy: when the MOS tube Q3 and the transistor Q5 are turned off, the voltage of the node D is greater than the turn-on voltage value of the transistor Q4; the resistance values ​​of the resistors R1 and R2 are selected to satisfy: when a slight power outage occurs at the input power supply terminal Vin, the voltage division value on the resistor R2 is greater than the turn-on voltage value of the MOS tube Q3; the resistance values ​​of the resistors R8 and R10 are selected to satisfy: when the MOS tube Q3 is turned on, the voltage of the node C is greater than the turn-on voltage value of the transistor Q5.

[0022] Figure 3 The circuit for maintaining normal output of the load for micro-interruption of the low-resistance power supply at the input end shown in the figure also includes a voltage stabilizing diode D1, the cathode of the voltage stabilizing diode D1 is connected to the node E, and the anode thereof is connected to the node F. The voltage stabilizing diode D1 plays a role in protecting the MOS tube (or field effect tube) Q1, preventing the voltage between the gate and the source of the MOS tube Q1 from exceeding the rated voltage value (or exceeding the gate and source withstand voltage value of the MOS tube). Specifically, the MOS tube (or field effect tube) Q1 will not be burned out because the voltage between the node E and the node F is too high when the power supply generates a pulse, exceeding the withstand voltage value between the source and the gate of the MOS tube (or field effect tube) Q1. It can also be said that the operating voltage value of the voltage stabilizing diode D1 is greater than the turn-on voltage value of the MOS tube Q1 and less than the maximum rated voltage value between the gate and the source of the MOS tube Q1, wherein the turn-on voltage value of the MOS tube Q1 is less than the maximum rated voltage value between the gate and the source of the MOS tube Q1.

[0023] Figure 3 The circuit shown in the figure for maintaining normal output of a load in response to a slight interruption of a low-resistance power supply at the input end further includes a filter capacitor C1 , one end of the filter capacitor C1 is connected to the node E, and the other end thereof is grounded.

[0024] The following is a detailed introduction Figure 3 The working process of the circuit shown is to maintain the normal output of the load in response to a slight interruption of the low-resistance power supply at the input end.

[0025] When the input power supply terminal Vin is powered normally, the input power flows through the body diode of the field effect tube Q1 (or PMOS transistor Q1), the node E is high level, and the voltage drop between the node A and the node E is less than the turn-on voltage value of the field effect tube Q3 (or PMOS transistor Q3), so the field effect tube Q3 is in the closed (or turned off) state at this time. At this time, the node C is low level, the voltage of the node C is less than the turn-on voltage value of the transistor Q5, and the transistor Q5 is in the closed (or turned off) state. Since the node E is high level, the selection of resistors R3, R7, and R9 needs to meet the following requirements: when the MOS tube Q3 and the transistor Q5 are turned off, the node E is high level, and the voltage of the node D is greater than the turn-on voltage value of the transistor Q4, so the node D is high level at this time, and the voltage of the node D is greater than the turn-on voltage value of the transistor Q4, and the transistor Q4 is in the on state, so that the node G is pulled down, and the resistor R5 is a current limiting resistor, which limits the current flowing through the transistor Q2 and protects the transistor Q2. The resistor R4 is a pull-down resistor, and its purpose is to allow the voltage of node E to pass through the transistor Q2 to the node H. Since the node G is at a low level and the node E is at a high level, the voltage drop between the node E and the node F is greater than the turn-on voltage value of the field effect transistor Q1, so the field effect transistor Q1 is in the on state, and the output power supply terminal Vout is powered by the input power supply terminal Vin through the field effect transistor Q1, and the circuit can work normally. That is to say, when the input power supply terminal Vin is powered normally, the MOS tube Q3 is turned off, the transistor Q2 in the switch control circuit is turned on, the transistor Q4 is turned on, and the transistor Q5 is turned off, so as to control the voltage of the node F so that the MOS tube Q1 is turned on.

[0026] When a micro-interruption occurs in the low-resistance power supply at the input end, the input power supply end Vin is equivalent to a low-value resistor. Due to the presence of the energy storage capacitor C2, when a micro-interruption occurs in the low-resistance power supply at the input end, the node E is still in a high-level state. If the circuit scheme designed by the utility model is not added, at this time, the voltage between the source and the gate (i.e., node E and node F) of the PMOS tube Q1 is still greater than the turn-on voltage value of the PMOS tube Q1, and the conductive channel of the PMOS tube Q1 is still in a conducting state, and the output power supply end Vout will discharge to the input power supply end Vin through the conductive channel of the PMOS tube Q1, thereby causing the output power supply end Vout to lose power quickly, affecting the output of the subsequent circuit. If the circuit scheme designed by the utility model is added, at this time, since the node E is a high level, the input power supply end Vin is equivalent to a low-value resistor, and the selection of resistors R1 and R2 needs to meet the following requirements: when a micro-interruption occurs in the low-resistance power supply at the input end, the voltage value of the voltage divider on the resistor R2 is greater than the turn-on voltage value of the field effect tube Q3, so the field effect tube Q3 is in a conducting state at this time. The selection of resistors R8 and R10 needs to meet the following conditions: when the field effect transistor Q3 is turned on, the voltage of node C is greater than the turn-on voltage of transistor Q5, so node C is at a high level, transistor Q5 is in the on state, and node D is pulled low. Since node D is at a low level, the voltage of node D is less than the turn-on voltage of transistor Q4, and transistor Q4 is in the off (or shut-off) state. At the same time, since the transistor Q2 is in the on state, and since the voltage drop between the emitter and the collector of the transistor is small, the voltage of the node H is approximately equal to the voltage of the node E. Since the transistor Q4 is in the off (or off) state, the voltage of the node F is approximately equal to the voltage of the node H. Therefore, the voltage drop between the node E and the node F is less than the turn-on voltage value of the field effect transistor Q1, so the conductive channel of the field effect transistor Q1 is turned off, so that the charge of the energy storage capacitor C2 at the output power supply terminal Vout will not be discharged to the low resistance part of the power supply terminal through the conduction channel of the PMOS tube Q1, so that the charge on the energy storage capacitor C2 can be used to maintain the product (or load) to continue working within the micro-interruption time range. That is to say, when a micro-interruption occurs at the input power supply terminal Vin, the MOS tube Q3 is turned on, the transistor Q2 in the switch control circuit is turned on, the transistor Q4 is turned off, and the transistor Q5 is turned on, so that the voltage of the node F is controlled to turn off the MOS tube Q1.

[0027] Compared with the prior art, the circuit provided by the utility model for maintaining normal output of loads for micro-interruption of low-resistance power supply at the input end has the following beneficial effects:

[0028] 1. The utility model can close the conductive channel of the PMOS tube Q1 when a micro-interruption occurs at the low-resistance power supply at the input end, so that the charge of the energy storage capacitor C2 in the circuit will not be discharged to the ground of the instantaneous short circuit of the power supply through the conductive channel of the PMOS tube Q1. It is suitable for products with high power and large current that need to maintain operation within the micro-interruption time range.

[0029] 2. When the input power is cut off, the utility model will close the conductive channel of the PMOS tube Q1, which can prevent the charge of the energy storage capacitor C2 from flowing back to the input power terminal Vin.

[0030] 3. When the input power is cut off, the utility model will close the conductive channel of the PMOS tube Q1, so that the charge on the energy storage capacitor C2 is only used to maintain the product working within the micro-interruption time range. While meeting the micro-interruption time requirement, it is beneficial to reduce the capacitance of the energy storage capacitor C2, thereby reducing costs.

[0031] It should be noted that any changes made by those skilled in the art to the specific implementation of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the aforementioned specific implementation.

Claims

1. A power output circuit, characterized in that: It includes MOS tube Q1, MOS tube Q3, resistor R1, resistor R2, switch control circuit and energy storage capacitor C2. The first connection end of the MOS transistor Q1 is connected to the input power supply terminal Vin, the second connection end thereof is connected to the node E, and the control end thereof is connected to the node F; one end of the resistor R1 is connected to the input power supply terminal Vin, and the other end thereof is connected to the node A; one end of the resistor R2 is connected to the node A, and the other end thereof is connected to the node E; the first connection end of the MOS transistor Q3 is connected to the first input end of the switch control circuit, the other end thereof is connected to the node E, and the control end thereof is connected to the node A; the node E is connected to the output power supply terminal Vout, one end of the energy storage capacitor C2 is connected to the output power supply terminal Vout, and the other end thereof is grounded; The second input terminal of the switch control circuit is connected to the node E, and the output terminal of the switch control circuit is connected to the node F. When the input power supply terminal Vin is supplying power normally, the MOS tube Q3 is turned off, and the switch control circuit controls the voltage of the node F to turn on the MOS tube Q1. When a micro interruption occurs at the input power supply terminal Vin, the MOS transistor Q3 is turned on, and the switch control circuit controls the voltage at the node F so that the MOS transistor Q1 is turned off.

2. The power output circuit according to claim 1, characterized in that: The switch control circuit includes transistor Q2, transistor Q4, transistor Q5, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, and resistor R10. One end of the resistor R8 is connected to the first connection end of the MOS transistor Q3 as the first input end of the switch control circuit, and the other end of the resistor R8 is connected to the node C. The first connection end of the transistor Q2 is connected to the node E as the second input end of the switch control circuit, the second connection end is connected to the node H, and the control end is connected to the node B; one end of the resistor R3 is connected to the node E, and the other end is connected to the node B; one end of the resistor R4 is connected to the node H, and the other end is grounded; One end of the resistor R5 is connected to the node H, and the other end thereof is connected to the node G; one end of the resistor R6 is connected to the node F as the output end of the switch control circuit, and the other end thereof is connected to the node G; a first connection end of the transistor Q4 is connected to the node G, a second connection end thereof is grounded, and a control end thereof is connected to the node D; one end of the resistor R9 is connected to the node D, and the other end thereof is grounded; one end of the resistor R7 is connected to the node B, and the other end thereof is connected to the node D; a first connection end of the transistor Q5 is connected to the node D, a second connection end thereof is grounded, and a control end thereof is connected to the node C; one end of the resistor R10 is connected to the node C, and the other end thereof is grounded.

3. The power output circuit according to claim 2, characterized in that: The MOS transistor Q1 is a PMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q1 are respectively the drain, the source and the gate of the PMOS transistor; The MOS transistor Q3 is a PMOS transistor, and the first connection end, the second connection end and the control end of the MOS transistor Q3 are respectively the drain, the source and the gate of the PMOS transistor; The transistor Q2 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q2 are respectively the emitter, the collector and the base of the PNP transistor; The transistor Q4 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q4 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q5 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q5 are respectively the collector, the emitter and the base of the NPN transistor.

4. The power output circuit according to claim 3, characterized in that: When the input power supply terminal Vin is supplying power normally, the MOS tube Q3 is turned off, the transistor Q2 in the switch control circuit is turned on, the transistor Q4 is turned on, and the transistor Q5 is turned off, thereby controlling the voltage of the node F to make the MOS tube Q1 turned on; When a micro-interruption occurs at the input power supply terminal Vin, the MOS tube Q3 is turned on, the transistor Q2 in the switch control circuit is turned on, the transistor Q4 is turned off, and the transistor Q5 is turned on, thereby controlling the voltage of the node F to turn off the MOS tube Q1.

5. The power output circuit according to claim 4, characterized in that: The resistance values ​​of the resistor R3, the resistor R7 and the resistor R9 are selected to satisfy the following conditions: when the MOS transistor Q3 and the transistor Q5 are turned off, the voltage of the node D is greater than the turn-on voltage value of the transistor Q4; The resistance values ​​of the resistor R1 and the resistor R2 are selected to satisfy the following conditions: when a slight power failure occurs at the input power supply terminal Vin, the voltage division value on the resistor R2 is greater than the turn-on voltage value of the MOS tube Q3; The resistance values ​​of the resistor R8 and the resistor R10 are selected to satisfy the following requirement: when the MOS transistor Q3 is turned on, the voltage at the node C is greater than the turn-on voltage value of the transistor Q5.

6. The power output circuit according to claim 1, characterized in that: It also includes a Zener diode D1, The cathode of the voltage stabilizing diode D1 is connected to the node E, and the anode of the voltage stabilizing diode D1 is connected to the node F; The operating voltage value of the voltage stabilizing diode D1 is greater than the turn-on voltage value of the MOS transistor Q1 and less than the maximum rated voltage value between the gate and the source of the MOS transistor Q1; The turn-on voltage value of the MOS transistor Q1 is less than the maximum rated voltage value between the gate and the source of the MOS transistor Q1.

7. The power output circuit according to any one of claims 1 to 6, characterized in that: It also includes filter capacitor C1, One end of the filter capacitor C1 is connected to the node E, and the other end thereof is grounded.

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