Negative logic IPM dipulse test circuit

Abstract

The utility model discloses a negative logic IPM dipulse test circuit, which comprises a first power supply, a signal generator, a first driving IC, an inductor, a second power supply, a capacitor and an IPM, and is characterized in that the positive electrode of the first power supply is connected with the first driving IC, and the negative electrode of the first power supply is connected with the first driving IC and the signal generator; two ends of the signal generator are connected with the first driving IC, the first driving IC is connected with the IPM, and the IPM is connected with the second power supply, the inductor and the capacitor. According to the test circuit provided by the utility model, IPM double-pulse test is realized only by relying on the double-pulse signal of the signal generator, an inverter does not need to be purchased, the required power supply is less, the difficulty and the cost are reduced, and the test circuit is simpler.

Description

Technical Field

[0001] The utility model relates to the technical field of IPM parameter testing, in particular to a negative logic IPM double pulse testing circuit. Background Art

[0002] IPM, that is, Intelligent Power Module, integrates power switching devices and drive circuits, plays an important role in power electronic conversion, and is widely used in fields such as electric vehicles, various inverter power supplies, variable frequency household appliances, servo drives, etc.

[0003] It is very difficult to achieve the reverse double pulse input signal required for negative logic IPM double pulse testing. Currently, each manufacturer uses complex circuits or inverters to achieve it. In addition to using an inverter for testing, in addition to purchasing an inverter, an additional power supply is required to supply power to the inverter. Both methods increase the difficulty and cost of testing.

[0004] In view of this, it is necessary to further improve the current negative logic IPM double pulse testing circuit. Summary of the Utility Model

[0005] Therefore, the purpose of the utility model is to solve at least to a certain extent the deficiencies in the prior art, and thus propose a negative logic IPM double pulse testing circuit.

[0006] To achieve the above purpose, a technical solution adopted by the utility model is:

[0007] The utility model provides a negative logic IPM double pulse testing circuit, including a first power supply, a signal generator, a first drive IC, an inductor, a second power supply, a capacitor and an IPM. The positive pole of the first power supply is connected to the first drive IC, and the negative pole is connected to the first drive IC and the signal generator. Both ends of the signal generator are connected to the first drive IC. The first drive IC is connected to the IPM, and the IPM is connected to the second power supply, the inductor and the capacitor.

[0008] Further, the IPM includes a second drive IC, a first IGBT and a second IGBT. The gate of the first IGBT is connected to the first drive IC, the collector is connected to the positive pole of the capacitor and the second power supply, and the emitter is connected to the collector of the second IGBT and the inductor. The gate of the second IGBT is connected to the second drive IC, the collector and the emitter are connected to both ends of the inductor, and the emitter is also connected to the capacitor and the negative pole of the second power supply.

[0009] Further, it also includes an oscilloscope. The current probe of the oscilloscope for detecting the IC is connected between the collector of the first IGBT and the inductor.

[0010] Further, a first voltage probe of the oscilloscope for detecting the VCE voltage is connected between the collector and the emitter of the first IGBT.

[0011] Further, a second voltage probe of the oscilloscope for detecting the VIN voltage is connected between both ends of the signal generator.

[0012] Further, the first power supply is a low-voltage power supply.

[0013] Further, the second power supply is a high-voltage power supply.

[0014] Further, the capacitor is a high-voltage capacitor.

[0015] Further, the inductor is a load inductor.

[0016] The utility model provides a negative logic IPM dual-pulse test circuit, including a first power supply, a signal generator, a first driving IC, an inductor, a second power supply, a capacitor and an IPM. The positive pole of the first power supply is connected to the first driving IC, and the negative pole is connected to the first driving IC and the signal generator. Both ends of the signal generator are connected to the first driving IC. The first driving IC is connected to the IPM, and the IPM is connected to the second power supply, the inductor and the capacitor. Through the test circuit provided by the utility model, only by relying on the dual-pulse signal of the signal generator, the IPM dual-pulse test can be realized. There is no need to purchase an inverter and less power supply is required. It not only reduces the difficulty and cost, but also makes the test circuit simpler. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0018] Figure 1 It is the circuit schematic diagram of the negative logic IPM dual-pulse test circuit of the present utility model;

[0019] Figure 2 It is the circuit diagram of the traditional test drive signal;

[0020] Figure 3 It is the drive signal circuit diagram of the negative logic IPM dual-pulse test circuit of the present utility model;

[0021] Figure 4It is a schematic diagram of the test waveform of a conventional negative-logic IPM double pulse;

[0022] Figure 5 It is a schematic diagram of the waveform of the negative-logic IPM double-pulse test circuit of the present invention.

[0023] The reference signs in the figure are represented as follows: 1. First power supply; 2. Signal generator; 21. Second voltage probe; 3. First driving IC; 4. Inductor; 5. Second power supply; 6. Capacitor; 7. Second driving IC; 8. First IGBT; 81. First voltage probe; 82. Current probe; 9. Second IGBT. Specific embodiments

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be noted that the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0026] Please refer to Figures 1 to 5 , the present invention provides a negative-logic IPM double-pulse test circuit, including a first power supply 1, a signal generator 2, a first driving IC 3, an inductor 4, a second power supply 5, a capacitor 6 and an IPM. The positive pole of the first power supply 1 is connected to the first driving IC 3, and the negative pole is connected to the first driving IC 3 and the signal generator 2. Both ends of the signal generator 2 are connected to the first driving IC 3. The first driving IC 3 is connected to the IPM, and the IPM is connected to the second power supply 5, the inductor 4 and the capacitor 6.

[0027] At present, the negative-logic IPMs on the market are divided into three structures: Half-bridge (half-bridge structure), 6in1 (three-phase full-bridge structure), and 7in1 (three-phase full-bridge + braking structure). All three IPMs can be tested using the test circuit provided in the embodiments of this application. In addition to double-pulse testing, short-circuit testing can also be completed using the test circuit provided in the embodiments of this application.

[0028] In this embodiment, the negative logic IPM dual-pulse test circuit includes a first power supply 1, a signal generator 2, a first driver IC 3, an inductor 4, a second power supply 5, a capacitor 6, and an IPM. The positive and negative poles of the first power supply 1 are both connected to the first driver IC 3, and the negative pole of the first power supply 1 is also connected to the signal generator 2; both ends of the signal generator 2 are connected to the first driver IC 3; the first driver IC 3 is connected to the IPM, and the IPM is connected to the second power supply 5, the inductor 4, and the capacitor 6. Specifically, the first power supply 1 is used to supply power to the first driver IC 3, the signal generator 2 is used to control the turn-on and turn-off of the IPM, the second power supply 5 and the capacitor 6 are used to provide the bus voltage for the IPM, and the inductor 4 is used to control the rising rate of the current when the IPM is turned on, so as to realize the reverse input signal and realize the dual-pulse test of the IPM.

[0029] Among them, please refer to Figure 2 and Figure 3 , Figure 2 is a traditional test drive signal circuit, Figure 3 is the optimized drive signal circuit in the embodiment of the present application. The traditional test drive signal circuit is composed of an inverter, an inverter power supply, a drive power supply, and a signal generator. The drive signal circuit in the embodiment of the present application is composed of the first power supply 1, the signal generator 2, and the first driver IC 3. Compared with the traditional test drive signal circuit, the drive signal circuit in the embodiment of the present application does not need to purchase an inverter, requires fewer power supplies, and the test circuit is simpler.

[0030] Among them, the first power supply 1 in this embodiment is a low-voltage power supply, the second power supply 5 is a high-voltage power supply, the capacitor 6 is a high-voltage capacitor, and the inductor 4 is a load inductor, and all are conventional models on the market, which are not limited here.

[0031] Furthermore, the IPM includes a second driver IC 7, a first IGBT 8, and a second IGBT 9. The gate of the first IGBT 8 is connected to the first driver IC 3, the collector is connected to the positive pole of the capacitor 6 and the second power supply 5, the emitter is connected to the collector of the second IGBT 9 and the inductor 4, the gate of the second IGBT 9 is connected to the second driver IC 7, the collector and the emitter are connected to both ends of the inductor 4, and the emitter is also connected to the negative pole of the capacitor 6 and the second power supply 5.

[0032] In this embodiment, the IPM includes a second driving IC7, a first IGBT8, and a second IGBT9. The first driving IC7 is connected to the gate of the second IGBT8. The emitter of the second IGBT8 is connected to the inductor 4, the capacitor 6, and the negative electrode of the second power supply 5. The collector of the second IGBT8 is connected to the inductor 4 and the emitter of the first IGBT7. The emitter of the first IGBT7 is also connected to the inductor 4. The gate of the first IGBT7 is connected to the first driving IC3. The collector of the first IGBT7 is connected to the capacitor 6 and the positive electrode of the second power supply 5. Among them, the signal generator 2 is specifically used to control the turn-on and turn-off of the first IGBT7 and the second IGBT8 of the IPM, so as to realize the reverse input signal.

[0033] Further, it also includes an oscilloscope. The current probe 82 of the oscilloscope for detecting the IC is connected between the collector of the first IGBT8 and the inductor 4.

[0034] In this embodiment, the oscilloscope includes a current probe 82. The current probe 82 is used to detect the current IC and is connected between the collector of the first IGBT8 and the inductor 4, and is specifically used to detect the collector current IC at this place.

[0035] Further, the first voltage probe 81 of the oscilloscope for detecting the VCE voltage is connected between the collector and the emitter of the first IGBT8.

[0036] In this embodiment, the oscilloscope further includes a first voltage probe 81. The first voltage probe 81 is arranged between the collector and the emitter of the first IGBT8 and is used to detect the VCE voltage of the IGBT.

[0037] Further, the second voltage probe 21 of the oscilloscope for detecting the VIN voltage is connected between the two ends of the signal generator 2.

[0038] In this embodiment, the oscilloscope further includes a second voltage probe 21. The second voltage probe 21 is connected to the two ends of the signal generator 2 and is used to detect the VIN voltage at this place.

[0039] Specifically, the oscilloscope captures the waveforms at various positions through the current probe 82, the first voltage probe 81, and the second voltage probe 21 to calculate the tested parameters.

[0040] Further, please refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of a conventional double-pulse test wave. When VIN is at a low level, the IGBT is turned on. When it is at a high level, the IGBT is turned off. For a conventional test, VIN needs to be kept high and two low-level pulse signals are output. Figure 5 is a schematic diagram of the double-pulse test waveform in the embodiment of the present application. The specific test method of the test circuit in the embodiment of the present application is as follows:

[0041] At the first rising edge of VIN, the first IGBT7 and the second IGBT8 do not act;

[0042] t 1 At this moment, VIN is at a low level, and the first IGBT7 and the second IGBT8 are turned on simultaneously;

[0043] t 2 At this moment, VIN is at a high level, and the first IGBT7 and the second IGBT8 are turned off simultaneously;

[0044] t 3 At this moment, VIN is at a low level, and the first IGBT7 and the second IGBT8 are turned on simultaneously;

[0045] t 4 At this moment, no high level is given anymore, and the first IGBT7 and the second IGBT8 are not actively turned off;

[0046] At t 5 At this moment, when the collector current IC detected by the current probe of the oscilloscope reaches the IPM short - circuit protection threshold current, the IPM triggers protection and turns off by itself. In this way, only relying on the double - pulse signal of the signal generator, the IPM double - pulse test can be realized.

[0047] The utility model provides a negative - logic IPM double - pulse test circuit, including a first power supply, a signal generator, a first driving IC, an inductor, a second power supply, a capacitor and an IPM. The positive pole of the first power supply is connected to the first driving IC, and the negative pole is connected to the first driving IC and the signal generator. Both ends of the signal generator are connected to the first driving IC. The first driving IC is connected to the IPM, and the IPM is connected to the second power supply, the inductor and the capacitor. Through the test circuit provided by the utility model, only relying on the double - pulse signal of the signal generator, the IPM double - pulse test can be realized, without the need to purchase an inverter and with fewer required power supplies, which not only reduces the difficulty and cost, but also makes the test circuit simpler.

[0048] It should be noted that the various embodiments in the content of the utility model are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0049] It should also be noted that in the content of the present utility model, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0050] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the content of the present utility model. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the content of the present utility model can be implemented in other embodiments without departing from the spirit or scope of the content of the present utility model. Therefore, the content of the present utility model will not be limited to these embodiments shown in the content of the present utility model, but rather to the broadest scope consistent with the principles and novel features disclosed in the content of the present utility model.

Claims

1. A negative logic IPM double pulse test circuit, characterized in that: It includes a first power supply, a signal generator, a first driver IC, an inductor, a second power supply, a capacitor and an IPM, wherein the positive electrode of the first power supply is connected to the first driver IC, the negative electrode is connected to the first driver IC and the signal generator, both ends of the signal generator are connected to the first driver IC, the first driver IC is connected to the IPM, and the IPM is connected to the second power supply, the inductor and the capacitor.

2. The negative logic IPM double pulse test circuit according to claim 1, characterized in that: The IPM includes a second driver IC, a first IGBT and a second IGBT, the gate of the first IGBT is connected to the first driver IC, the collector is connected to the capacitor and the positive electrode of the second power supply, the emitter is connected to the collector of the second IGBT and the inductor, the gate of the second IGBT is connected to the second driver IC, the collector and the emitter are connected to the two ends of the inductor, and the emitter is also connected to the capacitor and the negative electrode of the second power supply.

3. The negative logic IPM double pulse test circuit according to claim 2, characterized in that: An oscilloscope is also included. A current probe of the oscilloscope for detecting the IC is connected between the collector of the first IGBT and the inductor.

4. The negative logic IPM double pulse test circuit according to claim 3, characterized in that: The first voltage probe of the oscilloscope for detecting the VCE voltage is connected between the collector and the emitter of the first IGBT.

5. The negative logic IPM double pulse test circuit according to claim 3, characterized in that: The second voltage probe of the oscilloscope for detecting the VIN voltage is connected between the two ends of the signal generator.

6. The negative logic IPM double pulse test circuit according to claim 1, characterized in that: The first power source is a low voltage power source.

7. The negative logic IPM double pulse test circuit according to claim 1, characterized in that: The second power supply is a high voltage power supply.

8. The negative logic IPM double pulse test circuit according to claim 1, characterized in that: The capacitor is a high voltage capacitor.

9. The negative logic IPM double pulse test circuit according to claim 1, characterized in that: The inductor is a load inductor.

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