Array substrate and liquid crystal display device

Abstract

The utility model discloses an array substrate and a liquid crystal display device. The array substrate comprises a touch control wiring layer, a common electrode layer and via holes. The touch control wiring layer is manufactured through exposure of a mask plate, a touch control wiring pattern is formed, and the touch control wiring pattern comprises a first clearance area and a plurality of first connecting areas; the common electrode layer is manufactured through exposure of a mask, a common electrode pattern is formed, and the common electrode pattern comprises a second connecting area and a plurality of second clearance areas; the first connecting areas are connected with the second connecting areas of the corresponding second patterns through via holes; the second receding area avoids the via hole connecting area and is arranged in the area, corresponding to the touch control wiring pattern, of the common electrode pattern. The non-hollowing processing is performed on the common electrode pattern connected with the touch wiring pattern and the via hole, and the hollowing processing is performed on the other common electrode pattern areas corresponding to the touch wiring pattern, so that the problem of light leakage is avoided, and capacitive coupling between the common electrode layer and the touch wiring layer is also avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and particularly relates to an array substrate and a liquid crystal display device. Background Art

[0002] In recent years, liquid crystal display technology has developed rapidly. Thin Film Transistor-Liquid Crystal Display (hereinafter referred to as TFT-LCD) not only has the advantages of light weight, thin thickness, and low power consumption, but also has excellent characteristics such as high maturity, low radiation, low power consumption, and easy integration. TFT-LCD is widely used in display field electronic products such as televisions and monitors, especially in the display of portable electronic products, such as smart phones and tablets.

[0003] The TFT-LCD display device is thin, light, and has a relatively fast response speed, which has won the favor of consumers. However, due to unreasonable layout of common electrodes and other reasons, the existing display device has a risk of light leakage. The SD layer (referring to the touch wiring layer) is connected to the common electrode layer VITO (also called VCOM) through vias. The common electrode layer VITO is hollowed out here. When there is an alignment deviation in the common electrode layer VITO, or due to differences in device precision, the actual film formation may cause the common electrode layer VITO to deviate left and right, and at this time, light leakage will occur. This reduces the display quality. Summary of the Utility Model

[0004] In the existing TFT-LCD display device, a hollowing-out treatment is performed at the via connection between the common electrode layer and the SD layer, resulting in a problem of light leakage.

[0005] In view of the above problems, an array substrate and a liquid crystal display device are proposed. By not performing a hollowing-out treatment on the common electrode pattern connected to the touch wiring pattern through vias, and performing a hollowing-out treatment on other common electrode pattern areas corresponding to the touch wiring pattern, the problem of light leakage is avoided, and the capacitive coupling between the common electrode layer and the touch wiring layer is also avoided.

[0006] In a first aspect, an array substrate includes:

[0007] A touch wiring layer;

[0008] A common electrode layer;

[0009] Vias;

[0010] The touch wiring layer is formed by using a mask plate for exposure to form a touch wiring pattern, and the touch wiring pattern includes:

[0011] A first clearance area;

[0012] A plurality of first connection areas;

[0013] The common electrode layer is formed by using a mask plate for exposure to form a common electrode pattern, and the common electrode pattern includes:

[0014] A second connection area;

[0015] A plurality of second clearance areas;

[0016] The first connection area is connected to the second connection area of the corresponding second pattern through the via hole;

[0017] The second clearance area avoids the via hole connection area and is arranged in the area of the common electrode pattern corresponding to the touch trace pattern.

[0018] Combined with the array substrate described in the first aspect of the present invention, in the first possible implementation manner, the second clearance area is in a long strip shape and corresponds to the touch trace pattern.

[0019] Combined with the first possible implementation manner of the first aspect of the present invention, in the second possible implementation manner, the array substrate further includes:

[0020] An insulating layer;

[0021] A gate layer;

[0022] A glass substrate;

[0023] The insulating layer is made on the glass substrate;

[0024] The gate layer is made in the insulating layer.

[0025] Combined with the second possible implementation manner of the first aspect of the present invention, in the third possible implementation manner, the array substrate further includes:

[0026] An isolation layer;

[0027] The isolation layer is made on the insulating layer;

[0028] The touch trace layer is made on the isolation layer.

[0029] Combined with the third possible implementation manner of the first aspect of the present invention, in the fourth possible implementation manner, the array substrate further includes:

[0030] A planarization layer;

[0031] The planarization layer is made on the isolation layer;

[0032] The touch trace layer is made in the planarization layer.

[0033] Combined with the fourth possible implementation manner of the first aspect of the present utility model, in the fifth possible implementation manner, the array substrate further includes:

[0034] A passivation layer;

[0035] The passivation layer is fabricated on the planarization layer;

[0036] The common electrode layer is fabricated in the passivation layer.

[0037] Combined with the fifth possible implementation manner of the first aspect of the present utility model, in the sixth possible implementation manner, the array substrate further includes:

[0038] A pixel electrode layer;

[0039] The pixel electrode layer is fabricated on the passivation layer.

[0040] In a second aspect, a liquid crystal display device includes the array substrate described in the first aspect.

[0041] Implementing the array substrate and the liquid crystal display device of the present utility model, by not hollowing out the common electrode pattern connected to the touch trace pattern and hollowing out the other common electrode pattern regions corresponding to the touch trace pattern, both the light leakage problem and the capacitive coupling between the common electrode layer and the touch trace layer are avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic diagram of the film layer structure of the array substrate in the present utility model;

[0044] Figure 2 It is a schematic diagram of the structure of the common electrode layer in the present utility model;

[0045] Figure 3 It is a schematic diagram of the film layer connection structure between the common electrode layer and the touch trace layer in the present utility model;

[0046] The names of the parts referred to by the numbers in the attached drawings are as follows: 100 - glass substrate, 200 - insulating layer, 300 - gate layer, 400 - isolation layer, 500 - planarization layer, 600 - touch wiring layer, 610 - via hole, 620 - first connection area, 700 - common electrode layer, 710 - second connection area, 720 - second clearance area, 800 - passivation layer, 900 - pixel electrode layer. Detailed implementation manners

[0047] Next, the technical solutions in the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0049] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0050] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the attached drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0051] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0052] In the existing TFT-LCD display device, a hollowing treatment is performed at the connection between the common electrode layer 700 (VITO) and the SD layer via hole 610 (CON), resulting in a light leakage problem.

[0053] In view of the above problems, an array substrate 100 and a liquid crystal display device are proposed.

[0054] In a first aspect, as Figure 2 and Figure 3 , Figure 2 is a schematic structural diagram of the common electrode layer 700 (VITO) in the present utility model; Figure 3 is a schematic diagram of the film layer connection structure between the common electrode layer 700 (VITO) and the touch wiring layer 600 (SD) in the present utility model; An array substrate 100 includes a touch wiring layer 600 (SD), a common electrode layer 700 (VITO), and a via hole 610 (CON); The touch wiring layer 600 (SD) is formed by using a mask plate for exposure to form a touch wiring pattern, and the touch wiring pattern includes a first clearance area (not shown in the figure) and a plurality of first connection areas 620; The common electrode layer 700 (VITO) is formed by using a mask plate for exposure to form a common electrode pattern, and the common electrode pattern includes a second connection area 710 and a plurality of second clearance areas 720; The first connection area 620 is connected to the second connection area 710 of the corresponding second pattern through the via hole 610 (CON); The second clearance area 720 avoids the connection area of the via hole 610 (CON) and is arranged in the area of the common electrode pattern corresponding to the touch wiring pattern. By not performing a hollowing treatment on the common electrode pattern connected to the touch wiring pattern and the via hole 610 (CON), and performing a hollowing treatment on other areas of the common electrode pattern corresponding to the touch wiring pattern, both the light leakage problem and the capacitive coupling between the common electrode layer 700 (VITO) and the touch wiring layer 600 (SD) are avoided.

[0055] Preferably, as Figure 2 , the second clearance area 720 is in a strip shape and corresponds to the touch wiring pattern.

[0056] Furthermore, as Figure 1 , Figure 1 is a schematic diagram of the film layer structure of the array substrate 100 in the present utility model; From bottom to top, there are a glass substrate 100, an insulating layer 200, a gate layer 300 (gate), an isolation layer 400, a planarization layer 500, a touch wiring layer 600 (SD), a via hole 610 (CON), a passivation layer 800, a common electrode layer 700 (VITO), and a pixel electrode layer 900.

[0057] The SD (referring to the touch trace here) is connected to the common electrode VITO (also known as VCOM) through the via 610 (CON). VITO is hollowed out here. When there is an alignment deviation of VITO or a difference in device precision, the actual film formation may cause VITO to deviate left or right, and light leakage will occur at this time.

[0058] The common electrode pattern at the connection between the touch trace layer 600 (SD) and the common electrode layer 700 (VITO) is not hollowed out to avoid light leakage. Considering the RC Loading coupling, the common electrode pattern area where the common electrode layer 700 (VITO) is not connected to the touch trace layer 600 (SD) is hollowed out, which reduces the light leakage phenomenon to a certain extent, improves the display effect, and thus enhances the competitiveness of the product. The array substrate 100 further includes an insulating layer 200, a gate layer 300 (gate), and a glass substrate 100; the insulating layer 200 is fabricated on the glass substrate 100; the gate layer 300 (gate) is fabricated in the insulating layer 200.

[0059] Furthermore, as Figure 1 , the array substrate 100 further includes an isolation layer 400; the isolation layer 400 is fabricated on the insulating layer 200; the touch trace layer 600 (SD) is fabricated on the isolation layer 400.

[0060] Furthermore, as Figure 1 , the array substrate 100 further includes a planarization layer 500; the planarization layer 500 is fabricated on the isolation layer 400; the touch trace layer 600 (SD) is fabricated in the planarization layer 500.

[0061] Furthermore, as Figure 1 , the array substrate 100 further includes a passivation layer 800; the passivation layer 800 is fabricated on the planarization layer 500; the common electrode layer 700 (VITO) is fabricated in the passivation layer 800.

[0062] Furthermore, as Figure 1 , the array substrate 100 further includes a pixel electrode layer 900; the pixel electrode layer 900 is fabricated on the passivation layer 800.

[0063] In a second aspect, a liquid crystal display device includes the array substrate 100 of the first aspect.

[0064] Implementing an array substrate 100 and a liquid crystal display device of the present utility model, by not hollowing out the common electrode pattern where the touch trace pattern is connected to the via 610 (CON) and hollowing out the other common electrode pattern areas corresponding to the touch trace pattern, both the light leakage problem is avoided and the capacitive coupling between the common electrode layer 700 (VITO) and the touch trace layer 600 (SD) is avoided.

[0065] The above are only the preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An array substrate, characterized in that: include: Touch control wiring layer; A common electrode layer; Vias; The touch wiring layer is made by exposing with a mask to form a touch wiring pattern, and the touch wiring pattern includes: First air-avoidance area; a plurality of first connection regions; The common electrode layer is made by exposure using a mask to form a common electrode pattern, and the common electrode pattern includes: a second connection region; Multiple secondary air-avoidance areas; The first connection area is connected to the corresponding second connection area of ​​the common electrode pattern through the via hole; The second air avoidance area avoids the via connection area and is arranged in an area of ​​the common electrode pattern corresponding to the touch wiring pattern.

2. The array substrate according to claim 1, characterized in that: The second air avoidance area is in a long strip shape, corresponding to the touch wiring pattern.

3. The array substrate according to claim 2, characterized in that: The array substrate further includes: Insulation layer; Gate layer; Glass substrate; The insulating layer is formed on the glass substrate; The gate layer is formed in the insulating layer.

4. The array substrate according to claim 3, characterized in that: The array substrate further includes: Isolation layer; The isolation layer is formed on the insulating layer; The touch wiring layer is manufactured on the isolation layer.

5. The array substrate according to claim 4, characterized in that: The array substrate further includes: Flat layer; The flat layer is formed on the isolation layer; The touch wiring layer is manufactured in the flat layer.

6. The array substrate according to claim 5, characterized in that: The array substrate further includes: Passivation layer; The passivation layer is formed on the planar layer; The common electrode layer is formed in the passivation layer.

7. The array substrate according to claim 6, characterized in that: The array substrate further includes: A pixel electrode layer; The pixel electrode layer is formed on the passivation layer.

8. A liquid crystal display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

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