Semiconductor device

Abstract

The utility model provides a semiconductor device which can ensure the heat dissipation performance, reduce the impedance of a path and ensure the insulation distance. The semiconductor device includes a semiconductor element on a substrate having a conductive pattern, and the semiconductor element includes a plurality of electrodes provided on a first surface and an electrode provided on a second surface. Each of a plurality of electrodes provided on the first surface is bonded to the conductive pattern of the substrate via a conductive spacer, and an electrode provided on the second surface is bonded to a pad surface of a conductive clip lead.

Description

Technical Field

[0001] The present utility model relates to a semiconductor device. Background Art

[0002] Generally, a semiconductor device is manufactured by electrically connecting a semiconductor element to a circuit board having a metal pattern formed thereon or a lead frame including inner leads and performing resin sealing. In particular, as a representative semiconductor element, a power chip such as a transistor or a diode that processes large power is mainly joined to the metal pattern by soldering in a reflow process. In addition, in the case where there are a power chip and a control chip such as a control IC that does not process large power like the power chip, they are generally separately arranged at different positions on the circuit board or in different regions of the lead frame. In addition, the control chip is sometimes connected not by soldering but by a conductive adhesive.

[0003] Assume that as the use of power chips (hereinafter, also referred to as semiconductor elements or simply chips) expands, they process larger and larger power. At the same time, technologies for improving integration or miniaturization are also developing.

[0004] Regarding the improvement of integration, a technology of flip chip bonding (FCB) is disclosed. FCB is to mount the electrodes on the first surface of a power chip having electrodes on both surfaces on a first substrate, invert it by 180 degrees, and bond the electrodes on the second surface of the power chip to a second substrate (see Patent Document 1). It is known that FCB saves space compared with the conventional wire bonding (WB), and in addition, since the wiring length is shortened and the inductance component is small, it is suitable for high frequencies.

[0005] Regarding miniaturization, as an example of miniaturization of electrodes, a technology of Cu pillars (a plurality of arrangements of bumps (protrusions) in the shape of Cu pillars) is disclosed (see Patent Document 2).

[0006] [Prior Art Documents]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-107506

[0009] [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-151183 Summary of the Utility Model

[0010] [Problems to be Solved by the Utility Model]

[0011] In the case of further improving the integration or miniaturization of semiconductor elements such as power chips that process large power, there are the following three problems.

[0012] First, ensure heat dissipation performance. To prevent thermal damage to semiconductor elements caused by temperature rise due to power loss, sufficient heat dissipation must be achieved.

[0013] Second, reduce the impedance of the path. If the power processed by the semiconductor element increases, since the flowing current (I) increases, assuming that the impedance (Z) of the path connecting the semiconductor elements increases, the power loss (I 2 ×|Z|) on the path increases, leading to heat generation or efficiency degradation. To avoid this, the impedance of the path must be reduced.

[0014] Third, ensure the insulation distance. If the distance between the electrodes (e.g., the first electrode and the second electrode of the semiconductor element) of the semiconductor element becomes smaller due to increased integration or miniaturization, the electrode (e.g., the conductive pattern on the substrate) connected to the first electrode not only approaches the first electrode but also approaches the second electrode. Then, due to minute positional deviations during bonding, etc., it is impossible to ensure the insulation distance between the conductive pattern on the substrate to which the first electrode of the semiconductor element is bonded and the second electrode, and there is a risk of short - circuit or damage to the semiconductor element. To avoid this, the insulation distance must be ensured.

[0015] The present utility model is made to solve the above - mentioned problems, and its object is to provide a semiconductor device that can ensure heat dissipation performance, can reduce the impedance of the path, and can ensure the insulation distance.

[0016] [Technical means for solving the problem]

[0017] To solve the above - mentioned problems, the semiconductor device of the present utility model includes semiconductor elements on a substrate having a conductive pattern. In the semiconductor device, each of the semiconductor elements includes a plurality of electrodes provided on the first surface and an electrode provided on the second surface. Each of the plurality of electrodes provided on the first surface is bonded to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface is bonded to the bonding surface of a conductive clip - type lead.

[0018] For such a semiconductor device, not only can each of the plurality of electrodes provided on the first surface of the semiconductor element be bonded to the conductive pattern of the substrate via a conductive spacer for heat dissipation, but also the electrode provided on the second surface can be bonded to the bonding surface of a conductive clip - type lead for heat dissipation. Therefore, heat can be dissipated through the respective electrodes on both sides of the semiconductor element, and thus sufficient heat dissipation performance can be ensured.

[0019] In addition, in a semiconductor element, each of a plurality of electrodes provided on a first surface is joined to a conductive pattern of a substrate via a conductive spacer, and an electrode provided on a second surface is joined to a solder pad surface of a conductive clip lead. The impedance of the joined path is determined by the shape of the conductive pattern of the substrate or the shape of the solder pad surface of the clip lead, and thus can be arbitrarily adjusted according to the shape. Specifically, since they are all planar, more current can easily flow by expanding the area. That is, by expanding the area, the impedance of the path can be reduced.

[0020] In addition, in a semiconductor element, each of a plurality of electrodes provided on a first surface is joined to a conductive pattern of a substrate via a conductive spacer, so that the distance between each of the plurality of electrodes and the conductive pattern of the substrate can be increased by an amount corresponding to the thickness of the spacer, and an insulation distance can be easily ensured. Furthermore, due to the presence of the spacer, if the gap surrounded by the plurality of electrodes, the spacer, and the conductive pattern becomes wider, an insulating resin material can also be filled in the gap. If the insulating resin material is filled, the insulation performance can be further improved.

[0021] In addition, it is preferable that the clip lead further includes a terminal surface, and the terminal surface is joined to the conductive pattern of the substrate.

[0022] If it is such a planar terminal surface, not only can the terminal surface itself dissipate heat, but furthermore, by joining in surface contact with the conductive pattern, heat can be efficiently transferred from the terminal surface to the conductive pattern for heat dissipation. Furthermore, a planar structure can be provided from the solder pad surface through the terminal surface to the conductive pattern, so that the impedance of the path can be maintained at a low level without reducing the area in the middle.

[0023] In addition, it is preferable that a wiring wire is joined to a surface on the opposite side of the solder pad surface of the clip lead.

[0024] If it is such a structure, heat can be dissipated from the solder pad surface of the clip lead, and even if the connection destination is a position that is difficult to connect through the clip lead (for example, a distant position), the wire can be extended to freely perform wiring.

[0025] In addition, it is preferable that an insulating resist is included around the spacer on the conductive pattern of the substrate, and the semiconductor element and the conductive pattern are joined by solder.

[0026] If it is such a structure, the solder melted on the conductive pattern is blocked by the insulating resist and does not spread outward beyond it. Not only the opposing surfaces of the conductive pattern and the spacer are joined, but also the solder can spread upward in the gap between the inside of the insulating resist and the periphery of the spacer and adhere to the side surface of the spacer, and the semiconductor element and the conductive pattern are joined in a wrapping manner from the lower surface to the side surface of the spacer. Thereby, the semiconductor element and the conductive pattern can be reliably joined.

[0027] In addition, it is preferable that the spacer is a Cu pillar.

[0028] If it is such a Cu pillar, a conductive spacer that can reliably connect multiple electrodes to a conductive pattern can be realized.

[0029] [Effects of the utility model]

[0030] As described above, through the semiconductor device of the present utility model, not only each of the multiple electrodes provided on the first surface is joined to the conductive pattern of the substrate via a conductive spacer and can dissipate heat, but also the electrode provided on the second surface is joined to the solder pad surface of the conductive clip lead and can dissipate heat. Therefore, heat can be dissipated through various electrodes on both sides of the semiconductor element, and thus sufficient heat dissipation performance can be ensured.

[0031] In addition, in the semiconductor element, each of the multiple electrodes provided on the first surface is joined to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface is joined to the solder pad surface of the conductive clip lead. The impedance of the path after joining is determined by the shape of the conductive pattern of the substrate or the shape of the solder pad surface of the clip lead, and thus can be adjusted arbitrarily according to the shape. Specifically, since they are all planar, by widening the width of the surface, more current can easily flow. That is, by widening the width of the surface, the impedance of the path can be reduced.

[0032] In addition, in the semiconductor element, each of the multiple electrodes provided on the first surface is joined to the conductive pattern of the substrate via a conductive spacer. Therefore, the distance between each of the multiple electrodes and the conductive pattern of the substrate can be increased by an amount corresponding to the thickness of the spacer, and the insulation distance can be easily ensured. Furthermore, due to the presence of the spacer, if the gap surrounded by the multiple electrodes, the spacer, and the conductive pattern becomes wider, an insulating resin material can also be filled in the gap. If the insulating resin material is filled, the insulation performance can be further improved. Description of the drawings

[0033] Figure 1 It is a schematic cross-sectional view in the lateral direction of the semiconductor device in the first embodiment of the present utility model.

[0034] Figures 2(a) to 2(d) It is a schematic plan view of the semiconductor device in the first embodiment of the present utility model.

[0035] Figure 3 It is a schematic cross-sectional view in the longitudinal direction of the semiconductor device in the second embodiment of the present utility model.

[0036] Figure 4 It is a schematic plan view of the semiconductor device in another embodiment of the present utility model.

[0037] Figure 5 It is a longitudinal cross-sectional view of a semiconductor device in another embodiment of the present utility model.

[0038] Figure 6 It is a plan view of a semiconductor device in the third embodiment of the present utility model.

[0039] Figure 7 It is a transverse cross-sectional view of a semiconductor device in the third embodiment of the present utility model.

[0040] Figure 8 It is a longitudinal cross-sectional view of a semiconductor device in the third embodiment of the present utility model.

[0041] Figures 9(a) and 9(b) are plan views of a semiconductor device in the fourth embodiment of the present utility model.

[0042] Figure 10 It is a transverse cross-sectional view of a semiconductor device in the fourth embodiment of the present utility model.

[0043] Figures 11(a) to 11(c) It is a schematic diagram of a semiconductor device and a semiconductor element in the fifth embodiment of the present utility model.

[0044] Figures 12(a) to 12(c) It is a schematic diagram of a Cu pillar in the fifth embodiment of the present utility model.

[0045] [Description of symbols]

[0046] 1: Substrate

[0047] 2: Ceramic substrate

[0048] 3a, 3b, 3c, 3d, 3e: Conductive pattern

[0049] 4a, 4b, 4c, 4d, 4e, 4f: Spacer

[0050] 5, 6, 16: Power chip (semiconductor element)

[0051] 7a, 7b, 7c, 8a, 8b, 17a, 17b: Electrode

[0052] 9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, 9l: Solder

[0053] 10, 18: Clip lead

[0054] 11, 20: Solder pad

[0055] 12: Terminal surface

[0056] 13: Lead frame

[0057] 14: Control chip

[0058] 15: Gap

[0059] 19: Conductor

[0060] 21, 22: Insulating resist

[0061] 23: Cu pillar

[0062] 24: Sn plating Detailed implementation mode

[0063] Hereinafter, the present utility model will be described in detail, but the present utility model is not limited thereto.

[0064] As described above, in order to further improve the integration degree or miniaturize a semiconductor element for processing large power, a semiconductor device capable of ensuring heat dissipation performance, reducing the impedance of a path, and ensuring an insulation distance is required.

[0065] The creator of the present utility model has repeatedly made efforts in research, and as a result, it has been found that by studying the bonding structure of the electrodes of the semiconductor element, the above problems can be solved, and thus the present utility model has been completed.

[0066] That is, the present utility model is a semiconductor device including a semiconductor element on a substrate having a conductive pattern. In the semiconductor device, the semiconductor element includes a plurality of electrodes provided on a first surface and an electrode provided on a second surface. Each of the plurality of electrodes provided on the first surface is bonded to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface is bonded to the solder pad surface of a conductive clip lead.

[0067] Hereinafter, description will be made with reference to the drawings.

[0068] Here, the substrate is not particularly limited as long as it has a conductive pattern formed on its surface, and it may be a substrate having a metal pattern formed on its back surface or a multilayer substrate. For example, a direct bonding copper (DBC) substrate can be used.

[0069] The conductive pattern is not particularly limited as long as it can bond solder, and it may be a copper pattern.

[0070] The solder is not particularly limited as long as it can fix the semiconductor element. For example, lead-free solder can be used.

[0071] The solder is not particularly limited and can be pre-printed and bonded by heating and melting in a reflow process.

[0072] The semiconductor element is not particularly limited, but may also be a power chip such as a diode or a transistor. In addition, an Insulated Gate Bipolar Transistor (IGBT) or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) may be used.

[0073] The electrode is not particularly limited as long as it has conductivity and can be joined by solder, and may also be Cu or Al.

[0074] The conductive spacer is not particularly limited as long as it has conductivity and can be joined by solder. It may be made of Cu or may be a Cu pillar. Further, it may also be plating, and in the case of plating, it may be plating such as Sn.

[0075] The conductive clip lead is not particularly limited as long as it has conductivity and can be joined by solder, and may also be a metal plate such as Cu, Al, stainless steel (SUS), Fe, or other alloys.

[0076] [First Embodiment]

[0077] Refer to Figures 1 to 2(d) The first embodiment of the present utility model will be described. Figure 1 It is a schematic cross-sectional view of the semiconductor device in the lateral direction, Figures 2(a) to 2(d) and is a schematic plan view. Figures 2(a) to 2(d) In [the figure], in order to easily and understandably show the constituent members, it is shown based on the manufacturing steps of the semiconductor device as Figures 2(a) to 2(d) . Here, Figure 1 is a cross-sectional view taken along line A-A of FIG. 2(c).

[0078] As Figure 1 shown, the semiconductor device in the present embodiment includes semiconductor elements 5 and 6 on a substrate 1 having a conductive pattern. In the semiconductor device, in particular, the semiconductor element 5 includes a plurality of electrodes 7a and 7b provided on the first surface and an electrode 7c provided on the second surface. Each of the plurality of electrodes 7a and 7b provided on the first surface is joined to the conductive patterns 3a and 3b of the substrate 1 via conductive spacers 4a and 4b, and the electrode 7c provided on the second surface is joined to the solder pad surface 11 of the conductive clip lead 10.

[0079] In the case of such a semiconductor device, the semiconductor element 5 is not only disposed such that each of the plurality of electrodes 7a and 7b on the first surface is joined to the conductive patterns 3a and 3b of the substrate 1 via the conductive spacers 4a and 4b, and heat can be dissipated through the entire substrate 1, but also the electrode 7c on the second surface is joined to the solder pad surface 11 of the conductive clip lead 10, and heat can be dissipated through the entire clip lead 10. Therefore, heat can be dissipated over a wide range via the respective electrodes 7a to 7c on both surfaces of the semiconductor element 5, and thus sufficient heat dissipation performance can be ensured.

[0080] In addition, in the semiconductor element 5, each of the plurality of electrodes 7a and 7b provided on the first surface is joined to the conductive patterns 3a and 3b of the substrate 1 via the conductive spacers 4a and 4b, and the electrode 7c provided on the second surface is joined to the solder pad surface 11 of the conductive clip lead 10. The impedance of the joined path is determined by the shapes of the conductive patterns 3a and 3b of the substrate 1 or the solder pad surface 11 of the clip lead 10, and thus can be arbitrarily adjusted according to the shape. Specifically, since they are all planar, more current can easily flow by increasing the area. In particular, as clearly shown in Figures 1 to 3 , the area of the conductive pattern 3a or the solder pad surface 11 of the clip lead 10 is set to be wider than that of the semiconductor element 5. In this way, more current can easily flow by increasing the area, and the impedance of the path can be reduced.

[0081] In addition, in the semiconductor element 5, referring to Figure 1 , each of the plurality of electrodes 7a and 7b provided on the first surface is joined to the conductive patterns 3a and 3b of the substrate via the conductive spacers 4a and 4b. Therefore, the distance between each of the plurality of electrodes 7a and 7b and the conductive patterns 3a and 3b of the substrate can be increased by an amount corresponding to the thickness of the spacers 4a and 4b, and the insulation distance (in this case, particularly the insulation distance between the electrode 7a and the conductive pattern 3b that should not be joined, and the insulation distance between the electrode 7b and the conductive pattern 3a) can be easily ensured. For example, when the semiconductor element 5 is mounted on the substrate 1, even if the semiconductor element 5 is slightly offset in the Figure 1 left - right direction with respect to the substrate 1, since there is a distance in the up - down direction (the thickness direction of the spacers 4a and 4b), the insulation distance can be ensured. Furthermore, due to the presence of the spacers 4a and 4b, the gap 15 surrounded by the plurality of electrodes 7a, 7b, spacers 4a, 4b, and conductive patterns 3a, 3b becomes wider. Even if the electrodes 7a and 7b approach each other due to increased integration or miniaturization, as long as the gap 15 is widened, an insulating resin material can be filled in the gap 15. If the insulating resin material is filled, the insulation performance can be further improved.

[0082] Next, with reference to Figures 2(a) to 2(d) the steps of manufacturing the semiconductor device will be described. First, FIG. 2(a) is a diagram of the step of preparing a substrate. The substrate 1 has conductive patterns 3a to 3d and the like on the upper surface of the ceramic base material 2. In addition, there are also a plurality of conductive patterns on the right side of the conductive patterns 3a to 3d, but if all are labeled with symbols, it becomes very difficult to understand, so they are omitted. In addition, the substrate 1 also has a conductive pattern 3e on the lower surface (refer to Figure 1 , Figure 3 ).

[0083] Next, FIG. 2(b) is a diagram of the step of mounting power chips (semiconductor elements) 5 and power chips (semiconductor elements) 6 on the substrate 1 via conductive spacers 4a to 4c (refer to Figure 1 , Figure 3 ). In addition, there are also 5 sets of power chips on the right side of the power chips 5 and 6, but the symbols are omitted. In addition, originally, the underlying patterns and the like are not visible by arranging elements on the pattern, etc., but here, for the sake of clarifying the positional relationship, the structure is shown as visible in its entirety (the same applies to FIGS. 2(c) and 2(d)). Here, the power chip 5 is an IGBT and has two electrodes 7a and 7b on the first surface (the surface facing the substrate 1). The wider one is the source electrode 7a and the narrower one is the gate electrode 7b, which are respectively joined to the conductive patterns 3a and 3b via the spacers 4a and 4b. The power chip 6 is a diode and has one electrode 8a on the first surface (the surface facing the substrate 1), which is joined to the conductive pattern 3a via the spacer 4c. Here, solders 9a to 9c are used for joining.

[0084] Next, FIG. 2(c) is a diagram of the step of mounting a conductive clip lead 10. As Figure 3 shown, the solder pads 11 of the clip lead 10 are joined to the electrodes 7c and 8b provided on the second surface of the power chips 5 and 6 by solders 9d and 9e. In addition, the clip lead 10 also includes a terminal surface 12, and the terminal surface 12 is joined to the conductive pattern 3d of the substrate by solder 9f.

[0085] Next, FIG. 2(d) is a diagram of the step of integrating the substrate 1 and the lead frame 13 to complete the semiconductor device. A control chip 14 is mounted on the lead frame 13. Since the control chip 14 does not process such a large amount of power, wiring between the control chip 14 and the substrate 1 is performed by WB (wire bonding).

[0086] [Second Embodiment]

[0087] Figure 3is a longitudinal sectional view and is a sectional view taken along line B-B of Fig. 2(c). Other parts are the same as those of the embodiment, but as Figure 3 shown, the clip lead 10 further includes a terminal surface 12, and the terminal surface 12 is joined to the conductive pattern 3d of the substrate by solder 9f.

[0088] For the clip lead 10 having the planar terminal surface 12, not only can the terminal surface 12 itself dissipate heat, but also, by being joined to the conductive pattern 3d in surface contact, heat can be efficiently transferred from the terminal surface 12 to the conductive pattern 3d for heat dissipation. Further, a wide planar structure can be provided from the solder surface 11 via the terminal surface 12 to the conductive pattern 3d. Therefore, for example, the impedance of the path can be maintained at a low level without reducing the area due to a narrow cross-sectional area of a wire or the like in the middle.

[0089] In addition, in the present embodiment, the semiconductor elements 5 and 6 are assumed to be of a general silicon type and are composed of two chips, an IGBT and a diode, but it is not limited thereto.

[0090] As another embodiment, for example, a SiC type IGBT may sometimes be composed of only one chip. Refer to Figure 4 、 Figure 5 for an example of one chip. Figure 4 is a plan view, Figure 5 is a longitudinal sectional view.

[0091] The semiconductor element 16 is one chip and is a SiC type IGBT. Compared with the two chips (semiconductor elements 5 and 6 in Fig. 2(b)), in Figure 4 it has a shape extending in the vertical direction along the plane of the paper in one chip. Also, in the longitudinal section, compared with the two chips in Figure 3 , in the one chip in Figure 5 , the shapes of the electrode 17a on the first surface (the surface facing the substrate 1) of the semiconductor element 16, the electrode 17b on the second surface, the spacer 4d, the solder 9g, the solder 9h, etc. are different. Here, the transverse sectional view is the same as that in Figure 1 and is thus omitted. However, even for one chip, when there are two electrodes on the first surface (the surface facing the substrate 1) for joining to the conductive patterns 3a and 3b, the situation remains the same, and thus there is the same problem as in the case of two chips, which can be solved by the same means as in the case of two chips.

[0092] [Third Embodiment]

[0093] Refer to Figures 6 to 8 for a description of the third embodiment of the present utility model. Figure 6 is a plan schematic view. Figure 7is a schematic cross-sectional view in the horizontal direction and is Figure 6 a cross-sectional view of the E-E section of Figure 8 is a schematic cross-sectional view in the vertical direction and is Figure 6 a cross-sectional view of the F-F section of

[0094] The difference between the third embodiment and the second embodiment is that the clip lead 18 has a flat shape when viewed from the side, has no terminal surface, and has a wire 19.

[0095] Specifically, one end of the wire 19 for wiring is joined by solder 9i on the surface opposite to the solder pad surface 20 of the clip lead 18, and the other end of the wire 19 is joined to the conductive pattern 3d by solder 9j. In addition, the wire 19 can also be ultrasonically wire-bonded to a thick wire such as aluminum without using the solder 9i and the solder 9j.

[0096] If such a structure is adopted, heat can be dissipated from the solder pad surface 20 of the clip lead 18, and even if the connection destination is a position that is difficult to connect by the clip lead (for example, a distant position), the other end of the wire 19 can be extended to freely perform wiring.

[0097] [Fourth Embodiment]

[0098] Refer to FIGS. 9(a), 9(b), Figure 10 to describe the fourth embodiment of the present invention. FIGS. 9(a) and 9(b) are plan views, Figure 10 and are cross-sectional views in the horizontal direction.

[0099] The difference between the fourth embodiment and the first embodiment is that it has an insulating resist. FIG. 9(a) is an enlarged view of the substrate 1 and is a view obtained by enlarging the lower left part of FIG. 2(a) of the first embodiment. Different from the first embodiment, FIG. 9(b) is coated with an insulating resist 21 and an insulating resist 22 so as to surround a part of the regions on the conductive pattern 3a and the conductive pattern 3b, and spacers 4a and 4b are arranged in the regions surrounded by the insulating resist 21 and the insulating resist 22 and are joined by solder 9k and solder 9l.

[0100] In other words, around the spacers 4a and 4b on the conductive pattern 3a and the conductive pattern 3b of the substrate 1, there are an insulating resist 21 and an insulating resist 22, and the semiconductor element 5 is joined to the conductive pattern 3a and the conductive pattern 3b by solder 9k and solder 9l.

[0101] In such a structure, the solder 9k and solder 9l melted on the conductive patterns 3a and 3b are blocked by the insulating resist 21 and insulating resist 22 and do not spread outward beyond them. Not only are the facing surfaces of the conductive patterns 3a and 3b joined to the spacers 4a and 4b, but it can also spread upward in the gap between the inside of the insulating resist 21 and insulating resist 22 and the periphery of the spacers 4a and 4b, and also adhere to the sides of the spacers 4a and 4b. As a result, it is joined in a wrapping manner from the lower surface to the sides of the spacers 4a and 4b. Thereby, the semiconductor element 5 can be reliably joined to the conductive patterns 3a and 3b.

[0102] In addition, the fourth embodiment can of course be applied to the second embodiment and the third embodiment.

[0103] [Fifth Embodiment]

[0104] Refer to Figures 11(a) to 11(c) 、 Figures 12(a) to 12(c) The fifth embodiment of the present utility model will be described. Figures 11(a) to 11(c) is a schematic diagram of a semiconductor device and a semiconductor element, Figures 12(a) to 12(c) is a schematic diagram of a representative Cu pillar.

[0105] The difference between the fifth embodiment and the first embodiment is that Cu pillars are used as spacers. Fig. 11(a) is an enlarged view of the substrate 1 and is an enlarged view of the lower left part of Fig. 2(b) of the first embodiment. Fig. 11(b) is a schematic diagram of the semiconductor element 5 of the first embodiment. The upper figure is a figure obtained by reversing the semiconductor element 5 of Fig. 11(a) in the left-right direction, and the lower figure is a C-C cross-sectional view of the upper figure. On the electrodes 7a and 7b of the semiconductor element 5, one spacer 4a and one spacer 4b having a bottom shape substantially the same as that of the electrodes 7a and 7b are formed on each electrode. In this case, the number of electrodes is the same as the number of spacers (both are two). On the other hand, Fig. 11(c) is a structural diagram of the semiconductor element 5 using Cu pillars in this embodiment, and the lower figure is a D-D cross-sectional view of the upper figure. Compared with Fig. 11(b), the semiconductor element 5 and the electrodes 7a and 7b have the same structure, but the spacers 4e and 4f are composed of a much larger number of Cu pillars than the number of electrodes. Specifically, the spacer 4e on the electrode 7a has 159 Cu pillars, and the spacer 4f on the electrode 7b has 12 Cu pillars.

[0106] As described above, the spacers 4e and 4f in this embodiment are Cu pillars.

[0107] In the case of such Cu pillars, the conductive spacers 4e and 4f that can reliably connect the plurality of electrodes 7a and 7b to the conductive patterns 3a and 3b can be realized.

[0108] Particularly, in the case where the electrodes 7a and 7b are joined to the conductive patterns 3a and 3b by solder, the solder enters the gaps of the Cu pillars of the spacers 4e and 4f, which can make the joint stronger.

[0109] Figures 12(a) to 12(c) It is a diagram schematically showing the shape of a representative Cu pillar. Fig. 12(a) is a trapezoidal shape, Fig. 12(b) is a dome shape, and Fig. 12(c) is a diagram showing the Sn plating 24 for surface protection being applied to the upper part of the Cu pillar 23 formed by Cu plating. The Sn plating 24 has the effects of preventing Cu oxidation and being easily fused with solder.

[0110] In addition, the fifth embodiment can of course be applied to the second embodiment, the third embodiment, and the fourth embodiment.

[0111] The present utility model includes the following forms. [1]:

[0113] A semiconductor device includes semiconductor elements on a substrate having conductive patterns. The semiconductor device is characterized in that the semiconductor elements include a plurality of electrodes provided on a first surface and an electrode provided on a second surface. Each of the plurality of electrodes provided on the first surface is joined to the conductive pattern of the substrate via a conductive spacer, and the electrode provided on the second surface is joined to the solder pad surface of a conductive clip lead. [2]:

[0115] According to the semiconductor device described in [1] above, the clip lead further includes a terminal surface, and the terminal surface is joined to the conductive pattern of the substrate. [3]:

[0117] According to the semiconductor device described in [1] above, a wire for wiring is joined to a surface on the opposite side of the solder pad surface of the clip lead. [4]:

[0119] According to the semiconductor device according to any one of [1] to [3] above, an insulating resist is included around the spacer on the conductive pattern of the substrate, and the semiconductor element and the conductive pattern are joined by solder. [5]:

[0121] According to the semiconductor device according to any one of [1] to [4] above, the spacer is a Cu pillar.

[0122] In addition, the present utility model is not limited to the described embodiments. The described embodiments are illustrative, and any one having a structure substantially the same as the technical idea described in the claims of the present utility model and achieving the same function and effect is included in the technical scope of the present utility model.

Claims

1. A semiconductor device, characterized in that: A semiconductor element is included on a substrate having a conductive pattern, The semiconductor element includes a plurality of electrodes arranged on a first surface and an electrode arranged on a second surface. Each of the plurality of electrodes arranged on the first surface is joined to the conductive pattern of the substrate via a conductive spacer, and the electrode arranged on the second surface is joined to a pad surface of a conductive clip lead.

2. The semiconductor device according to claim 1, wherein: The clip lead further includes a terminal surface that is bonded to the conductive pattern of the substrate.

3. The semiconductor device according to claim 1, wherein: A wiring conductor is bonded to a surface of the clip lead opposite to the pad surface.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that An insulating resist is included around the spacer on the conductive pattern of the substrate, and the semiconductor element and the conductive pattern are bonded to each other by solder.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that The spacer is a Cu column.

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